From 1c966dd26b2e46a9d089fcb7e36f649000670e64 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Tue, 17 Sep 2013 21:12:42 -0700 Subject: [PATCH] drm/i915: Fix HSW parity test MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Haswell changed the log registers to be WO, so we can no longer read them to determine the programming (which sucks, see later note). For now, simply use the cached value, and hope HW doesn't screw us over. v2: Simplify the logic to avoid an extra !, remove last, and fix the buffer offset which broke along the rebase (Ville) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441 CC: Ville Syrjälä Signed-off-by: Ben Widawsky Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_sysfs.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index d572435cfbe7..71f6de24444e 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -133,6 +133,17 @@ i915_l3_read(struct file *filp, struct kobject *kobj, if (ret) return ret; + if (IS_HASWELL(drm_dev)) { + if (dev_priv->l3_parity.remap_info) + memcpy(buf, + dev_priv->l3_parity.remap_info + (offset/4), + count); + else + memset(buf, 0, count); + + goto out; + } + misccpctl = I915_READ(GEN7_MISCCPCTL); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); @@ -141,9 +152,10 @@ i915_l3_read(struct file *filp, struct kobject *kobj, I915_WRITE(GEN7_MISCCPCTL, misccpctl); +out: mutex_unlock(&drm_dev->struct_mutex); - return i; + return count; } static ssize_t -- 2.20.1