From 17b96cc38d93c65b3bf4e88ce89cc550dc90abf7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 23 Apr 2010 03:53:42 +1000 Subject: [PATCH] drm/nv50: output calculated crtc pll when debugging on Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nv50_crtc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index cfabeb974a56..41fe8aec0a12 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c @@ -279,6 +279,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) return ret; if (limits.vco2.maxfreq) { + NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n", + pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P); + reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00; reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00; nv_wr32(dev, pll_reg, 0x10000611); @@ -286,6 +289,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) nv_wr32(dev, pll_reg + 8, reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2); } else { + NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n", + pclk, ret, pll.N1, pll.M1, pll.log2P); + reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000; nv_wr32(dev, pll_reg, 0x50000610); nv_wr32(dev, pll_reg + 4, reg1 | -- 2.20.1