From 152ebb44eff3c2dae0fb7d5b19c3f65e7c8d3493 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Fri, 21 Mar 2014 18:43:59 +0800 Subject: [PATCH] MIPS: Loongson: Add basic Loongson-3 definition Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan Tested-by: Alex Smith Reviewed-by: Alex Smith Cc: John Crispin Cc: Steven J. Hill Cc: Aurelien Jarno Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang Cc: Zhangjin Wu Patchwork: https://patchwork.linux-mips.org/patch/6629/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu.h | 5 +++-- arch/mips/include/asm/mach-loongson/spaces.h | 9 +++++++++ arch/mips/include/asm/module.h | 2 ++ arch/mips/include/asm/pgtable-bits.h | 9 +++++++++ 4 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/spaces.h diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 01d757c83201..530eb8b3a68e 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -231,6 +231,7 @@ #define PRID_REV_LOONGSON1B 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 +#define PRID_REV_LOONGSON3A 0x0005 /* * Older processors used to encode processor version and revision in two @@ -304,8 +305,8 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, - CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, + CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, + CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_LAST }; diff --git a/arch/mips/include/asm/mach-loongson/spaces.h b/arch/mips/include/asm/mach-loongson/spaces.h new file mode 100644 index 000000000000..e2506ee90044 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/spaces.h @@ -0,0 +1,9 @@ +#ifndef __ASM_MACH_LOONGSON_SPACES_H_ +#define __ASM_MACH_LOONGSON_SPACES_H_ + +#if defined(CONFIG_64BIT) +#define CAC_BASE _AC(0x9800000000000000, UL) +#endif /* CONFIG_64BIT */ + +#include +#endif diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h index 44b705d08262..c2edae382d5d 100644 --- a/arch/mips/include/asm/module.h +++ b/arch/mips/include/asm/module.h @@ -126,6 +126,8 @@ search_module_dbetables(unsigned long addr) #define MODULE_PROC_FAMILY "LOONGSON1 " #elif defined CONFIG_CPU_LOONGSON2 #define MODULE_PROC_FAMILY "LOONGSON2 " +#elif defined CONFIG_CPU_LOONGSON3 +#define MODULE_PROC_FAMILY "LOONGSON3 " #elif defined CONFIG_CPU_CAVIUM_OCTEON #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_XLR diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 32aea4852fb0..e592f3687d6f 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -235,6 +235,15 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) +#elif defined(CONFIG_CPU_LOONGSON3) + +/* Using COHERENT flag for NONCOHERENT doesn't hurt. */ + +#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ +#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */ + #else #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */ -- 2.20.1