From 120b56a2a7a262c0940299615c7bcf97d3982711 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jul 2017 23:42:31 +0300 Subject: [PATCH] drm/i915/gen2: Add an ID for the display pipes power well MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Make the I830 power well ID assignment explicit for consistency. v2: - s/GEN2/I830/ in the comment, since other GEN2s don't have the power well. (Ville) Cc: Ville Syrjälä Signed-off-by: Imre Deak Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-2-imre.deak@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index aee40eecf688..ef0c1a86a52f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1072,6 +1072,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) * power wells their value must stay fixed. */ enum i915_power_well_id { + /* + * I830 + * - custom power well + */ + I830_DISP_PW_PIPES = 0, + /* * VLV/CHV * - PUNIT_REG_PWRGT_CTRL (bit: id*2), diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index bbade8a5918f..c36ec160b79f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2036,6 +2036,7 @@ static struct i915_power_well i830_power_wells[] = { .name = "pipes", .domains = I830_PIPES_POWER_DOMAINS, .ops = &i830_pipes_power_well_ops, + .id = I830_DISP_PW_PIPES, }, }; -- 2.20.1