From 0f2fa40e464c955e928979331625b5485c292bf0 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Wed, 23 Jan 2013 11:27:58 +0100 Subject: [PATCH] ARM: mach-ux500: enable 128KB way L2 cache on DB8540 DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540. Fix this by modifying ux500_l2x0_init() to use 128KB way size for all cpus in the x540 family. Signed-off-by: Maxime Coquelin Acked-by: Linus Walleij Signed-off-by: Fabio Baltieri Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cache-l2x0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 1c1609da76ce..f815efe54c73 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void) /* Unlock before init */ ux500_l2x0_unlock(); - /* DB9540's L2 has 128KB way size */ - if (cpu_is_u9540()) + /* DBx540's L2 has 128KB way size */ + if (cpu_is_ux540_family()) /* 128KB way size */ aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); else -- 2.20.1