From 0f1dfd520fdf66cee6bbb5a15f2c2363f3132421 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 17 Apr 2017 17:10:11 -0400 Subject: [PATCH] drm/amdgpu/gfx9: move SET_RESOURCES into the same command stream As the KCQ setup. This way we only have to wait once for the entire MEC. Acked-by: Tom St Denis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 73 +++++---------------------- 1 file changed, 14 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 139243fee58e..455d87522030 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2490,59 +2490,7 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); } -static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) -{ - struct amdgpu_device *adev = ring->adev; - uint32_t scratch, tmp = 0; - int r, i; - - r = amdgpu_gfx_scratch_get(adev, &scratch); - if (r) { - DRM_ERROR("Failed to get scratch reg (%d).\n", r); - return r; - } - WREG32(scratch, 0xCAFEDEAD); - - r = amdgpu_ring_alloc(ring, 8); - if (r) { - DRM_ERROR("Failed to lock KIQ (%d).\n", r); - amdgpu_gfx_scratch_free(adev, scratch); - return r; - } - amdgpu_ring_alloc(ring, 11); - /* set resources */ - amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); - amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | - PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ - amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */ - amdgpu_ring_write(ring, 0); /* queue mask hi */ - amdgpu_ring_write(ring, 0); /* gws mask lo */ - amdgpu_ring_write(ring, 0); /* gws mask hi */ - amdgpu_ring_write(ring, 0); /* oac mask */ - amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */ - /* write to scratch for completion */ - amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); - amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); - amdgpu_ring_write(ring, 0xDEADBEEF); - amdgpu_ring_commit(ring); - - for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32(scratch); - if (tmp == 0xDEADBEEF) - break; - DRM_UDELAY(1); - } - if (i >= adev->usec_timeout) { - DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n", - scratch, tmp); - r = -EINVAL; - } - amdgpu_gfx_scratch_free(adev, scratch); - - return r; -} - -static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev) +static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; uint32_t scratch, tmp = 0; @@ -2555,13 +2503,23 @@ static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev) } WREG32(scratch, 0xCAFEDEAD); - r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 3); + r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); if (r) { DRM_ERROR("Failed to lock KIQ (%d).\n", r); amdgpu_gfx_scratch_free(adev, scratch); return r; } + /* set resources */ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); + amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | + PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ + amdgpu_ring_write(kiq_ring, 0x000000FF); /* queue mask lo */ + amdgpu_ring_write(kiq_ring, 0); /* queue mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* oac mask */ + amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ for (i = 0; i < adev->gfx.num_compute_rings; i++) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); @@ -2848,7 +2806,6 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; struct v9_mqd *mqd = ring->mqd_ptr; int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; - int r; gfx_v9_0_kiq_setting(ring); @@ -2879,9 +2836,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) mutex_unlock(&adev->srbm_mutex); } - r = gfx_v9_0_kiq_enable(ring); - - return r; + return 0; } static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) @@ -2953,7 +2908,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) goto done; } - r = gfx_v9_0_map_queues_enable(adev); + r = gfx_v9_0_kiq_kcq_enable(adev); done: return r; } -- 2.20.1