From 0e47b5981a30e856c9c4aba785890528486d1594 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 2 Mar 2016 23:57:09 +0100 Subject: [PATCH] pwm: lpc18xx-sct: Test clock rate to avoid division by 0 The clk API may return 0 on clk_get_rate(), so we should check the result before using it as a divisor. Signed-off-by: Wolfram Sang Acked-by: Joachim Eastwood Signed-off-by: Thierry Reding --- drivers/pwm/pwm-lpc18xx-sct.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c index 9163085101bc..9861fed4e67d 100644 --- a/drivers/pwm/pwm-lpc18xx-sct.c +++ b/drivers/pwm/pwm-lpc18xx-sct.c @@ -360,6 +360,11 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev) } lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk); + if (!lpc18xx_pwm->clk_rate) { + dev_err(&pdev->dev, "pwm clock has no frequency\n"); + ret = -EINVAL; + goto disable_pwmclk; + } mutex_init(&lpc18xx_pwm->res_lock); mutex_init(&lpc18xx_pwm->period_lock); -- 2.20.1