From 0d95e11b7e27536dbb52c42a8bb5a6f31d7c24cf Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Mon, 31 Mar 2014 18:21:27 +0300 Subject: [PATCH] drm/i915: Warn when DPIO read returns 0xffffffff MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit DPIO reads from groups/broadcast register offsets for PCS and TX return all 1's. If that result gets used for something we'll probably end up doing something wrong. So warn when that happens. FIXME there might be some registers where all 1's is a valid value, so ideally we should check the register offset instead... Signed-off-by: Ville Syrjälä Reviewed-by: Jesse Barnes [danvet: copypaste the FIXME comment into the code.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_sideband.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 0954f132726e..b1a5514e695a 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -182,6 +182,14 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)), DPIO_OPCODE_REG_READ, reg, &val); + + /* + * FIXME: There might be some registers where all 1's is a valid value, + * so ideally we should check the register offset instead... + */ + WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n", + pipe_name(pipe), reg, val); + return val; } -- 2.20.1