From 03d6582fc5d9bcea384a74777e1d2e481730f5a4 Mon Sep 17 00:00:00 2001 From: Kyungwoo Kang Date: Wed, 28 Mar 2018 06:43:09 +0900 Subject: [PATCH] [COMMON] serial: samsung: Fix UART driver SW sequence This patch fixes two potential sequential sw hole. a. flush fifo after channel enable b. change div setting after enable AFC Change-Id: I559baba34fb4fd77fb26ddb7d9d8da3762cf5e86 Signed-off-by: Kyungwoo Kang --- drivers/tty/serial/samsung.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index b94200b33d4c..50b39725b3ba 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1014,6 +1014,9 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, wr_regl(port, S3C2410_ULCON, ulcon); wr_regl(port, S3C2410_UBRDIV, quot); + if (ourport->info->has_divslot) + wr_regl(port, S3C2443_DIVSLOT, udivslot); + umcon = rd_regl(port, S3C2410_UMCON); if (termios->c_cflag & CRTSCTS) { umcon |= S3C2410_UMCOM_AFC; @@ -1024,9 +1027,6 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, } wr_regl(port, S3C2410_UMCON, umcon); - if (ourport->info->has_divslot) - wr_regl(port, S3C2443_DIVSLOT, udivslot); - dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", rd_regl(port, S3C2410_ULCON), rd_regl(port, S3C2410_UCON), @@ -1347,14 +1347,14 @@ static void s3c24xx_serial_resetport(struct uart_port *port, ucon |= S3C2443_UCON_LOOPBACK; } - wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); - /* reset both fifos */ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); wr_regl(port, S3C2410_UFCON, cfg->ufcon); /* some delay is required after fifo reset */ udelay(1); + + wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); } /* s3c24xx_serial_init_port -- 2.20.1