From 037bde19a43e299d30f0490bba9be32ab355975c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 27 Mar 2014 08:24:19 +0000 Subject: [PATCH] Revert "drm/i915: Disable/Enable PM Intrrupts based on the current freq." MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This reverts commit 2754436913b94626a5414d82f0996489628c513d. Conflicts: drivers/gpu/drm/i915/i915_irq.c The partial application of interrupt masking without regard to other pathways for adjusting the RPS frequency results in completely disabling the PM interrupts. This leads to excessive power consumption as the GPU is kept at max clocks (until the failsafe mechanism fires of explicitly downclocking the GPU when all requests are idle). Or equally as bad for the UX, the GPU is kept at minimum clocks and prevented from upclocking in response to a requirement for more power. Testcase: pm_rps/blocking Cc: Deepak S Cc: Ville Syrjälä Cc: Daniel Vetter Signed-off-by: Chris Wilson Reviewed-by:Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 3 --- drivers/gpu/drm/i915/i915_irq.c | 38 --------------------------------- drivers/gpu/drm/i915/intel_pm.c | 8 ------- 3 files changed, 49 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 537404b9f760..8d10f220e044 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1001,9 +1001,6 @@ struct intel_gen6_power_mgmt { u8 rp1_freq; /* "less than" RP0 power/freqency */ u8 rp0_freq; /* Non-overclocked max frequency. */ - bool rp_up_masked; - bool rp_down_masked; - int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f5a74b70f5e5..72e26e2be301 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1084,43 +1084,6 @@ static void notify_ring(struct drm_device *dev, i915_queue_hangcheck(dev); } -void gen6_set_pm_mask(struct drm_i915_private *dev_priv, - u32 pm_iir, int new_delay) -{ - if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { - if (new_delay >= dev_priv->rps.max_freq_softlimit) { - /* Mask UP THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) | - GEN6_PM_RP_UP_THRESHOLD); - dev_priv->rps.rp_up_masked = true; - } - if (dev_priv->rps.rp_down_masked) { - /* UnMask DOWN THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) & - ~GEN6_PM_RP_DOWN_THRESHOLD); - dev_priv->rps.rp_down_masked = false; - } - } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { - if (new_delay <= dev_priv->rps.min_freq_softlimit) { - /* Mask DOWN THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) | - GEN6_PM_RP_DOWN_THRESHOLD); - dev_priv->rps.rp_down_masked = true; - } - - if (dev_priv->rps.rp_up_masked) { - /* UnMask UP THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) & - ~GEN6_PM_RP_UP_THRESHOLD); - dev_priv->rps.rp_up_masked = false; - } - } -} - static void gen6_pm_rps_work(struct work_struct *work) { drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, @@ -1180,7 +1143,6 @@ static void gen6_pm_rps_work(struct work_struct *work) dev_priv->rps.min_freq_softlimit, dev_priv->rps.max_freq_softlimit); - gen6_set_pm_mask(dev_priv, pm_iir, new_delay); dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; if (IS_VALLEYVIEW(dev_priv->dev)) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b66a43b90d1b..f702ac8a2f50 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3095,11 +3095,6 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, I915_READ(VLV_GTLC_SURVIVABILITY_REG) & ~VLV_GFX_CLK_FORCE_ON_BIT); - - /* Unmask Up interrupts */ - dev_priv->rps.rp_up_masked = true; - gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD, - dev_priv->rps.min_freq_softlimit); } void gen6_rps_idle(struct drm_i915_private *dev_priv) @@ -3688,9 +3683,6 @@ static void valleyview_enable_rps(struct drm_device *dev) valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); - dev_priv->rps.rp_up_masked = false; - dev_priv->rps.rp_down_masked = false; - gen6_enable_rps_interrupts(dev); gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); -- 2.20.1