drm/i915/bdw: Support eDP PSR
authorBen Widawsky <benjamin.widawsky@intel.com>
Tue, 5 Nov 2013 06:45:05 +0000 (22:45 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Nov 2013 17:10:00 +0000 (18:10 +0100)
commited8546ac1f99b850879f07b1e9b06b42fb0a36d9
treeac9dd66748341d1ea59869d869d631e71e864e4d
parent2a114cc1b964ba0208aa6858d01cee82ac026ec6
drm/i915/bdw: Support eDP PSR

Broadwell PSR support is a superset of Haswell. With this simple
register base calculation, everything that worked on HSW for eDP PSR
should work on BDW.

Note that Broadwell provides additional PSR support. This is not
addressed at this time.

v2: Make the HAS_PSR include BDW

v3: Use the correct offset (I had incorrectly used one from my faulty
brain) (Art!)

v4: It helps if you git add

v5: Be explicit about not setting min link entry time for BDW. This
should be no functional change over v4 (Jani)

Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dp.c