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(parent: e0a3862) | patch
clk: mediatek: Add MT2701 clock support
authorShunli Wang <shunli.wang@mediatek.com>
Fri, 4 Nov 2016 07:43:05 +0000 (15:43 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 8 Nov 2016 23:59:49 +0000 (15:59 -0800)
commite9862118272aa528e35e54ef9f1e35c217870fd7
tree8dc89a1e94dfef635dab7ac98d423cda5247627atree | snapshot (tar.gz zip)
parente0a3862c14f80e34d5787f1e038601da8ff9cc77commit | diff
clk: mediatek: Add MT2701 clock support

Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 files changed:
drivers/clk/mediatek/Kconfig diff | blob | blame | history
drivers/clk/mediatek/Makefile diff | blob | blame | history
drivers/clk/mediatek/clk-gate.c diff | blob | blame | history
drivers/clk/mediatek/clk-gate.h diff | blob | blame | history
drivers/clk/mediatek/clk-mt2701-bdp.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mt2701-eth.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mt2701-hif.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mt2701-img.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mt2701-mm.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mt2701-vdec.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mt2701.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mtk.c diff | blob | blame | history
drivers/clk/mediatek/clk-mtk.h diff | blob | blame | history
drivers/clk/mediatek/clk-pll.c diff | blob | blame | history