clk: samsung: register exynos5420 apll/kpll configuration data
authorThomas Abraham <thomas.ab@samsung.com>
Mon, 14 Jul 2014 13:38:34 +0000 (19:08 +0530)
committerTomasz Figa <t.figa@samsung.com>
Sat, 26 Jul 2014 00:50:15 +0000 (02:50 +0200)
commitca5b4029382245397dd6829c6321121cab1a1471
tree50b327d18f7d33b64b277a8dd009c14f932b043c
parente9d529562a8ca5f293032f5aca3060eeb9c406bb
clk: samsung: register exynos5420 apll/kpll configuration data

Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: Arjun K.V <arjun.kv@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
drivers/clk/samsung/clk-exynos5420.c