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MIPS: Emulate the BC1{EQ,NE}Z FPU instructions
authorMarkos Chandras <markos.chandras@imgtec.com>
Wed, 26 Nov 2014 10:10:18 +0000 (10:10 +0000)
committerMarkos Chandras <markos.chandras@imgtec.com>
Tue, 17 Feb 2015 15:37:32 +0000 (15:37 +0000)
commitc8a34581ec09a5ee11dd833d6c5cf41fdbef706f
treeae78d1cc82562dfa92bcad4bcc7848343af21dc7tree | snapshot (tar.gz zip)
parent319824eabc3f1c1aab67f408d66f384fbb996ee2commit | diff
MIPS: Emulate the BC1{EQ,NE}Z FPU instructions

MIPS R6 introduced the following two branch instructions for COP1:

BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero
BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/include/uapi/asm/inst.h diff | blob | blame | history
arch/mips/kernel/branch.c diff | blob | blame | history
arch/mips/math-emu/cp1emu.c diff | blob | blame | history
Motorola kernel-slsi