c0436b85
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] /
1 /*
2 * SAMSUNG EXYNOS5420 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
19
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21
22 / {
23 compatible = "samsung,exynos5420", "samsung,exynos5";
24
25 aliases {
26 mshc0 = &mmc_0;
27 mshc1 = &mmc_1;
28 mshc2 = &mmc_2;
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
34 i2c0 = &i2c_0;
35 i2c1 = &i2c_1;
36 i2c2 = &i2c_2;
37 i2c3 = &i2c_3;
38 i2c4 = &hsi2c_4;
39 i2c5 = &hsi2c_5;
40 i2c6 = &hsi2c_6;
41 i2c7 = &hsi2c_7;
42 i2c8 = &hsi2c_8;
43 i2c9 = &hsi2c_9;
44 i2c10 = &hsi2c_10;
45 gsc0 = &gsc_0;
46 gsc1 = &gsc_1;
47 spi0 = &spi_0;
48 spi1 = &spi_1;
49 spi2 = &spi_2;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a15";
61 reg = <0x0>;
62 clock-frequency = <1800000000>;
63 };
64
65 cpu1: cpu@1 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <0x1>;
69 clock-frequency = <1800000000>;
70 };
71
72 cpu2: cpu@2 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a15";
75 reg = <0x2>;
76 clock-frequency = <1800000000>;
77 };
78
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a15";
82 reg = <0x3>;
83 clock-frequency = <1800000000>;
84 };
85
86 cpu4: cpu@100 {
87 device_type = "cpu";
88 compatible = "arm,cortex-a7";
89 reg = <0x100>;
90 clock-frequency = <1000000000>;
91 };
92
93 cpu5: cpu@101 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a7";
96 reg = <0x101>;
97 clock-frequency = <1000000000>;
98 };
99
100 cpu6: cpu@102 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a7";
103 reg = <0x102>;
104 clock-frequency = <1000000000>;
105 };
106
107 cpu7: cpu@103 {
108 device_type = "cpu";
109 compatible = "arm,cortex-a7";
110 reg = <0x103>;
111 clock-frequency = <1000000000>;
112 };
113 };
114
115 sysram@02020000 {
116 compatible = "mmio-sram";
117 reg = <0x02020000 0x54000>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 ranges = <0 0x02020000 0x54000>;
121
122 smp-sysram@0 {
123 compatible = "samsung,exynos4210-sysram";
124 reg = <0x0 0x1000>;
125 };
126
127 smp-sysram@53000 {
128 compatible = "samsung,exynos4210-sysram-ns";
129 reg = <0x53000 0x1000>;
130 };
131 };
132
133 clock: clock-controller@10010000 {
134 compatible = "samsung,exynos5420-clock";
135 reg = <0x10010000 0x30000>;
136 #clock-cells = <1>;
137 };
138
139 clock_audss: audss-clock-controller@3810000 {
140 compatible = "samsung,exynos5420-audss-clock";
141 reg = <0x03810000 0x0C>;
142 #clock-cells = <1>;
143 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
144 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
145 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
146 };
147
148 mfc: codec@11000000 {
149 compatible = "samsung,mfc-v7";
150 reg = <0x11000000 0x10000>;
151 interrupts = <0 96 0>;
152 clocks = <&clock CLK_MFC>;
153 clock-names = "mfc";
154 samsung,power-domain = <&mfc_pd>;
155 };
156
157 mmc_0: mmc@12200000 {
158 compatible = "samsung,exynos5420-dw-mshc-smu";
159 interrupts = <0 75 0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <0x12200000 0x2000>;
163 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
164 clock-names = "biu", "ciu";
165 fifo-depth = <0x40>;
166 status = "disabled";
167 };
168
169 mmc_1: mmc@12210000 {
170 compatible = "samsung,exynos5420-dw-mshc-smu";
171 interrupts = <0 76 0>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 reg = <0x12210000 0x2000>;
175 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
176 clock-names = "biu", "ciu";
177 fifo-depth = <0x40>;
178 status = "disabled";
179 };
180
181 mmc_2: mmc@12220000 {
182 compatible = "samsung,exynos5420-dw-mshc";
183 interrupts = <0 77 0>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 reg = <0x12220000 0x1000>;
187 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
188 clock-names = "biu", "ciu";
189 fifo-depth = <0x40>;
190 status = "disabled";
191 };
192
193 mct: mct@101C0000 {
194 compatible = "samsung,exynos4210-mct";
195 reg = <0x101C0000 0x800>;
196 interrupt-controller;
197 #interrups-cells = <1>;
198 interrupt-parent = <&mct_map>;
199 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
200 <8>, <9>, <10>, <11>;
201 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
202 clock-names = "fin_pll", "mct";
203
204 mct_map: mct-map {
205 #interrupt-cells = <1>;
206 #address-cells = <0>;
207 #size-cells = <0>;
208 interrupt-map = <0 &combiner 23 3>,
209 <1 &combiner 23 4>,
210 <2 &combiner 25 2>,
211 <3 &combiner 25 3>,
212 <4 &gic 0 120 0>,
213 <5 &gic 0 121 0>,
214 <6 &gic 0 122 0>,
215 <7 &gic 0 123 0>,
216 <8 &gic 0 128 0>,
217 <9 &gic 0 129 0>,
218 <10 &gic 0 130 0>,
219 <11 &gic 0 131 0>;
220 };
221 };
222
223 gsc_pd: power-domain@10044000 {
224 compatible = "samsung,exynos4210-pd";
225 reg = <0x10044000 0x20>;
226 };
227
228 isp_pd: power-domain@10044020 {
229 compatible = "samsung,exynos4210-pd";
230 reg = <0x10044020 0x20>;
231 };
232
233 mfc_pd: power-domain@10044060 {
234 compatible = "samsung,exynos4210-pd";
235 reg = <0x10044060 0x20>;
236 };
237
238 disp_pd: power-domain@100440C0 {
239 compatible = "samsung,exynos4210-pd";
240 reg = <0x100440C0 0x20>;
241 };
242
243 mau_pd: power-domain@100440E0 {
244 compatible = "samsung,exynos4210-pd";
245 reg = <0x100440E0 0x20>;
246 };
247
248 g2d_pd: power-domain@10044100 {
249 compatible = "samsung,exynos4210-pd";
250 reg = <0x10044100 0x20>;
251 };
252
253 msc_pd: power-domain@10044120 {
254 compatible = "samsung,exynos4210-pd";
255 reg = <0x10044120 0x20>;
256 };
257
258 pinctrl_0: pinctrl@13400000 {
259 compatible = "samsung,exynos5420-pinctrl";
260 reg = <0x13400000 0x1000>;
261 interrupts = <0 45 0>;
262
263 wakeup-interrupt-controller {
264 compatible = "samsung,exynos4210-wakeup-eint";
265 interrupt-parent = <&gic>;
266 interrupts = <0 32 0>;
267 };
268 };
269
270 pinctrl_1: pinctrl@13410000 {
271 compatible = "samsung,exynos5420-pinctrl";
272 reg = <0x13410000 0x1000>;
273 interrupts = <0 78 0>;
274 };
275
276 pinctrl_2: pinctrl@14000000 {
277 compatible = "samsung,exynos5420-pinctrl";
278 reg = <0x14000000 0x1000>;
279 interrupts = <0 46 0>;
280 };
281
282 pinctrl_3: pinctrl@14010000 {
283 compatible = "samsung,exynos5420-pinctrl";
284 reg = <0x14010000 0x1000>;
285 interrupts = <0 50 0>;
286 };
287
288 pinctrl_4: pinctrl@03860000 {
289 compatible = "samsung,exynos5420-pinctrl";
290 reg = <0x03860000 0x1000>;
291 interrupts = <0 47 0>;
292 };
293
294 rtc: rtc@101E0000 {
295 clocks = <&clock CLK_RTC>;
296 clock-names = "rtc";
297 status = "disabled";
298 };
299
300 amba {
301 #address-cells = <1>;
302 #size-cells = <1>;
303 compatible = "arm,amba-bus";
304 interrupt-parent = <&gic>;
305 ranges;
306
307 adma: adma@03880000 {
308 compatible = "arm,pl330", "arm,primecell";
309 reg = <0x03880000 0x1000>;
310 interrupts = <0 110 0>;
311 clocks = <&clock_audss EXYNOS_ADMA>;
312 clock-names = "apb_pclk";
313 #dma-cells = <1>;
314 #dma-channels = <6>;
315 #dma-requests = <16>;
316 };
317
318 pdma0: pdma@121A0000 {
319 compatible = "arm,pl330", "arm,primecell";
320 reg = <0x121A0000 0x1000>;
321 interrupts = <0 34 0>;
322 clocks = <&clock CLK_PDMA0>;
323 clock-names = "apb_pclk";
324 #dma-cells = <1>;
325 #dma-channels = <8>;
326 #dma-requests = <32>;
327 };
328
329 pdma1: pdma@121B0000 {
330 compatible = "arm,pl330", "arm,primecell";
331 reg = <0x121B0000 0x1000>;
332 interrupts = <0 35 0>;
333 clocks = <&clock CLK_PDMA1>;
334 clock-names = "apb_pclk";
335 #dma-cells = <1>;
336 #dma-channels = <8>;
337 #dma-requests = <32>;
338 };
339
340 mdma0: mdma@10800000 {
341 compatible = "arm,pl330", "arm,primecell";
342 reg = <0x10800000 0x1000>;
343 interrupts = <0 33 0>;
344 clocks = <&clock CLK_MDMA0>;
345 clock-names = "apb_pclk";
346 #dma-cells = <1>;
347 #dma-channels = <8>;
348 #dma-requests = <1>;
349 };
350
351 mdma1: mdma@11C10000 {
352 compatible = "arm,pl330", "arm,primecell";
353 reg = <0x11C10000 0x1000>;
354 interrupts = <0 124 0>;
355 clocks = <&clock CLK_MDMA1>;
356 clock-names = "apb_pclk";
357 #dma-cells = <1>;
358 #dma-channels = <8>;
359 #dma-requests = <1>;
360 };
361 };
362
363 i2s0: i2s@03830000 {
364 compatible = "samsung,exynos5420-i2s";
365 reg = <0x03830000 0x100>;
366 dmas = <&adma 0
367 &adma 2
368 &adma 1>;
369 dma-names = "tx", "rx", "tx-sec";
370 clocks = <&clock_audss EXYNOS_I2S_BUS>,
371 <&clock_audss EXYNOS_I2S_BUS>,
372 <&clock_audss EXYNOS_SCLK_I2S>;
373 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
374 samsung,idma-addr = <0x03000000>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2s0_bus>;
377 status = "disabled";
378 };
379
380 i2s1: i2s@12D60000 {
381 compatible = "samsung,exynos5420-i2s";
382 reg = <0x12D60000 0x100>;
383 dmas = <&pdma1 12
384 &pdma1 11>;
385 dma-names = "tx", "rx";
386 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
387 clock-names = "iis", "i2s_opclk0";
388 pinctrl-names = "default";
389 pinctrl-0 = <&i2s1_bus>;
390 status = "disabled";
391 };
392
393 i2s2: i2s@12D70000 {
394 compatible = "samsung,exynos5420-i2s";
395 reg = <0x12D70000 0x100>;
396 dmas = <&pdma0 12
397 &pdma0 11>;
398 dma-names = "tx", "rx";
399 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
400 clock-names = "iis", "i2s_opclk0";
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2s2_bus>;
403 status = "disabled";
404 };
405
406 spi_0: spi@12d20000 {
407 compatible = "samsung,exynos4210-spi";
408 reg = <0x12d20000 0x100>;
409 interrupts = <0 66 0>;
410 dmas = <&pdma0 5
411 &pdma0 4>;
412 dma-names = "tx", "rx";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&spi0_bus>;
417 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
418 clock-names = "spi", "spi_busclk0";
419 status = "disabled";
420 };
421
422 spi_1: spi@12d30000 {
423 compatible = "samsung,exynos4210-spi";
424 reg = <0x12d30000 0x100>;
425 interrupts = <0 67 0>;
426 dmas = <&pdma1 5
427 &pdma1 4>;
428 dma-names = "tx", "rx";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&spi1_bus>;
433 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
434 clock-names = "spi", "spi_busclk0";
435 status = "disabled";
436 };
437
438 spi_2: spi@12d40000 {
439 compatible = "samsung,exynos4210-spi";
440 reg = <0x12d40000 0x100>;
441 interrupts = <0 68 0>;
442 dmas = <&pdma0 7
443 &pdma0 6>;
444 dma-names = "tx", "rx";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&spi2_bus>;
449 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
450 clock-names = "spi", "spi_busclk0";
451 status = "disabled";
452 };
453
454 uart_0: serial@12C00000 {
455 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
456 clock-names = "uart", "clk_uart_baud0";
457 };
458
459 uart_1: serial@12C10000 {
460 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
461 clock-names = "uart", "clk_uart_baud0";
462 };
463
464 uart_2: serial@12C20000 {
465 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
466 clock-names = "uart", "clk_uart_baud0";
467 };
468
469 uart_3: serial@12C30000 {
470 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
471 clock-names = "uart", "clk_uart_baud0";
472 };
473
474 pwm: pwm@12dd0000 {
475 compatible = "samsung,exynos4210-pwm";
476 reg = <0x12dd0000 0x100>;
477 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
478 #pwm-cells = <3>;
479 clocks = <&clock CLK_PWM>;
480 clock-names = "timers";
481 };
482
483 dp_phy: video-phy@10040728 {
484 compatible = "samsung,exynos5250-dp-video-phy";
485 reg = <0x10040728 4>;
486 #phy-cells = <0>;
487 };
488
489 dp: dp-controller@145B0000 {
490 clocks = <&clock CLK_DP1>;
491 clock-names = "dp";
492 phys = <&dp_phy>;
493 phy-names = "dp";
494 };
495
496 fimd: fimd@14400000 {
497 samsung,power-domain = <&disp_pd>;
498 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
499 clock-names = "sclk_fimd", "fimd";
500 };
501
502 adc: adc@12D10000 {
503 compatible = "samsung,exynos-adc-v2";
504 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
505 interrupts = <0 106 0>;
506 clocks = <&clock CLK_TSADC>;
507 clock-names = "adc";
508 #io-channel-cells = <1>;
509 io-channel-ranges;
510 status = "disabled";
511 };
512
513 i2c_0: i2c@12C60000 {
514 compatible = "samsung,s3c2440-i2c";
515 reg = <0x12C60000 0x100>;
516 interrupts = <0 56 0>;
517 #address-cells = <1>;
518 #size-cells = <0>;
519 clocks = <&clock CLK_I2C0>;
520 clock-names = "i2c";
521 pinctrl-names = "default";
522 pinctrl-0 = <&i2c0_bus>;
523 status = "disabled";
524 };
525
526 i2c_1: i2c@12C70000 {
527 compatible = "samsung,s3c2440-i2c";
528 reg = <0x12C70000 0x100>;
529 interrupts = <0 57 0>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 clocks = <&clock CLK_I2C1>;
533 clock-names = "i2c";
534 pinctrl-names = "default";
535 pinctrl-0 = <&i2c1_bus>;
536 status = "disabled";
537 };
538
539 i2c_2: i2c@12C80000 {
540 compatible = "samsung,s3c2440-i2c";
541 reg = <0x12C80000 0x100>;
542 interrupts = <0 58 0>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 clocks = <&clock CLK_I2C2>;
546 clock-names = "i2c";
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c2_bus>;
549 status = "disabled";
550 };
551
552 i2c_3: i2c@12C90000 {
553 compatible = "samsung,s3c2440-i2c";
554 reg = <0x12C90000 0x100>;
555 interrupts = <0 59 0>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 clocks = <&clock CLK_I2C3>;
559 clock-names = "i2c";
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c3_bus>;
562 status = "disabled";
563 };
564
565 hsi2c_4: i2c@12CA0000 {
566 compatible = "samsung,exynos5-hsi2c";
567 reg = <0x12CA0000 0x1000>;
568 interrupts = <0 60 0>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c4_hs_bus>;
573 clocks = <&clock CLK_I2C4>;
574 clock-names = "hsi2c";
575 status = "disabled";
576 };
577
578 hsi2c_5: i2c@12CB0000 {
579 compatible = "samsung,exynos5-hsi2c";
580 reg = <0x12CB0000 0x1000>;
581 interrupts = <0 61 0>;
582 #address-cells = <1>;
583 #size-cells = <0>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c5_hs_bus>;
586 clocks = <&clock CLK_I2C5>;
587 clock-names = "hsi2c";
588 status = "disabled";
589 };
590
591 hsi2c_6: i2c@12CC0000 {
592 compatible = "samsung,exynos5-hsi2c";
593 reg = <0x12CC0000 0x1000>;
594 interrupts = <0 62 0>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&i2c6_hs_bus>;
599 clocks = <&clock CLK_I2C6>;
600 clock-names = "hsi2c";
601 status = "disabled";
602 };
603
604 hsi2c_7: i2c@12CD0000 {
605 compatible = "samsung,exynos5-hsi2c";
606 reg = <0x12CD0000 0x1000>;
607 interrupts = <0 63 0>;
608 #address-cells = <1>;
609 #size-cells = <0>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&i2c7_hs_bus>;
612 clocks = <&clock CLK_I2C7>;
613 clock-names = "hsi2c";
614 status = "disabled";
615 };
616
617 hsi2c_8: i2c@12E00000 {
618 compatible = "samsung,exynos5-hsi2c";
619 reg = <0x12E00000 0x1000>;
620 interrupts = <0 87 0>;
621 #address-cells = <1>;
622 #size-cells = <0>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&i2c8_hs_bus>;
625 clocks = <&clock CLK_I2C8>;
626 clock-names = "hsi2c";
627 status = "disabled";
628 };
629
630 hsi2c_9: i2c@12E10000 {
631 compatible = "samsung,exynos5-hsi2c";
632 reg = <0x12E10000 0x1000>;
633 interrupts = <0 88 0>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&i2c9_hs_bus>;
638 clocks = <&clock CLK_I2C9>;
639 clock-names = "hsi2c";
640 status = "disabled";
641 };
642
643 hsi2c_10: i2c@12E20000 {
644 compatible = "samsung,exynos5-hsi2c";
645 reg = <0x12E20000 0x1000>;
646 interrupts = <0 203 0>;
647 #address-cells = <1>;
648 #size-cells = <0>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&i2c10_hs_bus>;
651 clocks = <&clock CLK_I2C10>;
652 clock-names = "hsi2c";
653 status = "disabled";
654 };
655
656 hdmi: hdmi@14530000 {
657 compatible = "samsung,exynos5420-hdmi";
658 reg = <0x14530000 0x70000>;
659 interrupts = <0 95 0>;
660 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
661 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
662 <&clock CLK_MOUT_HDMI>;
663 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
664 "sclk_hdmiphy", "mout_hdmi";
665 phy = <&hdmiphy>;
666 status = "disabled";
667 };
668
669 hdmiphy: hdmiphy@145D0000 {
670 reg = <0x145D0000 0x20>;
671 };
672
673 mixer: mixer@14450000 {
674 compatible = "samsung,exynos5420-mixer";
675 reg = <0x14450000 0x10000>;
676 interrupts = <0 94 0>;
677 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
678 clock-names = "mixer", "sclk_hdmi";
679 };
680
681 gsc_0: video-scaler@13e00000 {
682 compatible = "samsung,exynos5-gsc";
683 reg = <0x13e00000 0x1000>;
684 interrupts = <0 85 0>;
685 clocks = <&clock CLK_GSCL0>;
686 clock-names = "gscl";
687 samsung,power-domain = <&gsc_pd>;
688 };
689
690 gsc_1: video-scaler@13e10000 {
691 compatible = "samsung,exynos5-gsc";
692 reg = <0x13e10000 0x1000>;
693 interrupts = <0 86 0>;
694 clocks = <&clock CLK_GSCL1>;
695 clock-names = "gscl";
696 samsung,power-domain = <&gsc_pd>;
697 };
698
699 pmu_system_controller: system-controller@10040000 {
700 compatible = "samsung,exynos5420-pmu", "syscon";
701 reg = <0x10040000 0x5000>;
702 };
703
704 tmu_cpu0: tmu@10060000 {
705 compatible = "samsung,exynos5420-tmu";
706 reg = <0x10060000 0x100>;
707 interrupts = <0 65 0>;
708 clocks = <&clock CLK_TMU>;
709 clock-names = "tmu_apbif";
710 };
711
712 tmu_cpu1: tmu@10064000 {
713 compatible = "samsung,exynos5420-tmu";
714 reg = <0x10064000 0x100>;
715 interrupts = <0 183 0>;
716 clocks = <&clock CLK_TMU>;
717 clock-names = "tmu_apbif";
718 };
719
720 tmu_cpu2: tmu@10068000 {
721 compatible = "samsung,exynos5420-tmu-ext-triminfo";
722 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
723 interrupts = <0 184 0>;
724 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
725 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
726 };
727
728 tmu_cpu3: tmu@1006c000 {
729 compatible = "samsung,exynos5420-tmu-ext-triminfo";
730 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
731 interrupts = <0 185 0>;
732 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
733 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
734 };
735
736 tmu_gpu: tmu@100a0000 {
737 compatible = "samsung,exynos5420-tmu-ext-triminfo";
738 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
739 interrupts = <0 215 0>;
740 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
741 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
742 };
743
744 watchdog: watchdog@101D0000 {
745 compatible = "samsung,exynos5420-wdt";
746 reg = <0x101D0000 0x100>;
747 interrupts = <0 42 0>;
748 clocks = <&clock CLK_WDT>;
749 clock-names = "watchdog";
750 samsung,syscon-phandle = <&pmu_system_controller>;
751 };
752
753 sss: sss@10830000 {
754 compatible = "samsung,exynos4210-secss";
755 reg = <0x10830000 0x10000>;
756 interrupts = <0 112 0>;
757 clocks = <&clock 471>;
758 clock-names = "secss";
759 samsung,power-domain = <&g2d_pd>;
760 };
761
762 usbdrd3_0: usb@12000000 {
763 compatible = "samsung,exynos5250-dwusb3";
764 clocks = <&clock CLK_USBD300>;
765 clock-names = "usbdrd30";
766 #address-cells = <1>;
767 #size-cells = <1>;
768 ranges;
769
770 dwc3 {
771 compatible = "snps,dwc3";
772 reg = <0x12000000 0x10000>;
773 interrupts = <0 72 0>;
774 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
775 phy-names = "usb2-phy", "usb3-phy";
776 };
777 };
778
779 usbdrd_phy0: phy@12100000 {
780 compatible = "samsung,exynos5420-usbdrd-phy";
781 reg = <0x12100000 0x100>;
782 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
783 clock-names = "phy", "ref";
784 samsung,pmu-syscon = <&pmu_system_controller>;
785 #phy-cells = <1>;
786 };
787
788 usbdrd3_1: usb@12400000 {
789 compatible = "samsung,exynos5250-dwusb3";
790 clocks = <&clock CLK_USBD301>;
791 clock-names = "usbdrd30";
792 #address-cells = <1>;
793 #size-cells = <1>;
794 ranges;
795
796 dwc3 {
797 compatible = "snps,dwc3";
798 reg = <0x12400000 0x10000>;
799 interrupts = <0 73 0>;
800 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
801 phy-names = "usb2-phy", "usb3-phy";
802 };
803 };
804
805 usbdrd_phy1: phy@12500000 {
806 compatible = "samsung,exynos5420-usbdrd-phy";
807 reg = <0x12500000 0x100>;
808 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
809 clock-names = "phy", "ref";
810 samsung,pmu-syscon = <&pmu_system_controller>;
811 #phy-cells = <1>;
812 };
813 };