drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+
authorChris Wilson <chris@chris-wilson.co.uk>
Sat, 9 Apr 2016 09:57:53 +0000 (10:57 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Sat, 9 Apr 2016 11:08:53 +0000 (12:08 +0100)
commit9b9ed3093613288247a27a55a6dd07f1222150f1
treeeef209b9bf3d813b9f37dadf47a73a3cb483ac99
parent782f6bc0aba037436d6a04d19b23f8b61020a576
drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+

In order to ensure seqno/irq coherency, we currently read a ring register.
The mmio transaction following the interrupt delays the inspection of
the seqno long enough for the MI_STORE_DWORD_IMM to update the CPU
cache. However, it is only the memory timing that is important for the
purposes of the delay, we do not need nor desire the extra forcewake.

v3: Update commentary

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> [v2]
Link: http://patchwork.freedesktop.org/patch/msgid/1460195877-20520-1-git-send-email-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/intel_ringbuffer.c