powerpc: Add new cache geometry aux vectors
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 3 Feb 2017 06:20:07 +0000 (17:20 +1100)
committerMichael Ellerman <mpe@ellerman.id.au>
Mon, 6 Feb 2017 08:46:04 +0000 (19:46 +1100)
commit98a5f361b8625c6f4841d6ba013bbf0e80d08147
tree4ed95efaf4243a91d9542e1431dca008df075d5e
parent608b42140e966a65cabc68d997875065f3e63c2f
powerpc: Add new cache geometry aux vectors

This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size of the cache in bytes
and the geometry (line size and number of ways).

We chose to not use the existing alpha/sh definition which
packs all the information in a single entry per cache level as
it is too restricted to represent some of the geometries used
on POWER.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/cache.h
arch/powerpc/include/asm/elf.h
arch/powerpc/include/uapi/asm/auxvec.h
arch/powerpc/kernel/setup_64.c