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(parent: ab3951e) | patch
drm/i915: Only apply the SNB pipe control w/a to gen6
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 20 Jul 2012 17:02:28 +0000 (18:02 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 8 Aug 2012 07:34:32 +0000 (09:34 +0200)
commit6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
tree188e1c0c4381913f1a2e16f2509704672e7689ddtree | snapshot (tar.gz zip)
parentab3951eb74e7c33a2f5b7b64d72e82f1eea61571commit | diff
drm/i915: Only apply the SNB pipe control w/a to gen6

The requirements for the sync flush to be emitted prior to the render
cache flush is only true for SandyBridge. On IvyBridge and friends we
can just emit the flushes with an inline CS stall.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | blame | history