git.stricted.de - GitHub/LineageOS/android_kernel_motorola

1 /*

2 * Copyright IBM Corp. 2004, 2011

3 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,

4 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,

5 * Thomas Spatzier <tspat@de.ibm.com>,

6 *

7 * This file contains interrupt related functions.

8 */

10 #include <linux/kernel_stat.h>

11 #include <linux/interrupt.h>

12 #include <linux/seq_file.h>

13 #include <linux/proc_fs.h>

14 #include <linux/profile.h>

15 #include <linux/module.h>

16 #include <linux/kernel.h>

17 #include <linux/ftrace.h>

18 #include <linux/errno.h>

19 #include <linux/slab.h>

20 #include <linux/cpu.h>

21 #include <asm/irq_regs.h>

22 #include <asm/cputime.h>

23 #include <asm/lowcore.h>

24 #include <asm/irq.h>

25 #include <asm/hw_irq.h>

26 #include "entry.h"

28 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);

29 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);

31 struct irq_class {

32 char *name;

33 char *desc;

34 };

36 /*

37 * The list of "main" irq classes on s390. This is the list of interrupts

38 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.

39 * Historically only external and I/O interrupts have been part of /proc/stat.

40 * We can't add the split external and I/O sub classes since the first field

41 * in the "intr" line in /proc/stat is supposed to be the sum of all other

42 * fields.

43 * Since the external and I/O interrupt fields are already sums we would end

44 * up with having a sum which accounts each interrupt twice.

45 */

46 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {

47 [EXT_INTERRUPT] = {.name = "EXT"},

48 [IO_INTERRUPT] = {.name = "I/O"},

49 [THIN_INTERRUPT] = {.name = "AIO"},

50 };

52 /*

53 * The list of split external and I/O interrupts that appear only in

54 * /proc/interrupts.

55 * In addition this list contains non external / I/O events like NMIs.

56 */

57 static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = {

58 [IRQEXT_CLK] = {.name = "CLK", .desc = "[EXT] Clock Comparator"},

59 [IRQEXT_EXC] = {.name = "EXC", .desc = "[EXT] External Call"},

60 [IRQEXT_EMS] = {.name = "EMS", .desc = "[EXT] Emergency Signal"},

61 [IRQEXT_TMR] = {.name = "TMR", .desc = "[EXT] CPU Timer"},

62 [IRQEXT_TLA] = {.name = "TAL", .desc = "[EXT] Timing Alert"},

63 [IRQEXT_PFL] = {.name = "PFL", .desc = "[EXT] Pseudo Page Fault"},

64 [IRQEXT_DSD] = {.name = "DSD", .desc = "[EXT] DASD Diag"},

65 [IRQEXT_VRT] = {.name = "VRT", .desc = "[EXT] Virtio"},

66 [IRQEXT_SCP] = {.name = "SCP", .desc = "[EXT] Service Call"},

67 [IRQEXT_IUC] = {.name = "IUC", .desc = "[EXT] IUCV"},

68 [IRQEXT_CMS] = {.name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},

69 [IRQEXT_CMC] = {.name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},

70 [IRQEXT_CMR] = {.name = "CMR", .desc = "[EXT] CPU-Measurement: RI"},

71 [IRQIO_CIO] = {.name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},

72 [IRQIO_QAI] = {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},

73 [IRQIO_DAS] = {.name = "DAS", .desc = "[I/O] DASD"},

74 [IRQIO_C15] = {.name = "C15", .desc = "[I/O] 3215"},

75 [IRQIO_C70] = {.name = "C70", .desc = "[I/O] 3270"},

76 [IRQIO_TAP] = {.name = "TAP", .desc = "[I/O] Tape"},

77 [IRQIO_VMR] = {.name = "VMR", .desc = "[I/O] Unit Record Devices"},

78 [IRQIO_LCS] = {.name = "LCS", .desc = "[I/O] LCS"},

79 [IRQIO_CLW] = {.name = "CLW", .desc = "[I/O] CLAW"},

80 [IRQIO_CTC] = {.name = "CTC", .desc = "[I/O] CTC"},

81 [IRQIO_APB] = {.name = "APB", .desc = "[I/O] AP Bus"},

82 [IRQIO_ADM] = {.name = "ADM", .desc = "[I/O] EADM Subchannel"},

83 [IRQIO_CSC] = {.name = "CSC", .desc = "[I/O] CHSC Subchannel"},

84 [IRQIO_PCI] = {.name = "PCI", .desc = "[I/O] PCI Interrupt" },

85 [IRQIO_MSI] = {.name = "MSI", .desc = "[I/O] MSI Interrupt" },

86 [IRQIO_VIR] = {.name = "VIR", .desc = "[I/O] Virtual I/O Devices"},

87 [NMI_NMI] = {.name = "NMI", .desc = "[NMI] Machine Check"},

88 [CPU_RST] = {.name = "RST", .desc = "[CPU] CPU Restart"},

89 };

91 void __init init_IRQ(void)

92 {

93 irq_reserve_irqs(0, THIN_INTERRUPT);

94 init_cio_interrupts();

95 init_airq_interrupts();

96 init_ext_interrupts();

97 }

99 void do_IRQ(struct pt_regs *regs, int irq)

100 {

101 struct pt_regs *old_regs;

102

103 old_regs = set_irq_regs(regs);

104 irq_enter();

105 if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)

106 /* Serve timer interrupts first. */

107 clock_comparator_work();

108 generic_handle_irq(irq);

109 irq_exit();

110 set_irq_regs(old_regs);

111 }

112

113 /*

114 * show_interrupts is needed by /proc/interrupts.

115 */

116 int show_interrupts(struct seq_file *p, void *v)

117 {

118 int irq = *(loff_t *) v;

119 int cpu;

120

121 get_online_cpus();

122 if (irq == 0) {

123 seq_puts(p, " ");

124 for_each_online_cpu(cpu)

125 seq_printf(p, "CPU%d ", cpu);

126 seq_putc(p, '\n');

127 goto out;

128 }

129 if (irq < NR_IRQS) {

130 if (irq >= NR_IRQS_BASE)

131 goto out;

132 seq_printf(p, "%s: ", irqclass_main_desc[irq].name);

133 for_each_online_cpu(cpu)

134 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));

135 seq_putc(p, '\n');

136 goto out;

137 }

138 for (irq = 0; irq < NR_ARCH_IRQS; irq++) {

139 seq_printf(p, "%s: ", irqclass_sub_desc[irq].name);

140 for_each_online_cpu(cpu)

141 seq_printf(p, "%10u ",

142 per_cpu(irq_stat, cpu).irqs[irq]);

143 if (irqclass_sub_desc[irq].desc)

144 seq_printf(p, " %s", irqclass_sub_desc[irq].desc);

145 seq_putc(p, '\n');

146 }

147 out:

148 put_online_cpus();

149 return 0;

150 }

151

152 int arch_show_interrupts(struct seq_file *p, int prec)

153 {

154 return 0;

155 }

156

157 /*

158 * Switch to the asynchronous interrupt stack for softirq execution.

159 */

160 asmlinkage void do_softirq(void)

161 {

162 unsigned long flags, old, new;

163

164 if (in_interrupt())

165 return;

166

167 local_irq_save(flags);

168

169 if (local_softirq_pending()) {

170 /* Get current stack pointer. */

171 asm volatile("la %0,0(15)" : "=a" (old));

172 /* Check against async. stack address range. */

173 new = S390_lowcore.async_stack;

174 if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {

175 /* Need to switch to the async. stack. */

176 new -= STACK_FRAME_OVERHEAD;

177 ((struct stack_frame *) new)->back_chain = old;

178

179 asm volatile(" la 15,0(%0)\n"

180 " basr 14,%2\n"

181 " la 15,0(%1)\n"

182 : : "a" (new), "a" (old),

183 "a" (__do_softirq)

184 : "0", "1", "2", "3", "4", "5", "14",

185 "cc", "memory" );

186 } else {

187 /* We are already on the async stack. */

188 __do_softirq();

189 }

190 }

191

192 local_irq_restore(flags);

193 }

194

195 /*

196 * ext_int_hash[index] is the list head for all external interrupts that hash

197 * to this index.

198 */

199 static struct hlist_head ext_int_hash[256];

200

201 struct ext_int_info {

202 ext_int_handler_t handler;

203 struct hlist_node entry;

204 struct rcu_head rcu;

205 u16 code;

206 };

207

208 /* ext_int_hash_lock protects the handler lists for external interrupts */

209 DEFINE_SPINLOCK(ext_int_hash_lock);

210

211 static inline int ext_hash(u16 code)

212 {

213 return (code + (code >> 9)) & 0xff;

214 }

215

216 int register_external_interrupt(u16 code, ext_int_handler_t handler)

217 {

218 struct ext_int_info *p;

219 unsigned long flags;

220 int index;

221

222 p = kmalloc(sizeof(*p), GFP_ATOMIC);

223 if (!p)

224 return -ENOMEM;

225 p->code = code;

226 p->handler = handler;

227 index = ext_hash(code);

228

229 spin_lock_irqsave(&ext_int_hash_lock, flags);

230 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);

231 spin_unlock_irqrestore(&ext_int_hash_lock, flags);

232 return 0;

233 }

234 EXPORT_SYMBOL(register_external_interrupt);

235

236 int unregister_external_interrupt(u16 code, ext_int_handler_t handler)

237 {

238 struct ext_int_info *p;

239 unsigned long flags;

240 int index = ext_hash(code);

241

242 spin_lock_irqsave(&ext_int_hash_lock, flags);

243 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {

244 if (p->code == code && p->handler == handler) {

245 hlist_del_rcu(&p->entry);

246 kfree_rcu(p, rcu);

247 }

248 }

249 spin_unlock_irqrestore(&ext_int_hash_lock, flags);

250 return 0;

251 }

252 EXPORT_SYMBOL(unregister_external_interrupt);

253

254 static irqreturn_t do_ext_interrupt(int irq, void *dummy)

255 {

256 struct pt_regs *regs = get_irq_regs();

257 struct ext_code ext_code;

258 struct ext_int_info *p;

259 int index;

260

261 ext_code = *(struct ext_code *) &regs->int_code;

262 if (ext_code.code != 0x1004)

263 __get_cpu_var(s390_idle).nohz_delay = 1;

264

265 index = ext_hash(ext_code.code);

266 rcu_read_lock();

267 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {

268 if (unlikely(p->code != ext_code.code))

269 continue;

270 p->handler(ext_code, regs->int_parm, regs->int_parm_long);

271 }

272 rcu_read_unlock();

273 return IRQ_HANDLED;

274 }

275

276 static struct irqaction external_interrupt = {

277 .name = "EXT",

278 .handler = do_ext_interrupt,

279 };

280

281 void __init init_ext_interrupts(void)

282 {

283 int idx;

284

285 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)

286 INIT_HLIST_HEAD(&ext_int_hash[idx]);

287

288 irq_set_chip_and_handler(EXT_INTERRUPT,

289 &dummy_irq_chip, handle_percpu_irq);

290 setup_irq(EXT_INTERRUPT, &external_interrupt);

291 }

292

293 static DEFINE_SPINLOCK(irq_subclass_lock);

294 static unsigned char irq_subclass_refcount[64];

295

296 void irq_subclass_register(enum irq_subclass subclass)

297 {

298 spin_lock(&irq_subclass_lock);

299 if (!irq_subclass_refcount[subclass])

300 ctl_set_bit(0, subclass);

301 irq_subclass_refcount[subclass]++;

302 spin_unlock(&irq_subclass_lock);

303 }

304 EXPORT_SYMBOL(irq_subclass_register);

305

306 void irq_subclass_unregister(enum irq_subclass subclass)

307 {

308 spin_lock(&irq_subclass_lock);

309 irq_subclass_refcount[subclass]--;

310 if (!irq_subclass_refcount[subclass])

311 ctl_clear_bit(0, subclass);

312 spin_unlock(&irq_subclass_lock);

313 }

314 EXPORT_SYMBOL(irq_subclass_unregister);