62d22ae
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] /
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_edid.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39
40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
50 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
51
52
53 static const char *tv_format_names[] = {
54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61 };
62
63 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
65 struct intel_sdvo {
66 struct intel_encoder base;
67
68 u8 slave_addr;
69
70 /* Register for the SDVO device: SDVOB or SDVOC */
71 int sdvo_reg;
72
73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
75
76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
80 struct intel_sdvo_caps caps;
81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
83 int pixel_clock_min, pixel_clock_max;
84
85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
100 /* This is for current tv format name */
101 int tv_format_index;
102
103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
107
108 /**
109 * This is set if we detect output of sdvo device as LVDS.
110 */
111 bool is_lvds;
112
113 /**
114 * This is sdvo flags for input timing.
115 */
116 uint8_t sdvo_flags;
117
118 /**
119 * This is sdvo fixed pannel mode pointer
120 */
121 struct drm_display_mode *sdvo_lvds_fixed_mode;
122
123 /*
124 * supported encoding mode, used to determine whether HDMI is
125 * supported
126 */
127 struct intel_sdvo_encode encode;
128
129 /* DDC bus used by this SDVO encoder */
130 uint8_t ddc_bus;
131
132 /* Mac mini hack -- use the same DDC as the analog connector */
133 struct i2c_adapter *analog_ddc_bus;
134
135 };
136
137 struct intel_sdvo_connector {
138 struct intel_connector base;
139
140 /* Mark the type of connector */
141 uint16_t output_flag;
142
143 /* This contains all current supported TV format */
144 u8 tv_format_supported[TV_FORMAT_NUM];
145 int format_supported_num;
146 struct drm_property *tv_format;
147
148 /* add the property for the SDVO-TV */
149 struct drm_property *left;
150 struct drm_property *right;
151 struct drm_property *top;
152 struct drm_property *bottom;
153 struct drm_property *hpos;
154 struct drm_property *vpos;
155 struct drm_property *contrast;
156 struct drm_property *saturation;
157 struct drm_property *hue;
158 struct drm_property *sharpness;
159 struct drm_property *flicker_filter;
160 struct drm_property *flicker_filter_adaptive;
161 struct drm_property *flicker_filter_2d;
162 struct drm_property *tv_chroma_filter;
163 struct drm_property *tv_luma_filter;
164 struct drm_property *dot_crawl;
165
166 /* add the property for the SDVO-TV/LVDS */
167 struct drm_property *brightness;
168
169 /* Add variable to record current setting for the above property */
170 u32 left_margin, right_margin, top_margin, bottom_margin;
171
172 /* this is to get the range of margin.*/
173 u32 max_hscan, max_vscan;
174 u32 max_hpos, cur_hpos;
175 u32 max_vpos, cur_vpos;
176 u32 cur_brightness, max_brightness;
177 u32 cur_contrast, max_contrast;
178 u32 cur_saturation, max_saturation;
179 u32 cur_hue, max_hue;
180 u32 cur_sharpness, max_sharpness;
181 u32 cur_flicker_filter, max_flicker_filter;
182 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
183 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
184 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
185 u32 cur_tv_luma_filter, max_tv_luma_filter;
186 u32 cur_dot_crawl, max_dot_crawl;
187 };
188
189 static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
190 {
191 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
192 }
193
194 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
195 {
196 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
197 }
198
199 static bool
200 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
201 static bool
202 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
203 struct intel_sdvo_connector *intel_sdvo_connector,
204 int type);
205 static bool
206 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector);
208
209 /**
210 * Writes the SDVOB or SDVOC with the given value, but always writes both
211 * SDVOB and SDVOC to work around apparent hardware issues (according to
212 * comments in the BIOS).
213 */
214 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
215 {
216 struct drm_device *dev = intel_sdvo->base.enc.dev;
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 u32 bval = val, cval = val;
219 int i;
220
221 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
222 I915_WRITE(intel_sdvo->sdvo_reg, val);
223 I915_READ(intel_sdvo->sdvo_reg);
224 return;
225 }
226
227 if (intel_sdvo->sdvo_reg == SDVOB) {
228 cval = I915_READ(SDVOC);
229 } else {
230 bval = I915_READ(SDVOB);
231 }
232 /*
233 * Write the registers twice for luck. Sometimes,
234 * writing them only once doesn't appear to 'stick'.
235 * The BIOS does this too. Yay, magic
236 */
237 for (i = 0; i < 2; i++)
238 {
239 I915_WRITE(SDVOB, bval);
240 I915_READ(SDVOB);
241 I915_WRITE(SDVOC, cval);
242 I915_READ(SDVOC);
243 }
244 }
245
246 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
247 {
248 u8 out_buf[2] = { addr, 0 };
249 u8 buf[2];
250 struct i2c_msg msgs[] = {
251 {
252 .addr = intel_sdvo->slave_addr >> 1,
253 .flags = 0,
254 .len = 1,
255 .buf = out_buf,
256 },
257 {
258 .addr = intel_sdvo->slave_addr >> 1,
259 .flags = I2C_M_RD,
260 .len = 1,
261 .buf = buf,
262 }
263 };
264 int ret;
265
266 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
267 {
268 *ch = buf[0];
269 return true;
270 }
271
272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
273 return false;
274 }
275
276 static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
277 {
278 u8 out_buf[2] = { addr, ch };
279 struct i2c_msg msgs[] = {
280 {
281 .addr = intel_sdvo->slave_addr >> 1,
282 .flags = 0,
283 .len = 2,
284 .buf = out_buf,
285 }
286 };
287
288 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
289 }
290
291 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
292 /** Mapping of command numbers to names, for debug output */
293 static const struct _sdvo_cmd_name {
294 u8 cmd;
295 const char *name;
296 } sdvo_cmd_names[] = {
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
340
341 /* Add the op code for SDVO enhancements */
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
386
387 /* HDMI op code */
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
408 };
409
410 #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
411 #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
412
413 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
414 const void *args, int args_len)
415 {
416 int i;
417
418 DRM_DEBUG_KMS("%s: W: %02X ",
419 SDVO_NAME(intel_sdvo), cmd);
420 for (i = 0; i < args_len; i++)
421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
422 for (; i < 8; i++)
423 DRM_LOG_KMS(" ");
424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
425 if (cmd == sdvo_cmd_names[i].cmd) {
426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
427 break;
428 }
429 }
430 if (i == ARRAY_SIZE(sdvo_cmd_names))
431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
433 }
434
435 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
436 const void *args, int args_len)
437 {
438 int i;
439
440 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
441
442 for (i = 0; i < args_len; i++) {
443 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
444 ((u8*)args)[i]))
445 return false;
446 }
447
448 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
449 }
450
451 static const char *cmd_status_names[] = {
452 "Power on",
453 "Success",
454 "Not supported",
455 "Invalid arg",
456 "Pending",
457 "Target not specified",
458 "Scaling not supported"
459 };
460
461 static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
462 void *response, int response_len,
463 u8 status)
464 {
465 int i;
466
467 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
468 for (i = 0; i < response_len; i++)
469 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
470 for (; i < 8; i++)
471 DRM_LOG_KMS(" ");
472 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
473 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
474 else
475 DRM_LOG_KMS("(??? %d)", status);
476 DRM_LOG_KMS("\n");
477 }
478
479 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
480 void *response, int response_len)
481 {
482 int i;
483 u8 status;
484 u8 retry = 50;
485
486 while (retry--) {
487 /* Read the command response */
488 for (i = 0; i < response_len; i++) {
489 if (!intel_sdvo_read_byte(intel_sdvo,
490 SDVO_I2C_RETURN_0 + i,
491 &((u8 *)response)[i]))
492 return false;
493 }
494
495 /* read the return status */
496 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
497 &status))
498 return false;
499
500 intel_sdvo_debug_response(intel_sdvo, response, response_len,
501 status);
502 if (status != SDVO_CMD_STATUS_PENDING)
503 break;
504
505 mdelay(50);
506 }
507
508 return status == SDVO_CMD_STATUS_SUCCESS;
509 }
510
511 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
512 {
513 if (mode->clock >= 100000)
514 return 1;
515 else if (mode->clock >= 50000)
516 return 2;
517 else
518 return 4;
519 }
520
521 /**
522 * Try to read the response after issuie the DDC switch command. But it
523 * is noted that we must do the action of reading response and issuing DDC
524 * switch command in one I2C transaction. Otherwise when we try to start
525 * another I2C transaction after issuing the DDC bus switch, it will be
526 * switched to the internal SDVO register.
527 */
528 static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
529 u8 target)
530 {
531 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
532 struct i2c_msg msgs[] = {
533 {
534 .addr = intel_sdvo->slave_addr >> 1,
535 .flags = 0,
536 .len = 2,
537 .buf = out_buf,
538 },
539 /* the following two are to read the response */
540 {
541 .addr = intel_sdvo->slave_addr >> 1,
542 .flags = 0,
543 .len = 1,
544 .buf = cmd_buf,
545 },
546 {
547 .addr = intel_sdvo->slave_addr >> 1,
548 .flags = I2C_M_RD,
549 .len = 1,
550 .buf = ret_value,
551 },
552 };
553
554 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
555 &target, 1);
556 /* write the DDC switch command argument */
557 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
558
559 out_buf[0] = SDVO_I2C_OPCODE;
560 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
561 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
562 cmd_buf[1] = 0;
563 ret_value[0] = 0;
564 ret_value[1] = 0;
565
566 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
567 if (ret != 3) {
568 /* failure in I2C transfer */
569 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
570 return;
571 }
572 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
573 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
574 ret_value[0]);
575 return;
576 }
577 return;
578 }
579
580 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
581 {
582 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
583 return false;
584
585 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
586 }
587
588 static bool
589 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
590 {
591 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
592 return false;
593
594 return intel_sdvo_read_response(intel_sdvo, value, len);
595 }
596
597 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
598 {
599 struct intel_sdvo_set_target_input_args targets = {0};
600 return intel_sdvo_set_value(intel_sdvo,
601 SDVO_CMD_SET_TARGET_INPUT,
602 &targets, sizeof(targets));
603 }
604
605 /**
606 * Return whether each input is trained.
607 *
608 * This function is making an assumption about the layout of the response,
609 * which should be checked against the docs.
610 */
611 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
612 {
613 struct intel_sdvo_get_trained_inputs_response response;
614
615 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
616 &response, sizeof(response)))
617 return false;
618
619 *input_1 = response.input0_trained;
620 *input_2 = response.input1_trained;
621 return true;
622 }
623
624 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
625 u16 outputs)
626 {
627 return intel_sdvo_set_value(intel_sdvo,
628 SDVO_CMD_SET_ACTIVE_OUTPUTS,
629 &outputs, sizeof(outputs));
630 }
631
632 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
633 int mode)
634 {
635 u8 state = SDVO_ENCODER_STATE_ON;
636
637 switch (mode) {
638 case DRM_MODE_DPMS_ON:
639 state = SDVO_ENCODER_STATE_ON;
640 break;
641 case DRM_MODE_DPMS_STANDBY:
642 state = SDVO_ENCODER_STATE_STANDBY;
643 break;
644 case DRM_MODE_DPMS_SUSPEND:
645 state = SDVO_ENCODER_STATE_SUSPEND;
646 break;
647 case DRM_MODE_DPMS_OFF:
648 state = SDVO_ENCODER_STATE_OFF;
649 break;
650 }
651
652 return intel_sdvo_set_value(intel_sdvo,
653 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
654 }
655
656 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
657 int *clock_min,
658 int *clock_max)
659 {
660 struct intel_sdvo_pixel_clock_range clocks;
661
662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
665 return false;
666
667 /* Convert the values from units of 10 kHz to kHz. */
668 *clock_min = clocks.min * 10;
669 *clock_max = clocks.max * 10;
670 return true;
671 }
672
673 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
674 u16 outputs)
675 {
676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_TARGET_OUTPUT,
678 &outputs, sizeof(outputs));
679 }
680
681 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
682 struct intel_sdvo_dtd *dtd)
683 {
684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
686 }
687
688 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
689 struct intel_sdvo_dtd *dtd)
690 {
691 return intel_sdvo_set_timing(intel_sdvo,
692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
693 }
694
695 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
696 struct intel_sdvo_dtd *dtd)
697 {
698 return intel_sdvo_set_timing(intel_sdvo,
699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
700 }
701
702 static bool
703 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
704 uint16_t clock,
705 uint16_t width,
706 uint16_t height)
707 {
708 struct intel_sdvo_preferred_input_timing_args args;
709
710 memset(&args, 0, sizeof(args));
711 args.clock = clock;
712 args.width = width;
713 args.height = height;
714 args.interlace = 0;
715
716 if (intel_sdvo->is_lvds &&
717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
719 args.scaled = 1;
720
721 return intel_sdvo_set_value(intel_sdvo,
722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
723 &args, sizeof(args));
724 }
725
726 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
727 struct intel_sdvo_dtd *dtd)
728 {
729 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
730 &dtd->part1, sizeof(dtd->part1)) &&
731 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
732 &dtd->part2, sizeof(dtd->part2));
733 }
734
735 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
736 {
737 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
738 }
739
740 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
741 const struct drm_display_mode *mode)
742 {
743 uint16_t width, height;
744 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
745 uint16_t h_sync_offset, v_sync_offset;
746
747 width = mode->crtc_hdisplay;
748 height = mode->crtc_vdisplay;
749
750 /* do some mode translations */
751 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
752 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
753
754 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
755 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
756
757 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
758 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
759
760 dtd->part1.clock = mode->clock / 10;
761 dtd->part1.h_active = width & 0xff;
762 dtd->part1.h_blank = h_blank_len & 0xff;
763 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
764 ((h_blank_len >> 8) & 0xf);
765 dtd->part1.v_active = height & 0xff;
766 dtd->part1.v_blank = v_blank_len & 0xff;
767 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
768 ((v_blank_len >> 8) & 0xf);
769
770 dtd->part2.h_sync_off = h_sync_offset & 0xff;
771 dtd->part2.h_sync_width = h_sync_len & 0xff;
772 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
773 (v_sync_len & 0xf);
774 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
775 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
776 ((v_sync_len & 0x30) >> 4);
777
778 dtd->part2.dtd_flags = 0x18;
779 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
780 dtd->part2.dtd_flags |= 0x2;
781 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
782 dtd->part2.dtd_flags |= 0x4;
783
784 dtd->part2.sdvo_flags = 0;
785 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
786 dtd->part2.reserved = 0;
787 }
788
789 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
790 const struct intel_sdvo_dtd *dtd)
791 {
792 mode->hdisplay = dtd->part1.h_active;
793 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
794 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
795 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
796 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
797 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
798 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
799 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
800
801 mode->vdisplay = dtd->part1.v_active;
802 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
803 mode->vsync_start = mode->vdisplay;
804 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
805 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
806 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
807 mode->vsync_end = mode->vsync_start +
808 (dtd->part2.v_sync_off_width & 0xf);
809 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
810 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
811 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
812
813 mode->clock = dtd->part1.clock * 10;
814
815 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
816 if (dtd->part2.dtd_flags & 0x2)
817 mode->flags |= DRM_MODE_FLAG_PHSYNC;
818 if (dtd->part2.dtd_flags & 0x4)
819 mode->flags |= DRM_MODE_FLAG_PVSYNC;
820 }
821
822 static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
823 struct intel_sdvo_encode *encode)
824 {
825 if (intel_sdvo_get_value(intel_sdvo,
826 SDVO_CMD_GET_SUPP_ENCODE,
827 encode, sizeof(*encode)))
828 return true;
829
830 /* non-support means DVI */
831 memset(encode, 0, sizeof(*encode));
832 return false;
833 }
834
835 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
836 uint8_t mode)
837 {
838 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
839 }
840
841 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
842 uint8_t mode)
843 {
844 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
845 }
846
847 #if 0
848 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
849 {
850 int i, j;
851 uint8_t set_buf_index[2];
852 uint8_t av_split;
853 uint8_t buf_size;
854 uint8_t buf[48];
855 uint8_t *pos;
856
857 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
858
859 for (i = 0; i <= av_split; i++) {
860 set_buf_index[0] = i; set_buf_index[1] = 0;
861 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
862 set_buf_index, 2);
863 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
864 intel_sdvo_read_response(encoder, &buf_size, 1);
865
866 pos = buf;
867 for (j = 0; j <= buf_size; j += 8) {
868 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
869 NULL, 0);
870 intel_sdvo_read_response(encoder, pos, 8);
871 pos += 8;
872 }
873 }
874 }
875 #endif
876
877 static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
878 int index,
879 uint8_t *data, int8_t size, uint8_t tx_rate)
880 {
881 uint8_t set_buf_index[2];
882
883 set_buf_index[0] = index;
884 set_buf_index[1] = 0;
885
886 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
887 set_buf_index, 2))
888 return false;
889
890 for (; size > 0; size -= 8) {
891 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
892 return false;
893
894 data += 8;
895 }
896
897 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
898 }
899
900 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
901 {
902 uint8_t csum = 0;
903 int i;
904
905 for (i = 0; i < size; i++)
906 csum += data[i];
907
908 return 0x100 - csum;
909 }
910
911 #define DIP_TYPE_AVI 0x82
912 #define DIP_VERSION_AVI 0x2
913 #define DIP_LEN_AVI 13
914
915 struct dip_infoframe {
916 uint8_t type;
917 uint8_t version;
918 uint8_t len;
919 uint8_t checksum;
920 union {
921 struct {
922 /* Packet Byte #1 */
923 uint8_t S:2;
924 uint8_t B:2;
925 uint8_t A:1;
926 uint8_t Y:2;
927 uint8_t rsvd1:1;
928 /* Packet Byte #2 */
929 uint8_t R:4;
930 uint8_t M:2;
931 uint8_t C:2;
932 /* Packet Byte #3 */
933 uint8_t SC:2;
934 uint8_t Q:2;
935 uint8_t EC:3;
936 uint8_t ITC:1;
937 /* Packet Byte #4 */
938 uint8_t VIC:7;
939 uint8_t rsvd2:1;
940 /* Packet Byte #5 */
941 uint8_t PR:4;
942 uint8_t rsvd3:4;
943 /* Packet Byte #6~13 */
944 uint16_t top_bar_end;
945 uint16_t bottom_bar_start;
946 uint16_t left_bar_end;
947 uint16_t right_bar_start;
948 } avi;
949 struct {
950 /* Packet Byte #1 */
951 uint8_t channel_count:3;
952 uint8_t rsvd1:1;
953 uint8_t coding_type:4;
954 /* Packet Byte #2 */
955 uint8_t sample_size:2; /* SS0, SS1 */
956 uint8_t sample_frequency:3;
957 uint8_t rsvd2:3;
958 /* Packet Byte #3 */
959 uint8_t coding_type_private:5;
960 uint8_t rsvd3:3;
961 /* Packet Byte #4 */
962 uint8_t channel_allocation;
963 /* Packet Byte #5 */
964 uint8_t rsvd4:3;
965 uint8_t level_shift:4;
966 uint8_t downmix_inhibit:1;
967 } audio;
968 uint8_t payload[28];
969 } __attribute__ ((packed)) u;
970 } __attribute__((packed));
971
972 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
973 struct drm_display_mode * mode)
974 {
975 struct dip_infoframe avi_if = {
976 .type = DIP_TYPE_AVI,
977 .version = DIP_VERSION_AVI,
978 .len = DIP_LEN_AVI,
979 };
980
981 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
982 4 + avi_if.len);
983 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
984 4 + avi_if.len,
985 SDVO_HBUF_TX_VSYNC);
986 }
987
988 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
989 {
990 struct intel_sdvo_tv_format format;
991 uint32_t format_map;
992
993 format_map = 1 << intel_sdvo->tv_format_index;
994 memset(&format, 0, sizeof(format));
995 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
996
997 BUILD_BUG_ON(sizeof(format) != 6);
998 return intel_sdvo_set_value(intel_sdvo,
999 SDVO_CMD_SET_TV_FORMAT,
1000 &format, sizeof(format));
1001 }
1002
1003 static bool
1004 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1005 struct drm_display_mode *mode)
1006 {
1007 struct intel_sdvo_dtd output_dtd;
1008
1009 if (!intel_sdvo_set_target_output(intel_sdvo,
1010 intel_sdvo->attached_output))
1011 return false;
1012
1013 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1014 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1015 return false;
1016
1017 return true;
1018 }
1019
1020 static bool
1021 intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1022 struct drm_display_mode *mode,
1023 struct drm_display_mode *adjusted_mode)
1024 {
1025 struct intel_sdvo_dtd input_dtd;
1026
1027 /* Reset the input timing to the screen. Assume always input 0. */
1028 if (!intel_sdvo_set_target_input(intel_sdvo))
1029 return false;
1030
1031 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1032 mode->clock / 10,
1033 mode->hdisplay,
1034 mode->vdisplay))
1035 return false;
1036
1037 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1038 &input_dtd))
1039 return false;
1040
1041 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1042 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
1043
1044 drm_mode_set_crtcinfo(adjusted_mode, 0);
1045 mode->clock = adjusted_mode->clock;
1046 return true;
1047 }
1048
1049 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1050 struct drm_display_mode *mode,
1051 struct drm_display_mode *adjusted_mode)
1052 {
1053 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1054
1055 /* We need to construct preferred input timings based on our
1056 * output timings. To do that, we have to set the output
1057 * timings, even though this isn't really the right place in
1058 * the sequence to do it. Oh well.
1059 */
1060 if (intel_sdvo->is_tv) {
1061 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1062 return false;
1063
1064 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1065 mode,
1066 adjusted_mode);
1067 } else if (intel_sdvo->is_lvds) {
1068 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
1069
1070 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1071 intel_sdvo->sdvo_lvds_fixed_mode))
1072 return false;
1073
1074 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1075 mode,
1076 adjusted_mode);
1077 }
1078
1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1080 * SDVO device will be told of the multiplier during mode_set.
1081 */
1082 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1083
1084 return true;
1085 }
1086
1087 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1088 struct drm_display_mode *mode,
1089 struct drm_display_mode *adjusted_mode)
1090 {
1091 struct drm_device *dev = encoder->dev;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc = encoder->crtc;
1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1095 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1096 u32 sdvox = 0;
1097 int sdvo_pixel_multiply, rate;
1098 struct intel_sdvo_in_out_map in_out;
1099 struct intel_sdvo_dtd input_dtd;
1100
1101 if (!mode)
1102 return;
1103
1104 /* First, set the input mapping for the first input to our controlled
1105 * output. This is only correct if we're a single-input device, in
1106 * which case the first input is the output from the appropriate SDVO
1107 * channel on the motherboard. In a two-input device, the first input
1108 * will be SDVOB and the second SDVOC.
1109 */
1110 in_out.in0 = intel_sdvo->attached_output;
1111 in_out.in1 = 0;
1112
1113 intel_sdvo_set_value(intel_sdvo,
1114 SDVO_CMD_SET_IN_OUT_MAP,
1115 &in_out, sizeof(in_out));
1116
1117 if (intel_sdvo->is_hdmi) {
1118 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1119 return;
1120
1121 sdvox |= SDVO_AUDIO_ENABLE;
1122 }
1123
1124 /* We have tried to get input timing in mode_fixup, and filled into
1125 adjusted_mode */
1126 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1127 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1128 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
1129
1130 /* If it's a TV, we already set the output timing in mode_fixup.
1131 * Otherwise, the output timing is equal to the input timing.
1132 */
1133 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
1134 /* Set the output timing to the screen */
1135 if (!intel_sdvo_set_target_output(intel_sdvo,
1136 intel_sdvo->attached_output))
1137 return;
1138
1139 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
1140 }
1141
1142 /* Set the input timing to the screen. Assume always input 0. */
1143 if (!intel_sdvo_set_target_input(intel_sdvo))
1144 return;
1145
1146 if (intel_sdvo->is_tv) {
1147 if (!intel_sdvo_set_tv_format(intel_sdvo))
1148 return;
1149 }
1150
1151 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1152 * provide the device with a timing it can support, if it supports that
1153 * feature. However, presumably we would need to adjust the CRTC to
1154 * output the preferred timing, and we don't support that currently.
1155 */
1156 #if 0
1157 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
1158 width, height);
1159 if (success) {
1160 struct intel_sdvo_dtd *input_dtd;
1161
1162 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1163 intel_sdvo_set_input_timing(encoder, &input_dtd);
1164 }
1165 #else
1166 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
1167 #endif
1168
1169 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1170 switch (sdvo_pixel_multiply) {
1171 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1172 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1173 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1174 }
1175 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1176 return;
1177
1178 /* Set the SDVO control regs. */
1179 if (IS_I965G(dev)) {
1180 sdvox |= SDVO_BORDER_ENABLE;
1181 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1182 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1183 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1184 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
1185 } else {
1186 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1187 switch (intel_sdvo->sdvo_reg) {
1188 case SDVOB:
1189 sdvox &= SDVOB_PRESERVE_MASK;
1190 break;
1191 case SDVOC:
1192 sdvox &= SDVOC_PRESERVE_MASK;
1193 break;
1194 }
1195 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1196 }
1197 if (intel_crtc->pipe == 1)
1198 sdvox |= SDVO_PIPE_B_SELECT;
1199
1200 if (IS_I965G(dev)) {
1201 /* done in crtc_mode_set as the dpll_md reg must be written early */
1202 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1203 /* done in crtc_mode_set as it lives inside the dpll register */
1204 } else {
1205 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1206 }
1207
1208 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
1209 sdvox |= SDVO_STALL_SELECT;
1210 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1211 }
1212
1213 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1214 {
1215 struct drm_device *dev = encoder->dev;
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1218 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
1219 u32 temp;
1220
1221 if (mode != DRM_MODE_DPMS_ON) {
1222 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1223 if (0)
1224 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1225
1226 if (mode == DRM_MODE_DPMS_OFF) {
1227 temp = I915_READ(intel_sdvo->sdvo_reg);
1228 if ((temp & SDVO_ENABLE) != 0) {
1229 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1230 }
1231 }
1232 } else {
1233 bool input1, input2;
1234 int i;
1235 u8 status;
1236
1237 temp = I915_READ(intel_sdvo->sdvo_reg);
1238 if ((temp & SDVO_ENABLE) == 0)
1239 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1240 for (i = 0; i < 2; i++)
1241 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242
1243 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1244 /* Warn if the device reported failure to sync.
1245 * A lot of SDVO devices fail to notify of sync, but it's
1246 * a given it the status is a success, we succeeded.
1247 */
1248 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1249 DRM_DEBUG_KMS("First %s output reported failure to "
1250 "sync\n", SDVO_NAME(intel_sdvo));
1251 }
1252
1253 if (0)
1254 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1255 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1256 }
1257 return;
1258 }
1259
1260 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1261 struct drm_display_mode *mode)
1262 {
1263 struct drm_encoder *encoder = intel_attached_encoder(connector);
1264 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1265
1266 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1267 return MODE_NO_DBLESCAN;
1268
1269 if (intel_sdvo->pixel_clock_min > mode->clock)
1270 return MODE_CLOCK_LOW;
1271
1272 if (intel_sdvo->pixel_clock_max < mode->clock)
1273 return MODE_CLOCK_HIGH;
1274
1275 if (intel_sdvo->is_lvds) {
1276 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1277 return MODE_PANEL;
1278
1279 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1280 return MODE_PANEL;
1281 }
1282
1283 return MODE_OK;
1284 }
1285
1286 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1287 {
1288 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
1289 }
1290
1291 /* No use! */
1292 #if 0
1293 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1294 {
1295 struct drm_connector *connector = NULL;
1296 struct intel_sdvo *iout = NULL;
1297 struct intel_sdvo *sdvo;
1298
1299 /* find the sdvo connector */
1300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1301 iout = to_intel_sdvo(connector);
1302
1303 if (iout->type != INTEL_OUTPUT_SDVO)
1304 continue;
1305
1306 sdvo = iout->dev_priv;
1307
1308 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1309 return connector;
1310
1311 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1312 return connector;
1313
1314 }
1315
1316 return NULL;
1317 }
1318
1319 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1320 {
1321 u8 response[2];
1322 u8 status;
1323 struct intel_sdvo *intel_sdvo;
1324 DRM_DEBUG_KMS("\n");
1325
1326 if (!connector)
1327 return 0;
1328
1329 intel_sdvo = to_intel_sdvo(connector);
1330
1331 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1332 &response, 2) && response[0];
1333 }
1334
1335 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1336 {
1337 u8 response[2];
1338 u8 status;
1339 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
1340
1341 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1342 intel_sdvo_read_response(intel_sdvo, &response, 2);
1343
1344 if (on) {
1345 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1346 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
1347
1348 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1349 } else {
1350 response[0] = 0;
1351 response[1] = 0;
1352 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1353 }
1354
1355 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1356 intel_sdvo_read_response(intel_sdvo, &response, 2);
1357 }
1358 #endif
1359
1360 static bool
1361 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1362 {
1363 int caps = 0;
1364
1365 if (intel_sdvo->caps.output_flags &
1366 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1367 caps++;
1368 if (intel_sdvo->caps.output_flags &
1369 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1370 caps++;
1371 if (intel_sdvo->caps.output_flags &
1372 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1373 caps++;
1374 if (intel_sdvo->caps.output_flags &
1375 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1376 caps++;
1377 if (intel_sdvo->caps.output_flags &
1378 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1379 caps++;
1380
1381 if (intel_sdvo->caps.output_flags &
1382 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1383 caps++;
1384
1385 if (intel_sdvo->caps.output_flags &
1386 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1387 caps++;
1388
1389 return (caps > 1);
1390 }
1391
1392 static struct drm_connector *
1393 intel_find_analog_connector(struct drm_device *dev)
1394 {
1395 struct drm_connector *connector;
1396 struct drm_encoder *encoder;
1397 struct intel_sdvo *intel_sdvo;
1398
1399 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1400 intel_sdvo = enc_to_intel_sdvo(encoder);
1401 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
1402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1403 if (encoder == intel_attached_encoder(connector))
1404 return connector;
1405 }
1406 }
1407 }
1408 return NULL;
1409 }
1410
1411 static int
1412 intel_analog_is_connected(struct drm_device *dev)
1413 {
1414 struct drm_connector *analog_connector;
1415
1416 analog_connector = intel_find_analog_connector(dev);
1417 if (!analog_connector)
1418 return false;
1419
1420 if (analog_connector->funcs->detect(analog_connector) ==
1421 connector_status_disconnected)
1422 return false;
1423
1424 return true;
1425 }
1426
1427 enum drm_connector_status
1428 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1429 {
1430 struct drm_encoder *encoder = intel_attached_encoder(connector);
1431 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1432 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1433 enum drm_connector_status status = connector_status_connected;
1434 struct edid *edid = NULL;
1435
1436 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
1437
1438 /* This is only applied to SDVO cards with multiple outputs */
1439 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1440 uint8_t saved_ddc, temp_ddc;
1441 saved_ddc = intel_sdvo->ddc_bus;
1442 temp_ddc = intel_sdvo->ddc_bus >> 1;
1443 /*
1444 * Don't use the 1 as the argument of DDC bus switch to get
1445 * the EDID. It is used for SDVO SPD ROM.
1446 */
1447 while(temp_ddc > 1) {
1448 intel_sdvo->ddc_bus = temp_ddc;
1449 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
1450 if (edid) {
1451 /*
1452 * When we can get the EDID, maybe it is the
1453 * correct DDC bus. Update it.
1454 */
1455 intel_sdvo->ddc_bus = temp_ddc;
1456 break;
1457 }
1458 temp_ddc >>= 1;
1459 }
1460 if (edid == NULL)
1461 intel_sdvo->ddc_bus = saved_ddc;
1462 }
1463 /* when there is no edid and no monitor is connected with VGA
1464 * port, try to use the CRT ddc to read the EDID for DVI-connector
1465 */
1466 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
1467 !intel_analog_is_connected(connector->dev))
1468 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
1469
1470 if (edid != NULL) {
1471 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1472 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
1473
1474 /* DDC bus is shared, match EDID to connector type */
1475 if (is_digital && need_digital)
1476 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
1477 else if (is_digital != need_digital)
1478 status = connector_status_disconnected;
1479
1480 connector->display_info.raw_edid = NULL;
1481 } else
1482 status = connector_status_disconnected;
1483
1484 kfree(edid);
1485
1486 return status;
1487 }
1488
1489 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1490 {
1491 uint16_t response;
1492 struct drm_encoder *encoder = intel_attached_encoder(connector);
1493 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1494 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1495 enum drm_connector_status ret;
1496
1497 if (!intel_sdvo_write_cmd(intel_sdvo,
1498 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1499 return connector_status_unknown;
1500 if (intel_sdvo->is_tv) {
1501 /* add 30ms delay when the output type is SDVO-TV */
1502 mdelay(30);
1503 }
1504 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1505 return connector_status_unknown;
1506
1507 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1508
1509 if (response == 0)
1510 return connector_status_disconnected;
1511
1512 intel_sdvo->attached_output = response;
1513
1514 if ((intel_sdvo_connector->output_flag & response) == 0)
1515 ret = connector_status_disconnected;
1516 else if (response & SDVO_TMDS_MASK)
1517 ret = intel_sdvo_hdmi_sink_detect(connector);
1518 else
1519 ret = connector_status_connected;
1520
1521 /* May update encoder flag for like clock for SDVO TV, etc.*/
1522 if (ret == connector_status_connected) {
1523 intel_sdvo->is_tv = false;
1524 intel_sdvo->is_lvds = false;
1525 intel_sdvo->base.needs_tv_clock = false;
1526
1527 if (response & SDVO_TV_MASK) {
1528 intel_sdvo->is_tv = true;
1529 intel_sdvo->base.needs_tv_clock = true;
1530 }
1531 if (response & SDVO_LVDS_MASK)
1532 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1533 }
1534
1535 return ret;
1536 }
1537
1538 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1539 {
1540 struct drm_encoder *encoder = intel_attached_encoder(connector);
1541 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1542 int num_modes;
1543
1544 /* set the bus switch and get the modes */
1545 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
1546
1547 /*
1548 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1549 * link between analog and digital outputs. So, if the regular SDVO
1550 * DDC fails, check to see if the analog output is disconnected, in
1551 * which case we'll look there for the digital DDC data.
1552 */
1553 if (num_modes == 0 &&
1554 intel_sdvo->analog_ddc_bus &&
1555 !intel_analog_is_connected(connector->dev)) {
1556 /* Switch to the analog ddc bus and try that
1557 */
1558 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
1559 }
1560 }
1561
1562 /*
1563 * Set of SDVO TV modes.
1564 * Note! This is in reply order (see loop in get_tv_modes).
1565 * XXX: all 60Hz refresh?
1566 */
1567 struct drm_display_mode sdvo_tv_modes[] = {
1568 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1569 416, 0, 200, 201, 232, 233, 0,
1570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1571 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1572 416, 0, 240, 241, 272, 273, 0,
1573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1574 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1575 496, 0, 300, 301, 332, 333, 0,
1576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1577 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1578 736, 0, 350, 351, 382, 383, 0,
1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1580 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1581 736, 0, 400, 401, 432, 433, 0,
1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1583 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1584 736, 0, 480, 481, 512, 513, 0,
1585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1586 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1587 800, 0, 480, 481, 512, 513, 0,
1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1589 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1590 800, 0, 576, 577, 608, 609, 0,
1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1592 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1593 816, 0, 350, 351, 382, 383, 0,
1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1595 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1596 816, 0, 400, 401, 432, 433, 0,
1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1598 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1599 816, 0, 480, 481, 512, 513, 0,
1600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1601 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1602 816, 0, 540, 541, 572, 573, 0,
1603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1604 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1605 816, 0, 576, 577, 608, 609, 0,
1606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1607 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1608 864, 0, 576, 577, 608, 609, 0,
1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1611 896, 0, 600, 601, 632, 633, 0,
1612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1613 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1614 928, 0, 624, 625, 656, 657, 0,
1615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1616 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1617 1016, 0, 766, 767, 798, 799, 0,
1618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1620 1120, 0, 768, 769, 800, 801, 0,
1621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1623 1376, 0, 1024, 1025, 1056, 1057, 0,
1624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1625 };
1626
1627 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1628 {
1629 struct drm_encoder *encoder = intel_attached_encoder(connector);
1630 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1631 struct intel_sdvo_sdtv_resolution_request tv_res;
1632 uint32_t reply = 0, format_map = 0;
1633 int i;
1634
1635 /* Read the list of supported input resolutions for the selected TV
1636 * format.
1637 */
1638 format_map = 1 << intel_sdvo->tv_format_index;
1639 memcpy(&tv_res, &format_map,
1640 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1641
1642 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1643 return;
1644
1645 BUILD_BUG_ON(sizeof(tv_res) != 3);
1646 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1647 &tv_res, sizeof(tv_res)))
1648 return;
1649 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1650 return;
1651
1652 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1653 if (reply & (1 << i)) {
1654 struct drm_display_mode *nmode;
1655 nmode = drm_mode_duplicate(connector->dev,
1656 &sdvo_tv_modes[i]);
1657 if (nmode)
1658 drm_mode_probed_add(connector, nmode);
1659 }
1660 }
1661
1662 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1663 {
1664 struct drm_encoder *encoder = intel_attached_encoder(connector);
1665 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1666 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1667 struct drm_display_mode *newmode;
1668
1669 /*
1670 * Attempt to get the mode list from DDC.
1671 * Assume that the preferred modes are
1672 * arranged in priority order.
1673 */
1674 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
1675 if (list_empty(&connector->probed_modes) == false)
1676 goto end;
1677
1678 /* Fetch modes from VBT */
1679 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1680 newmode = drm_mode_duplicate(connector->dev,
1681 dev_priv->sdvo_lvds_vbt_mode);
1682 if (newmode != NULL) {
1683 /* Guarantee the mode is preferred */
1684 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1685 DRM_MODE_TYPE_DRIVER);
1686 drm_mode_probed_add(connector, newmode);
1687 }
1688 }
1689
1690 end:
1691 list_for_each_entry(newmode, &connector->probed_modes, head) {
1692 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1693 intel_sdvo->sdvo_lvds_fixed_mode =
1694 drm_mode_duplicate(connector->dev, newmode);
1695 intel_sdvo->is_lvds = true;
1696 break;
1697 }
1698 }
1699
1700 }
1701
1702 static int intel_sdvo_get_modes(struct drm_connector *connector)
1703 {
1704 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1705
1706 if (IS_TV(intel_sdvo_connector))
1707 intel_sdvo_get_tv_modes(connector);
1708 else if (IS_LVDS(intel_sdvo_connector))
1709 intel_sdvo_get_lvds_modes(connector);
1710 else
1711 intel_sdvo_get_ddc_modes(connector);
1712
1713 return !list_empty(&connector->probed_modes);
1714 }
1715
1716 static void
1717 intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1718 {
1719 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1720 struct drm_device *dev = connector->dev;
1721
1722 if (intel_sdvo_connector->left)
1723 drm_property_destroy(dev, intel_sdvo_connector->left);
1724 if (intel_sdvo_connector->right)
1725 drm_property_destroy(dev, intel_sdvo_connector->right);
1726 if (intel_sdvo_connector->top)
1727 drm_property_destroy(dev, intel_sdvo_connector->top);
1728 if (intel_sdvo_connector->bottom)
1729 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1730 if (intel_sdvo_connector->hpos)
1731 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1732 if (intel_sdvo_connector->vpos)
1733 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1734 if (intel_sdvo_connector->saturation)
1735 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1736 if (intel_sdvo_connector->contrast)
1737 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1738 if (intel_sdvo_connector->hue)
1739 drm_property_destroy(dev, intel_sdvo_connector->hue);
1740 if (intel_sdvo_connector->sharpness)
1741 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1742 if (intel_sdvo_connector->flicker_filter)
1743 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1744 if (intel_sdvo_connector->flicker_filter_2d)
1745 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1746 if (intel_sdvo_connector->flicker_filter_adaptive)
1747 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1748 if (intel_sdvo_connector->tv_luma_filter)
1749 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1750 if (intel_sdvo_connector->tv_chroma_filter)
1751 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1752 if (intel_sdvo_connector->dot_crawl)
1753 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
1754 if (intel_sdvo_connector->brightness)
1755 drm_property_destroy(dev, intel_sdvo_connector->brightness);
1756 }
1757
1758 static void intel_sdvo_destroy(struct drm_connector *connector)
1759 {
1760 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1761
1762 if (intel_sdvo_connector->tv_format)
1763 drm_property_destroy(connector->dev,
1764 intel_sdvo_connector->tv_format);
1765
1766 intel_sdvo_destroy_enhance_property(connector);
1767 drm_sysfs_connector_remove(connector);
1768 drm_connector_cleanup(connector);
1769 kfree(connector);
1770 }
1771
1772 static int
1773 intel_sdvo_set_property(struct drm_connector *connector,
1774 struct drm_property *property,
1775 uint64_t val)
1776 {
1777 struct drm_encoder *encoder = intel_attached_encoder(connector);
1778 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1779 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1780 uint16_t temp_value;
1781 uint8_t cmd;
1782 int ret;
1783
1784 ret = drm_connector_property_set_value(connector, property, val);
1785 if (ret)
1786 return ret;
1787
1788 #define CHECK_PROPERTY(name, NAME) \
1789 if (intel_sdvo_connector->name == property) { \
1790 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1791 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1792 cmd = SDVO_CMD_SET_##NAME; \
1793 intel_sdvo_connector->cur_##name = temp_value; \
1794 goto set_value; \
1795 }
1796
1797 if (property == intel_sdvo_connector->tv_format) {
1798 if (val >= TV_FORMAT_NUM)
1799 return -EINVAL;
1800
1801 if (intel_sdvo->tv_format_index ==
1802 intel_sdvo_connector->tv_format_supported[val])
1803 return 0;
1804
1805 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
1806 goto done;
1807 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
1808 temp_value = val;
1809 if (intel_sdvo_connector->left == property) {
1810 drm_connector_property_set_value(connector,
1811 intel_sdvo_connector->right, val);
1812 if (intel_sdvo_connector->left_margin == temp_value)
1813 return 0;
1814
1815 intel_sdvo_connector->left_margin = temp_value;
1816 intel_sdvo_connector->right_margin = temp_value;
1817 temp_value = intel_sdvo_connector->max_hscan -
1818 intel_sdvo_connector->left_margin;
1819 cmd = SDVO_CMD_SET_OVERSCAN_H;
1820 goto set_value;
1821 } else if (intel_sdvo_connector->right == property) {
1822 drm_connector_property_set_value(connector,
1823 intel_sdvo_connector->left, val);
1824 if (intel_sdvo_connector->right_margin == temp_value)
1825 return 0;
1826
1827 intel_sdvo_connector->left_margin = temp_value;
1828 intel_sdvo_connector->right_margin = temp_value;
1829 temp_value = intel_sdvo_connector->max_hscan -
1830 intel_sdvo_connector->left_margin;
1831 cmd = SDVO_CMD_SET_OVERSCAN_H;
1832 goto set_value;
1833 } else if (intel_sdvo_connector->top == property) {
1834 drm_connector_property_set_value(connector,
1835 intel_sdvo_connector->bottom, val);
1836 if (intel_sdvo_connector->top_margin == temp_value)
1837 return 0;
1838
1839 intel_sdvo_connector->top_margin = temp_value;
1840 intel_sdvo_connector->bottom_margin = temp_value;
1841 temp_value = intel_sdvo_connector->max_vscan -
1842 intel_sdvo_connector->top_margin;
1843 cmd = SDVO_CMD_SET_OVERSCAN_V;
1844 goto set_value;
1845 } else if (intel_sdvo_connector->bottom == property) {
1846 drm_connector_property_set_value(connector,
1847 intel_sdvo_connector->top, val);
1848 if (intel_sdvo_connector->bottom_margin == temp_value)
1849 return 0;
1850
1851 intel_sdvo_connector->top_margin = temp_value;
1852 intel_sdvo_connector->bottom_margin = temp_value;
1853 temp_value = intel_sdvo_connector->max_vscan -
1854 intel_sdvo_connector->top_margin;
1855 cmd = SDVO_CMD_SET_OVERSCAN_V;
1856 goto set_value;
1857 }
1858 CHECK_PROPERTY(hpos, HPOS)
1859 CHECK_PROPERTY(vpos, VPOS)
1860 CHECK_PROPERTY(saturation, SATURATION)
1861 CHECK_PROPERTY(contrast, CONTRAST)
1862 CHECK_PROPERTY(hue, HUE)
1863 CHECK_PROPERTY(brightness, BRIGHTNESS)
1864 CHECK_PROPERTY(sharpness, SHARPNESS)
1865 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1866 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1867 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1868 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1869 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
1870 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
1871 }
1872
1873 return -EINVAL; /* unknown property */
1874
1875 set_value:
1876 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1877 return -EIO;
1878
1879
1880 done:
1881 if (encoder->crtc) {
1882 struct drm_crtc *crtc = encoder->crtc;
1883
1884 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1885 crtc->y, crtc->fb);
1886 }
1887
1888 return 0;
1889 #undef CHECK_PROPERTY
1890 }
1891
1892 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1893 .dpms = intel_sdvo_dpms,
1894 .mode_fixup = intel_sdvo_mode_fixup,
1895 .prepare = intel_encoder_prepare,
1896 .mode_set = intel_sdvo_mode_set,
1897 .commit = intel_encoder_commit,
1898 };
1899
1900 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
1901 .dpms = drm_helper_connector_dpms,
1902 .detect = intel_sdvo_detect,
1903 .fill_modes = drm_helper_probe_single_connector_modes,
1904 .set_property = intel_sdvo_set_property,
1905 .destroy = intel_sdvo_destroy,
1906 };
1907
1908 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1909 .get_modes = intel_sdvo_get_modes,
1910 .mode_valid = intel_sdvo_mode_valid,
1911 .best_encoder = intel_attached_encoder,
1912 };
1913
1914 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
1915 {
1916 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1917
1918 if (intel_sdvo->analog_ddc_bus)
1919 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
1920
1921 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
1922 drm_mode_destroy(encoder->dev,
1923 intel_sdvo->sdvo_lvds_fixed_mode);
1924
1925 intel_encoder_destroy(encoder);
1926 }
1927
1928 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1929 .destroy = intel_sdvo_enc_destroy,
1930 };
1931
1932
1933 /**
1934 * Choose the appropriate DDC bus for control bus switch command for this
1935 * SDVO output based on the controlled output.
1936 *
1937 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1938 * outputs, then LVDS outputs.
1939 */
1940 static void
1941 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
1942 struct intel_sdvo *sdvo, u32 reg)
1943 {
1944 struct sdvo_device_mapping *mapping;
1945
1946 if (IS_SDVOB(reg))
1947 mapping = &(dev_priv->sdvo_mappings[0]);
1948 else
1949 mapping = &(dev_priv->sdvo_mappings[1]);
1950
1951 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1952 }
1953
1954 static bool
1955 intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
1956 {
1957 return intel_sdvo_set_target_output(intel_sdvo,
1958 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1959 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1960 &intel_sdvo->is_hdmi, 1);
1961 }
1962
1963 static struct intel_sdvo *
1964 intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
1965 {
1966 struct drm_device *dev = chan->drm_dev;
1967 struct drm_encoder *encoder;
1968
1969 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1970 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1971 if (intel_sdvo->base.ddc_bus == &chan->adapter)
1972 return intel_sdvo;
1973 }
1974
1975 return NULL;
1976 }
1977
1978 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1979 struct i2c_msg msgs[], int num)
1980 {
1981 struct intel_sdvo *intel_sdvo;
1982 struct i2c_algo_bit_data *algo_data;
1983 const struct i2c_algorithm *algo;
1984
1985 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1986 intel_sdvo =
1987 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
1988 (algo_data->data));
1989 if (intel_sdvo == NULL)
1990 return -EINVAL;
1991
1992 algo = intel_sdvo->base.i2c_bus->algo;
1993
1994 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
1995 return algo->master_xfer(i2c_adap, msgs, num);
1996 }
1997
1998 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1999 .master_xfer = intel_sdvo_master_xfer,
2000 };
2001
2002 static u8
2003 intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2004 {
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 struct sdvo_device_mapping *my_mapping, *other_mapping;
2007
2008 if (IS_SDVOB(sdvo_reg)) {
2009 my_mapping = &dev_priv->sdvo_mappings[0];
2010 other_mapping = &dev_priv->sdvo_mappings[1];
2011 } else {
2012 my_mapping = &dev_priv->sdvo_mappings[1];
2013 other_mapping = &dev_priv->sdvo_mappings[0];
2014 }
2015
2016 /* If the BIOS described our SDVO device, take advantage of it. */
2017 if (my_mapping->slave_addr)
2018 return my_mapping->slave_addr;
2019
2020 /* If the BIOS only described a different SDVO device, use the
2021 * address that it isn't using.
2022 */
2023 if (other_mapping->slave_addr) {
2024 if (other_mapping->slave_addr == 0x70)
2025 return 0x72;
2026 else
2027 return 0x70;
2028 }
2029
2030 /* No SDVO device info is found for another DVO port,
2031 * so use mapping assumption we had before BIOS parsing.
2032 */
2033 if (IS_SDVOB(sdvo_reg))
2034 return 0x70;
2035 else
2036 return 0x72;
2037 }
2038
2039 static void
2040 intel_sdvo_connector_init(struct drm_encoder *encoder,
2041 struct drm_connector *connector)
2042 {
2043 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2044 connector->connector_type);
2045
2046 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2047
2048 connector->interlace_allowed = 0;
2049 connector->doublescan_allowed = 0;
2050 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2051
2052 drm_mode_connector_attach_encoder(connector, encoder);
2053 drm_sysfs_connector_add(connector);
2054 }
2055
2056 static bool
2057 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2058 {
2059 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2060 struct drm_connector *connector;
2061 struct intel_connector *intel_connector;
2062 struct intel_sdvo_connector *intel_sdvo_connector;
2063
2064 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2065 if (!intel_sdvo_connector)
2066 return false;
2067
2068 if (device == 0) {
2069 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2070 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2071 } else if (device == 1) {
2072 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2073 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2074 }
2075
2076 intel_connector = &intel_sdvo_connector->base;
2077 connector = &intel_connector->base;
2078 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2079 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2080 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2081
2082 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2083 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2084 && intel_sdvo->is_hdmi) {
2085 /* enable hdmi encoding mode if supported */
2086 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2087 intel_sdvo_set_colorimetry(intel_sdvo,
2088 SDVO_COLORIMETRY_RGB256);
2089 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2090 }
2091 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2092 (1 << INTEL_ANALOG_CLONE_BIT));
2093
2094 intel_sdvo_connector_init(encoder, connector);
2095
2096 return true;
2097 }
2098
2099 static bool
2100 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2101 {
2102 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2103 struct drm_connector *connector;
2104 struct intel_connector *intel_connector;
2105 struct intel_sdvo_connector *intel_sdvo_connector;
2106
2107 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2108 if (!intel_sdvo_connector)
2109 return false;
2110
2111 intel_connector = &intel_sdvo_connector->base;
2112 connector = &intel_connector->base;
2113 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2114 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2115
2116 intel_sdvo->controlled_output |= type;
2117 intel_sdvo_connector->output_flag = type;
2118
2119 intel_sdvo->is_tv = true;
2120 intel_sdvo->base.needs_tv_clock = true;
2121 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2122
2123 intel_sdvo_connector_init(encoder, connector);
2124
2125 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2126 goto err;
2127
2128 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2129 goto err;
2130
2131 return true;
2132
2133 err:
2134 intel_sdvo_destroy_enhance_property(connector);
2135 kfree(intel_sdvo_connector);
2136 return false;
2137 }
2138
2139 static bool
2140 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2141 {
2142 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2143 struct drm_connector *connector;
2144 struct intel_connector *intel_connector;
2145 struct intel_sdvo_connector *intel_sdvo_connector;
2146
2147 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2148 if (!intel_sdvo_connector)
2149 return false;
2150
2151 intel_connector = &intel_sdvo_connector->base;
2152 connector = &intel_connector->base;
2153 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2154 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2155 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2156
2157 if (device == 0) {
2158 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2159 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2160 } else if (device == 1) {
2161 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2162 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2163 }
2164
2165 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2166 (1 << INTEL_ANALOG_CLONE_BIT));
2167
2168 intel_sdvo_connector_init(encoder, connector);
2169 return true;
2170 }
2171
2172 static bool
2173 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2174 {
2175 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2176 struct drm_connector *connector;
2177 struct intel_connector *intel_connector;
2178 struct intel_sdvo_connector *intel_sdvo_connector;
2179
2180 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2181 if (!intel_sdvo_connector)
2182 return false;
2183
2184 intel_connector = &intel_sdvo_connector->base;
2185 connector = &intel_connector->base;
2186 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2187 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2188
2189 if (device == 0) {
2190 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2191 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2192 } else if (device == 1) {
2193 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2194 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2195 }
2196
2197 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2198 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
2199
2200 intel_sdvo_connector_init(encoder, connector);
2201 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2202 goto err;
2203
2204 return true;
2205
2206 err:
2207 intel_sdvo_destroy_enhance_property(connector);
2208 kfree(intel_sdvo_connector);
2209 return false;
2210 }
2211
2212 static bool
2213 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2214 {
2215 intel_sdvo->is_tv = false;
2216 intel_sdvo->base.needs_tv_clock = false;
2217 intel_sdvo->is_lvds = false;
2218
2219 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2220
2221 if (flags & SDVO_OUTPUT_TMDS0)
2222 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2223 return false;
2224
2225 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2226 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2227 return false;
2228
2229 /* TV has no XXX1 function block */
2230 if (flags & SDVO_OUTPUT_SVID0)
2231 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2232 return false;
2233
2234 if (flags & SDVO_OUTPUT_CVBS0)
2235 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2236 return false;
2237
2238 if (flags & SDVO_OUTPUT_RGB0)
2239 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2240 return false;
2241
2242 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2243 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2244 return false;
2245
2246 if (flags & SDVO_OUTPUT_LVDS0)
2247 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2248 return false;
2249
2250 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2251 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2252 return false;
2253
2254 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2255 unsigned char bytes[2];
2256
2257 intel_sdvo->controlled_output = 0;
2258 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2259 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2260 SDVO_NAME(intel_sdvo),
2261 bytes[0], bytes[1]);
2262 return false;
2263 }
2264 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
2265
2266 return true;
2267 }
2268
2269 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2270 struct intel_sdvo_connector *intel_sdvo_connector,
2271 int type)
2272 {
2273 struct drm_device *dev = intel_sdvo->base.enc.dev;
2274 struct intel_sdvo_tv_format format;
2275 uint32_t format_map, i;
2276
2277 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2278 return false;
2279
2280 if (!intel_sdvo_get_value(intel_sdvo,
2281 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2282 &format, sizeof(format)))
2283 return false;
2284
2285 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2286
2287 if (format_map == 0)
2288 return false;
2289
2290 intel_sdvo_connector->format_supported_num = 0;
2291 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2292 if (format_map & (1 << i))
2293 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2294
2295
2296 intel_sdvo_connector->tv_format =
2297 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2298 "mode", intel_sdvo_connector->format_supported_num);
2299 if (!intel_sdvo_connector->tv_format)
2300 return false;
2301
2302 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2303 drm_property_add_enum(
2304 intel_sdvo_connector->tv_format, i,
2305 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2306
2307 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2308 drm_connector_attach_property(&intel_sdvo_connector->base.base,
2309 intel_sdvo_connector->tv_format, 0);
2310 return true;
2311
2312 }
2313
2314 #define ENHANCEMENT(name, NAME) do { \
2315 if (enhancements.name) { \
2316 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2317 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2318 return false; \
2319 intel_sdvo_connector->max_##name = data_value[0]; \
2320 intel_sdvo_connector->cur_##name = response; \
2321 intel_sdvo_connector->name = \
2322 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2323 if (!intel_sdvo_connector->name) return false; \
2324 intel_sdvo_connector->name->values[0] = 0; \
2325 intel_sdvo_connector->name->values[1] = data_value[0]; \
2326 drm_connector_attach_property(connector, \
2327 intel_sdvo_connector->name, \
2328 intel_sdvo_connector->cur_##name); \
2329 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2330 data_value[0], data_value[1], response); \
2331 } \
2332 } while(0)
2333
2334 static bool
2335 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2336 struct intel_sdvo_connector *intel_sdvo_connector,
2337 struct intel_sdvo_enhancements_reply enhancements)
2338 {
2339 struct drm_device *dev = intel_sdvo->base.enc.dev;
2340 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2341 uint16_t response, data_value[2];
2342
2343 /* when horizontal overscan is supported, Add the left/right property */
2344 if (enhancements.overscan_h) {
2345 if (!intel_sdvo_get_value(intel_sdvo,
2346 SDVO_CMD_GET_MAX_OVERSCAN_H,
2347 &data_value, 4))
2348 return false;
2349
2350 if (!intel_sdvo_get_value(intel_sdvo,
2351 SDVO_CMD_GET_OVERSCAN_H,
2352 &response, 2))
2353 return false;
2354
2355 intel_sdvo_connector->max_hscan = data_value[0];
2356 intel_sdvo_connector->left_margin = data_value[0] - response;
2357 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2358 intel_sdvo_connector->left =
2359 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2360 "left_margin", 2);
2361 if (!intel_sdvo_connector->left)
2362 return false;
2363
2364 intel_sdvo_connector->left->values[0] = 0;
2365 intel_sdvo_connector->left->values[1] = data_value[0];
2366 drm_connector_attach_property(connector,
2367 intel_sdvo_connector->left,
2368 intel_sdvo_connector->left_margin);
2369
2370 intel_sdvo_connector->right =
2371 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2372 "right_margin", 2);
2373 if (!intel_sdvo_connector->right)
2374 return false;
2375
2376 intel_sdvo_connector->right->values[0] = 0;
2377 intel_sdvo_connector->right->values[1] = data_value[0];
2378 drm_connector_attach_property(connector,
2379 intel_sdvo_connector->right,
2380 intel_sdvo_connector->right_margin);
2381 DRM_DEBUG_KMS("h_overscan: max %d, "
2382 "default %d, current %d\n",
2383 data_value[0], data_value[1], response);
2384 }
2385
2386 if (enhancements.overscan_v) {
2387 if (!intel_sdvo_get_value(intel_sdvo,
2388 SDVO_CMD_GET_MAX_OVERSCAN_V,
2389 &data_value, 4))
2390 return false;
2391
2392 if (!intel_sdvo_get_value(intel_sdvo,
2393 SDVO_CMD_GET_OVERSCAN_V,
2394 &response, 2))
2395 return false;
2396
2397 intel_sdvo_connector->max_vscan = data_value[0];
2398 intel_sdvo_connector->top_margin = data_value[0] - response;
2399 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2400 intel_sdvo_connector->top =
2401 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2402 "top_margin", 2);
2403 if (!intel_sdvo_connector->top)
2404 return false;
2405
2406 intel_sdvo_connector->top->values[0] = 0;
2407 intel_sdvo_connector->top->values[1] = data_value[0];
2408 drm_connector_attach_property(connector,
2409 intel_sdvo_connector->top,
2410 intel_sdvo_connector->top_margin);
2411
2412 intel_sdvo_connector->bottom =
2413 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2414 "bottom_margin", 2);
2415 if (!intel_sdvo_connector->bottom)
2416 return false;
2417
2418 intel_sdvo_connector->bottom->values[0] = 0;
2419 intel_sdvo_connector->bottom->values[1] = data_value[0];
2420 drm_connector_attach_property(connector,
2421 intel_sdvo_connector->bottom,
2422 intel_sdvo_connector->bottom_margin);
2423 DRM_DEBUG_KMS("v_overscan: max %d, "
2424 "default %d, current %d\n",
2425 data_value[0], data_value[1], response);
2426 }
2427
2428 ENHANCEMENT(hpos, HPOS);
2429 ENHANCEMENT(vpos, VPOS);
2430 ENHANCEMENT(saturation, SATURATION);
2431 ENHANCEMENT(contrast, CONTRAST);
2432 ENHANCEMENT(hue, HUE);
2433 ENHANCEMENT(sharpness, SHARPNESS);
2434 ENHANCEMENT(brightness, BRIGHTNESS);
2435 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2436 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2437 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2438 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2439 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2440
2441 if (enhancements.dot_crawl) {
2442 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2443 return false;
2444
2445 intel_sdvo_connector->max_dot_crawl = 1;
2446 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2447 intel_sdvo_connector->dot_crawl =
2448 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2449 if (!intel_sdvo_connector->dot_crawl)
2450 return false;
2451
2452 intel_sdvo_connector->dot_crawl->values[0] = 0;
2453 intel_sdvo_connector->dot_crawl->values[1] = 1;
2454 drm_connector_attach_property(connector,
2455 intel_sdvo_connector->dot_crawl,
2456 intel_sdvo_connector->cur_dot_crawl);
2457 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2458 }
2459
2460 return true;
2461 }
2462
2463 static bool
2464 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2465 struct intel_sdvo_connector *intel_sdvo_connector,
2466 struct intel_sdvo_enhancements_reply enhancements)
2467 {
2468 struct drm_device *dev = intel_sdvo->base.enc.dev;
2469 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2470 uint16_t response, data_value[2];
2471
2472 ENHANCEMENT(brightness, BRIGHTNESS);
2473
2474 return true;
2475 }
2476 #undef ENHANCEMENT
2477
2478 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2479 struct intel_sdvo_connector *intel_sdvo_connector)
2480 {
2481 union {
2482 struct intel_sdvo_enhancements_reply reply;
2483 uint16_t response;
2484 } enhancements;
2485
2486 if (!intel_sdvo_get_value(intel_sdvo,
2487 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2488 &enhancements, sizeof(enhancements)))
2489 return false;
2490
2491 if (enhancements.response == 0) {
2492 DRM_DEBUG_KMS("No enhancement is supported\n");
2493 return true;
2494 }
2495
2496 if (IS_TV(intel_sdvo_connector))
2497 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2498 else if(IS_LVDS(intel_sdvo_connector))
2499 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2500 else
2501 return true;
2502
2503 }
2504
2505 bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2506 {
2507 struct drm_i915_private *dev_priv = dev->dev_private;
2508 struct intel_encoder *intel_encoder;
2509 struct intel_sdvo *intel_sdvo;
2510 u8 ch[0x40];
2511 int i;
2512 u32 i2c_reg, ddc_reg, analog_ddc_reg;
2513
2514 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2515 if (!intel_sdvo)
2516 return false;
2517
2518 intel_sdvo->sdvo_reg = sdvo_reg;
2519
2520 intel_encoder = &intel_sdvo->base;
2521 intel_encoder->type = INTEL_OUTPUT_SDVO;
2522
2523 if (HAS_PCH_SPLIT(dev)) {
2524 i2c_reg = PCH_GPIOE;
2525 ddc_reg = PCH_GPIOE;
2526 analog_ddc_reg = PCH_GPIOA;
2527 } else {
2528 i2c_reg = GPIOE;
2529 ddc_reg = GPIOE;
2530 analog_ddc_reg = GPIOA;
2531 }
2532
2533 /* setup the DDC bus. */
2534 if (IS_SDVOB(sdvo_reg))
2535 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
2536 else
2537 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
2538
2539 if (!intel_encoder->i2c_bus)
2540 goto err_inteloutput;
2541
2542 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2543
2544 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2545 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2546
2547 /* Read the regs to test if we can talk to the device */
2548 for (i = 0; i < 0x40; i++) {
2549 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
2550 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2551 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2552 goto err_i2c;
2553 }
2554 }
2555
2556 /* setup the DDC bus. */
2557 if (IS_SDVOB(sdvo_reg)) {
2558 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
2559 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2560 "SDVOB/VGA DDC BUS");
2561 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2562 } else {
2563 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
2564 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2565 "SDVOC/VGA DDC BUS");
2566 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2567 }
2568 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
2569 goto err_i2c;
2570
2571 /* Wrap with our custom algo which switches to DDC mode */
2572 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2573
2574 /* encoder type will be decided later */
2575 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2576 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2577
2578 /* In default case sdvo lvds is false */
2579 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2580 goto err_enc;
2581
2582 if (intel_sdvo_output_setup(intel_sdvo,
2583 intel_sdvo->caps.output_flags) != true) {
2584 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2585 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2586 goto err_enc;
2587 }
2588
2589 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2590
2591 /* Set the input timing to the screen. Assume always input 0. */
2592 if (!intel_sdvo_set_target_input(intel_sdvo))
2593 goto err_enc;
2594
2595 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2596 &intel_sdvo->pixel_clock_min,
2597 &intel_sdvo->pixel_clock_max))
2598 goto err_enc;
2599
2600 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2601 "clock range %dMHz - %dMHz, "
2602 "input 1: %c, input 2: %c, "
2603 "output 1: %c, output 2: %c\n",
2604 SDVO_NAME(intel_sdvo),
2605 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2606 intel_sdvo->caps.device_rev_id,
2607 intel_sdvo->pixel_clock_min / 1000,
2608 intel_sdvo->pixel_clock_max / 1000,
2609 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2610 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2611 /* check currently supported outputs */
2612 intel_sdvo->caps.output_flags &
2613 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2614 intel_sdvo->caps.output_flags &
2615 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2616 return true;
2617
2618 err_enc:
2619 drm_encoder_cleanup(&intel_encoder->enc);
2620 err_i2c:
2621 if (intel_sdvo->analog_ddc_bus != NULL)
2622 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
2623 if (intel_encoder->ddc_bus != NULL)
2624 intel_i2c_destroy(intel_encoder->ddc_bus);
2625 if (intel_encoder->i2c_bus != NULL)
2626 intel_i2c_destroy(intel_encoder->i2c_bus);
2627 err_inteloutput:
2628 kfree(intel_sdvo);
2629
2630 return false;
2631 }