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(parent: f1c66c4) | patch
tile/PCI: use cached pci_dev->pcie_mpss to simplify code
authorYijing Wang <wangyijing@huawei.com>
Mon, 9 Sep 2013 13:13:04 +0000 (21:13 +0800)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 24 Sep 2013 18:10:04 +0000 (12:10 -0600)
commit503275bf371fbab01a14f2e9fd1ac7aa20c81645
tree295daeca82f990fce2400440234526af6b1bb264tree | snapshot (tar.gz zip)
parentf1c66c4678ad223bda0dcd261e4048f009234f85commit | diff
tile/PCI: use cached pci_dev->pcie_mpss to simplify code

The PCI core caches the "PCIe Max Payload Size Supported" in
pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword().

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
arch/tile/kernel/pci.c diff | blob | blame | history