clk: gxbb: add the SAR ADC clocks and expose them
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Thu, 19 Jan 2017 14:58:20 +0000 (15:58 +0100)
committerKevin Hilman <khilman@baylibre.com>
Mon, 23 Jan 2017 18:18:21 +0000 (10:18 -0800)
commit33d0fcdfe0e87070d96c678e554d711ae15b9fa6
tree572705e9afdd982329b78e7c592fdc949ddbf3e5
parent0264a88d6153e6cd5ee61239058b2002f36dde6b
clk: gxbb: add the SAR ADC clocks and expose them

The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
  2-bit wide, but the datasheet only lists the parents for the first
  bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock

Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
drivers/clk/meson/gxbb.c
drivers/clk/meson/gxbb.h
include/dt-bindings/clock/gxbb-clkc.h