git.stricted.de - GitHub/LineageOS/android_kernel_motorola

1 /**

2 * @file nmi_int.c

3 *

5 * @remark Read the file COPYING

6 *

7 * @author John Levon <levon@movementarian.org>

8 * @author Robert Richter <robert.richter@amd.com>

9 */

11 #include <linux/init.h>

12 #include <linux/notifier.h>

13 #include <linux/smp.h>

14 #include <linux/oprofile.h>

15 #include <linux/sysdev.h>

16 #include <linux/slab.h>

17 #include <linux/moduleparam.h>

18 #include <linux/kdebug.h>

19 #include <linux/cpu.h>

20 #include <asm/nmi.h>

21 #include <asm/msr.h>

22 #include <asm/apic.h>

24 #include "op_counter.h"

25 #include "op_x86_model.h"

27 static struct op_x86_model_spec const *model;

28 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);

29 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

31 /* 0 == registered but off, 1 == registered and on */

32 static int nmi_enabled = 0;

34 static int profile_exceptions_notify(struct notifier_block *self,

35 unsigned long val, void *data)

36 {

37 struct die_args *args = (struct die_args *)data;

38 int ret = NOTIFY_DONE;

39 int cpu = smp_processor_id();

41 switch (val) {

42 case DIE_NMI:

43 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))

44 ret = NOTIFY_STOP;

45 break;

46 default:

47 break;

48 }

49 return ret;

50 }

52 static void nmi_cpu_save_registers(struct op_msrs *msrs)

53 {

54 unsigned int const nr_ctrs = model->num_counters;

55 unsigned int const nr_ctrls = model->num_controls;

56 struct op_msr *counters = msrs->counters;

57 struct op_msr *controls = msrs->controls;

58 unsigned int i;

60 for (i = 0; i < nr_ctrs; ++i) {

61 if (counters[i].addr) {

62 rdmsr(counters[i].addr,

63 counters[i].saved.low,

64 counters[i].saved.high);

65 }

66 }

68 for (i = 0; i < nr_ctrls; ++i) {

69 if (controls[i].addr) {

70 rdmsr(controls[i].addr,

71 controls[i].saved.low,

72 controls[i].saved.high);

73 }

74 }

75 }

77 static void nmi_save_registers(void *dummy)

78 {

79 int cpu = smp_processor_id();

80 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

81 nmi_cpu_save_registers(msrs);

82 }

84 static void free_msrs(void)

85 {

86 int i;

87 for_each_possible_cpu(i) {

88 kfree(per_cpu(cpu_msrs, i).counters);

89 per_cpu(cpu_msrs, i).counters = NULL;

90 kfree(per_cpu(cpu_msrs, i).controls);

91 per_cpu(cpu_msrs, i).controls = NULL;

92 }

93 }

95 static int allocate_msrs(void)

96 {

97 int success = 1;

98 size_t controls_size = sizeof(struct op_msr) * model->num_controls;

99 size_t counters_size = sizeof(struct op_msr) * model->num_counters;

100

101 int i;

102 for_each_possible_cpu(i) {

103 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,

104 GFP_KERNEL);

105 if (!per_cpu(cpu_msrs, i).counters) {

106 success = 0;

107 break;

108 }

109 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,

110 GFP_KERNEL);

111 if (!per_cpu(cpu_msrs, i).controls) {

112 success = 0;

113 break;

114 }

115 }

116

117 if (!success)

118 free_msrs();

119

120 return success;

121 }

122

123 static void nmi_cpu_setup(void *dummy)

124 {

125 int cpu = smp_processor_id();

126 struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

127 spin_lock(&oprofilefs_lock);

128 model->setup_ctrs(msrs);

129 spin_unlock(&oprofilefs_lock);

130 per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);

131 apic_write(APIC_LVTPC, APIC_DM_NMI);

132 }

133

134 static struct notifier_block profile_exceptions_nb = {

135 .notifier_call = profile_exceptions_notify,

136 .next = NULL,

137 .priority = 0

138 };

139

140 static int nmi_setup(void)

141 {

142 int err = 0;

143 int cpu;

144

145 if (!allocate_msrs())

146 return -ENOMEM;

147

148 err = register_die_notifier(&profile_exceptions_nb);

149 if (err) {

150 free_msrs();

151 return err;

152 }

153

154 /* We need to serialize save and setup for HT because the subset

155 * of msrs are distinct for save and setup operations

156 */

157

158 /* Assume saved/restored counters are the same on all CPUs */

159 model->fill_in_addresses(&per_cpu(cpu_msrs, 0));

160 for_each_possible_cpu(cpu) {

161 if (cpu != 0) {

162 memcpy(per_cpu(cpu_msrs, cpu).counters,

163 per_cpu(cpu_msrs, 0).counters,

164 sizeof(struct op_msr) * model->num_counters);

165

166 memcpy(per_cpu(cpu_msrs, cpu).controls,

167 per_cpu(cpu_msrs, 0).controls,

168 sizeof(struct op_msr) * model->num_controls);

169 }

170

171 }

172 on_each_cpu(nmi_save_registers, NULL, 1);

173 on_each_cpu(nmi_cpu_setup, NULL, 1);

174 nmi_enabled = 1;

175 return 0;

176 }

177

178 static void nmi_restore_registers(struct op_msrs *msrs)

179 {

180 unsigned int const nr_ctrs = model->num_counters;

181 unsigned int const nr_ctrls = model->num_controls;

182 struct op_msr *counters = msrs->counters;

183 struct op_msr *controls = msrs->controls;

184 unsigned int i;

185

186 for (i = 0; i < nr_ctrls; ++i) {

187 if (controls[i].addr) {

188 wrmsr(controls[i].addr,

189 controls[i].saved.low,

190 controls[i].saved.high);

191 }

192 }

193

194 for (i = 0; i < nr_ctrs; ++i) {

195 if (counters[i].addr) {

196 wrmsr(counters[i].addr,

197 counters[i].saved.low,

198 counters[i].saved.high);

199 }

200 }

201 }

202

203 static void nmi_cpu_shutdown(void *dummy)

204 {

205 unsigned int v;

206 int cpu = smp_processor_id();

207 struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

208

209 /* restoring APIC_LVTPC can trigger an apic error because the delivery

210 * mode and vector nr combination can be illegal. That's by design: on

211 * power on apic lvt contain a zero vector nr which are legal only for

212 * NMI delivery mode. So inhibit apic err before restoring lvtpc

213 */

214 v = apic_read(APIC_LVTERR);

215 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);

216 apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));

217 apic_write(APIC_LVTERR, v);

218 nmi_restore_registers(msrs);

219 }

220

221 static void nmi_shutdown(void)

222 {

223 struct op_msrs *msrs;

224

225 nmi_enabled = 0;

226 on_each_cpu(nmi_cpu_shutdown, NULL, 1);

227 unregister_die_notifier(&profile_exceptions_nb);

228 msrs = &get_cpu_var(cpu_msrs);

229 model->shutdown(msrs);

230 free_msrs();

231 put_cpu_var(cpu_msrs);

232 }

233

234 static void nmi_cpu_start(void *dummy)

235 {

236 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);

237 model->start(msrs);

238 }

239

240 static int nmi_start(void)

241 {

242 on_each_cpu(nmi_cpu_start, NULL, 1);

243 return 0;

244 }

245

246 static void nmi_cpu_stop(void *dummy)

247 {

248 struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);

249 model->stop(msrs);

250 }

251

252 static void nmi_stop(void)

253 {

254 on_each_cpu(nmi_cpu_stop, NULL, 1);

255 }

256

257 struct op_counter_config counter_config[OP_MAX_COUNTER];

258

259 static int nmi_create_files(struct super_block *sb, struct dentry *root)

260 {

261 unsigned int i;

262

263 for (i = 0; i < model->num_counters; ++i) {

264 struct dentry *dir;

265 char buf[4];

266

267 /* quick little hack to _not_ expose a counter if it is not

268 * available for use. This should protect userspace app.

269 * NOTE: assumes 1:1 mapping here (that counters are organized

270 * sequentially in their struct assignment).

271 */

272 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))

273 continue;

274

275 snprintf(buf, sizeof(buf), "%d", i);

276 dir = oprofilefs_mkdir(sb, root, buf);

277 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);

278 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);

279 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);

280 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);

281 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);

282 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);

283 }

284

285 return 0;

286 }

287

288 #ifdef CONFIG_SMP

289 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,

290 void *data)

291 {

292 int cpu = (unsigned long)data;

293 switch (action) {

294 case CPU_DOWN_FAILED:

295 case CPU_ONLINE:

296 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);

297 break;

298 case CPU_DOWN_PREPARE:

299 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);

300 break;

301 }

302 return NOTIFY_DONE;

303 }

304

305 static struct notifier_block oprofile_cpu_nb = {

306 .notifier_call = oprofile_cpu_notifier

307 };

308 #endif

309

310 #ifdef CONFIG_PM

311

312 static int nmi_suspend(struct sys_device *dev, pm_message_t state)

313 {

314 /* Only one CPU left, just stop that one */

315 if (nmi_enabled == 1)

316 nmi_cpu_stop(NULL);

317 return 0;

318 }

319

320 static int nmi_resume(struct sys_device *dev)

321 {

322 if (nmi_enabled == 1)

323 nmi_cpu_start(NULL);

324 return 0;

325 }

326

327 static struct sysdev_class oprofile_sysclass = {

328 .name = "oprofile",

329 .resume = nmi_resume,

330 .suspend = nmi_suspend,

331 };

332

333 static struct sys_device device_oprofile = {

334 .id = 0,

335 .cls = &oprofile_sysclass,

336 };

337

338 static int __init init_sysfs(void)

339 {

340 int error;

341

342 error = sysdev_class_register(&oprofile_sysclass);

343 if (!error)

344 error = sysdev_register(&device_oprofile);

345 return error;

346 }

347

348 static void exit_sysfs(void)

349 {

350 sysdev_unregister(&device_oprofile);

351 sysdev_class_unregister(&oprofile_sysclass);

352 }

353

354 #else

355 #define init_sysfs() do { } while (0)

356 #define exit_sysfs() do { } while (0)

357 #endif /* CONFIG_PM */

358

359 static int p4force;

360 module_param(p4force, int, 0);

361

362 static int __init p4_init(char **cpu_type)

363 {

364 __u8 cpu_model = boot_cpu_data.x86_model;

365

366 if (!p4force && (cpu_model > 6 || cpu_model == 5))

367 return 0;

368

369 #ifndef CONFIG_SMP

370 *cpu_type = "i386/p4";

371 model = &op_p4_spec;

372 return 1;

373 #else

374 switch (smp_num_siblings) {

375 case 1:

376 *cpu_type = "i386/p4";

377 model = &op_p4_spec;

378 return 1;

379

380 case 2:

381 *cpu_type = "i386/p4-ht";

382 model = &op_p4_ht2_spec;

383 return 1;

384 }

385 #endif

386

387 printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");

388 printk(KERN_INFO "oprofile: Reverting to timer mode.\n");

389 return 0;

390 }

391

392 static int __init ppro_init(char **cpu_type)

393 {

394 __u8 cpu_model = boot_cpu_data.x86_model;

395

396 switch (cpu_model) {

397 case 0 ... 2:

398 *cpu_type = "i386/ppro";

399 break;

400 case 3 ... 5:

401 *cpu_type = "i386/pii";

402 break;

403 case 6 ... 8:

404 *cpu_type = "i386/piii";

405 break;

406 case 9:

407 *cpu_type = "i386/p6_mobile";

408 break;

409 case 10 ... 13:

410 *cpu_type = "i386/p6";

411 break;

412 case 14:

413 *cpu_type = "i386/core";

414 break;

415 case 15: case 23:

416 *cpu_type = "i386/core_2";

417 break;

418 default:

419 /* Unknown */

420 return 0;

421 }

422

423 model = &op_ppro_spec;

424 return 1;

425 }

426

427 static int __init arch_perfmon_init(char **cpu_type)

428 {

429 if (!cpu_has_arch_perfmon)

430 return 0;

431 *cpu_type = "i386/arch_perfmon";

432 model = &op_arch_perfmon_spec;

433 arch_perfmon_setup_counters();

434 return 1;

435 }

436

437 /* in order to get sysfs right */

438 static int using_nmi;

439

440 int __init op_nmi_init(struct oprofile_operations *ops)

441 {

442 __u8 vendor = boot_cpu_data.x86_vendor;

443 __u8 family = boot_cpu_data.x86;

444 char *cpu_type = NULL;

445 int ret = 0;

446

447 if (!cpu_has_apic)

448 return -ENODEV;

449

450 switch (vendor) {

451 case X86_VENDOR_AMD:

452 /* Needs to be at least an Athlon (or hammer in 32bit mode) */

453

454 switch (family) {

455 default:

456 return -ENODEV;

457 case 6:

458 model = &op_amd_spec;

459 cpu_type = "i386/athlon";

460 break;

461 case 0xf:

462 model = &op_amd_spec;

463 /* Actually it could be i386/hammer too, but give

464 user space an consistent name. */

465 cpu_type = "x86-64/hammer";

466 break;

467 case 0x10:

468 model = &op_amd_spec;

469 cpu_type = "x86-64/family10";

470 break;

471 case 0x11:

472 model = &op_amd_spec;

473 cpu_type = "x86-64/family11h";

474 break;

475 }

476 break;

477

478 case X86_VENDOR_INTEL:

479 switch (family) {

480 /* Pentium IV */

481 case 0xf:

482 p4_init(&cpu_type);

483 break;

484

485 /* A P6-class processor */

486 case 6:

487 ppro_init(&cpu_type);

488 break;

489

490 default:

491 break;

492 }

493

494 if (!cpu_type && !arch_perfmon_init(&cpu_type))

495 return -ENODEV;

496 break;

497

498 default:

499 return -ENODEV;

500 }

501

502 #ifdef CONFIG_SMP

503 register_cpu_notifier(&oprofile_cpu_nb);

504 #endif

505 /* default values, can be overwritten by model */

506 ops->create_files = nmi_create_files;

507 ops->setup = nmi_setup;

508 ops->shutdown = nmi_shutdown;

509 ops->start = nmi_start;

510 ops->stop = nmi_stop;

511 ops->cpu_type = cpu_type;

512

513 if (model->init)

514 ret = model->init(ops);

515 if (ret)

516 return ret;

517

518 init_sysfs();

519 using_nmi = 1;

520 printk(KERN_INFO "oprofile: using NMI interrupt.\n");

521 return 0;

522 }

523

524 void op_nmi_exit(void)

525 {

526 if (using_nmi) {

527 exit_sysfs();

528 #ifdef CONFIG_SMP

529 unregister_cpu_notifier(&oprofile_cpu_nb);

530 #endif

531 }

532 if (model->exit)

533 model->exit();

534 }