GitHub/exynos8895/android_kernel_samsung_universal8895.git
12 years agodrm/i915: add ValleyView clock gating init
Jesse Barnes [Wed, 28 Mar 2012 20:39:26 +0000 (13:39 -0700)]
drm/i915: add ValleyView clock gating init

Set required clock gating and chicken bits on VLV.

v2: set PIXEL_SUBSPAN_COLLECT_OPT_DISABLE too (Ben)
    move function below ivb version to pretend to be consistent (Ben)

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add DPIO support
Jesse Barnes [Wed, 28 Mar 2012 20:39:25 +0000 (13:39 -0700)]
drm/i915: add DPIO support

ValleyView puts some display related registers like the PLL controls and
dividers behind the DPIO bus.  Add simple indirect register access
routines to get to those registers.

v2: move new wait_for macro to intel_drv.h (Ben)
    fix DPIO_PKT double write (Ben)
    add debugfs file

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: PLL defines for VLV
Jesse Barnes [Wed, 28 Mar 2012 20:39:23 +0000 (13:39 -0700)]
drm/i915: PLL defines for VLV

Add register definitions for the new VLV PLL bits.

v2: remove unused bits & regs (Ben)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: ValleyView watermark support
Jesse Barnes [Wed, 28 Mar 2012 20:39:22 +0000 (13:39 -0700)]
drm/i915: ValleyView watermark support

Add support for ValleyView watermark handling.

v2: remove unused reg & bit definitions (Ben)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro
Jesse Barnes [Wed, 28 Mar 2012 20:39:21 +0000 (13:39 -0700)]
drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro

For use by the rest of the ValleyView code.

v2: fix desktop variant to not set is_mobile (Ben)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: split PLL update code out of i9xx_crtc_mode_set
Daniel Vetter [Wed, 28 Mar 2012 21:12:16 +0000 (23:12 +0200)]
drm/i915: split PLL update code out of i9xx_crtc_mode_set

Makes it more readable and maintainable.  ValleyView will add its own
PLL update function in a later patch.

v2: split LVDS bits out of this patch (Daniel)
v3: fix dropped DP dithering hunk (Daniel)

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
danvet:
- fixup spurious whitespace change
- reorder patches to fix bisect breakage
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: split LVDS update code out of i9xx_crtc_mode_set
Daniel Vetter [Wed, 28 Mar 2012 21:11:26 +0000 (23:11 +0200)]
drm/i915: split LVDS update code out of i9xx_crtc_mode_set

Just to make things clearer and reduce the size of this monstrosity.

v2: make sure 8xx PLL update function calls update_lvds too (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
danvet: fixed patch ordering to avoid breaking bisect.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Initialise GTT MTRR to -1
Chris Wilson [Fri, 23 Mar 2012 17:38:49 +0000 (17:38 +0000)]
drm/i915: Initialise GTT MTRR to -1

Fixes a regression from 9e984bc1 (drm/i915: Don't do MTRR setup if PAT
is enabled) where we left the MTRR as 0 and so tried to free a MTRR we
did not own during unload.

Reported-and-tested-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: allocate gmbus array as part of drm_i915_private
Daniel Kurtz [Tue, 27 Mar 2012 18:36:16 +0000 (02:36 +0800)]
drm/i915/intel_i2c: allocate gmbus array as part of drm_i915_private

This memory is always allocated, and it is always a fixed size, so just
allocate it along with the rest of the driver state.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: gmbus disabled and reserved ports are invalid
Daniel Kurtz [Tue, 27 Mar 2012 18:36:15 +0000 (02:36 +0800)]
drm/i915/intel_i2c: gmbus disabled and reserved ports are invalid

There is no GMBUS "disabled" port 0, nor "reserved" port 7.
For the other 6 ports there is a fixed 1:1 mapping between pin pairs and
gmbus ports, which means every real gmbus port has a gpio pin.

Given these realizations, clean up gmbus initialization.

Tested on Sandybridge (gen 6, PCH == CougarPoint) hardware.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: refactor using intel_gmbus_get_adapter
Daniel Kurtz [Tue, 27 Mar 2012 18:36:14 +0000 (02:36 +0800)]
drm/i915/intel_i2c: refactor using intel_gmbus_get_adapter

Instead of letting other modules directly access the ->gmbus array,
introduce intel_gmbus_get_adapter() for looking up an i2c_adapter
for a given gmbus port identifier.  This will enable later refactoring
of the gmbus port list.

Note: Before requesting an adapter for a given gmbus port number, the
driver must first check its validity using i2c_intel_gmbus_is_port_valid().
If this check fails, a call to intel_gmbus_get_adapter() will WARN_ON and
return NULL.  This is relevant for parts of the driver that read a port
from VBIOS, which might be improperly initialized and contain an invalid
port.  In these cases, the driver must fall back to using a safer default
port.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio xfers
Daniel Kurtz [Tue, 27 Mar 2012 18:36:13 +0000 (02:36 +0800)]
drm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio xfers

Instead of rolling our own custom quirk_xfer function, use the bit_algo
pre_xfer and post_xfer functions to setup and teardown bit-banged
i2c transactions.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: assign HDMI port D to pin pair 6
Daniel Kurtz [Tue, 27 Mar 2012 18:36:12 +0000 (02:36 +0800)]
drm/i915/intel_i2c: assign HDMI port D to pin pair 6

According to i915 documentation [1], "Port D" (DP/HDMI Port D) is
actually gmbus pin pair 6 (gmbus0.2:0 == 110b GPIOF), not 7 (111b).
Pin pair 7 is a reserved pair.

[1] Documentation for [DevSNB+] and [DevIBX], as found on
http://intellinuxgraphics.org:

[DevSNB+]:
http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol3_Part3.pdf
 Section 2.2.2 lists the 6 gmbus ports (gpio pin pairs):
    [ 5: HDMI/DPD, 4: HDMIB, 3: HDMI/DPC, 2: LVDS, 1: SSC, 0: VGA ]
 2.2.2.1 lists the GPIO registers to control these 6 ports.
 2.2.3.1 lists the mapping between 5 of these gmbus ports and the 3
 Pin_Pair_Select bits (of the GMBUS0 register).  This table is missing
 HDMIB (port 101).

[DevIBX]: http://intellinuxgraphics.org/IHD_OS_Vol3_Part3r2.pdf
 Section 2.2.2 lists the same 6 gmbus ports plus two 'reserved' gpio
 ports.
 2.2.2.1 lists 8 GPIO registers... however, it says the size of the
 block is 6x32, which implies that those 2 reserved GPIO registers
 (GPIO_6 & GPIO_7) don't actually exist (or are irrelevant).
 2.2.3.1 lists the mapping between the 6 named gmbus ports and the 3
 Pin_Pair_Select bits (of the GMBUS0 register).  This table has HDMIB.

Note: the "reserved" and "disabled" pairs do not actually map to a
physical pair of pins, nor GPIO regs and shouldn't be initialized or used.
Fixing this is left for a later patch.

This bug had not been noticed earlier for two reasons:
 1) Until recently, "gmbus" mode was disabled - all transfers actually
    used "bit-bang" mode on GPIO port 5 (the "HDMI/DPD CTLDATA/CLK"
    pair), at register 0x5024 (defined as GPIOF i915_reg.h).
    Since this is the correct pair of pins for HDMI1, transfers succeed.

 2) Even if gmbus mode is re-enabled, the first attempted transaction
    will fail because it tries to use the wrong ("Reserved") pin pair.
    However, the driver immediately falls back again to the bit-bang
    method, which correctly uses GPIOF, so again, transfers succeed.

However, if gmbus mode is re-enabled and the GPIO fall-back mode is
disabled, then reading an attached monitor's EDID fail.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: cleanup error messages and comments
Daniel Kurtz [Tue, 27 Mar 2012 18:36:11 +0000 (02:36 +0800)]
drm/i915/intel_i2c: cleanup error messages and comments

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/intel_i2c: refactor gmbus_xfer
Daniel Kurtz [Tue, 27 Mar 2012 18:36:10 +0000 (02:36 +0800)]
drm/i915/intel_i2c: refactor gmbus_xfer

Split out gmbus_xfer_read/write() helper functions.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: mark pwrite/pread slowpaths with unlikely
Daniel Vetter [Sun, 25 Mar 2012 17:47:43 +0000 (19:47 +0200)]
drm/i915: mark pwrite/pread slowpaths with unlikely

Beside helping the compiler untangle this maze they double-up as
documentation for which parts of the code aren't performance-critical
but just around to keep old (but already dead-slow) userspace from
breaking.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: fixup in-line clflushing on bit17 swizzled bos
Daniel Vetter [Sun, 25 Mar 2012 17:47:42 +0000 (19:47 +0200)]
drm/i915: fixup in-line clflushing on bit17 swizzled bos

The issue is that with inline clflushing the clflushing isn't properly
swizzled. Fix this by
- always clflushing entire 128 byte chunks and
- unconditionally flush before writes when swizzling a given page.
  We could be clever and check whether we pwrite a partial 128 byte
  chunk instead of a partial cacheline, but I've figured that's not
  worth it.

Now the usual approach is to fold this into the original patch series, but
I've opted against this because
- this fixes a corner case only very old userspace relies on and
- I'd like to not invalidate all the testing the pwrite rewrite has gotten.

This fixes the regression notice by tests/gem_tiled_partial_prite_pread
from i-g-t. Unfortunately it doesn't fix the issues with partial pwrites to
tiled buffers on bit17 swizzling machines. But that is also broken without
the pwrite patches, so likely a different issue (or a problem with the
testcase).

v2: Simplify the patch by dropping the overly clever partial write
logic for swizzled pages.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agomm: extend prefault helpers to fault in more than PAGE_SIZE
Daniel Vetter [Sun, 25 Mar 2012 17:47:41 +0000 (19:47 +0200)]
mm: extend prefault helpers to fault in more than PAGE_SIZE

drm/i915 wants to read/write more than one page in its fastpath
and hence needs to prefault more than PAGE_SIZE bytes.

Add new functions in filemap.h to make that possible.

Also kill a copy&pasted spurious space in both functions while at it.

v2: As suggested by Andrew Morton, add a multipage parameter to both
functions to avoid the additional branch for the pagemap.c hotpath.
My gcc 4.6 here seems to dtrt and indeed reap these branches where not
needed.

v3: Becaus I couldn't find a way around adding a uaddr += PAGE_SIZE to
the filemap.c hotpaths (that the compiler couldn't remove again),
let's go with separate new functions for the multipage use-case.

v4: Adjust comment to CodingStlye and fix spelling.

Acked-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: extract copy helpers from shmem_pread|pwrite
Daniel Vetter [Sun, 25 Mar 2012 17:47:40 +0000 (19:47 +0200)]
drm/i915: extract copy helpers from shmem_pread|pwrite

While moving around things, this two functions slowly grew out of any
sane bounds. So extract a few lines that do the copying and
clflushing. Also add a few comments to explain what's going on.

v2: Again do s/needs_clflush/needs_clflush_after/ in the write paths
as suggested by Chris Wilson.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: use uncached writes in pwrite
Daniel Vetter [Sun, 25 Mar 2012 17:47:39 +0000 (19:47 +0200)]
drm/i915: use uncached writes in pwrite

It's around 20% faster.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: fall back to shmem pwrite when the buffer is not accessible
Daniel Vetter [Sun, 25 Mar 2012 17:47:38 +0000 (19:47 +0200)]
drm/i915: fall back to shmem pwrite when the buffer is not accessible

It's too expensive to move it around just for that pwrite, especially
when we're trashing on the mappable gtt part like crazy.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: implement inline clflush for pwrite
Daniel Vetter [Sun, 25 Mar 2012 17:47:37 +0000 (19:47 +0200)]
drm/i915: implement inline clflush for pwrite

In micro-benchmarking of the usual pwrite use-pattern of alternating
pwrites with gtt domain reads from the gpu, this yields around 30%
improvement of pwrite throughput across all buffers size. The trick is
that we can avoid clflush cachelines that we will overwrite completely
anyway.

Furthermore for partial pwrites it gives a proportional speedup on top
of the 30% percent because we only clflush back the part of the buffer
we're actually writing.

v2: Simplify the clflush-before-write logic, as suggested by Chris
Wilson.

v3: Finishing touches suggested by Chris Wilson:
- add comment to needs_clflush_before and only set this if the bo is
  uncached.
- s/needs_clflush/needs_clflush_after/ in the write paths to clearly
  differentiate it from needs_clflush_before.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: don't clobber userspace memory before commiting to the pread
Daniel Vetter [Sun, 25 Mar 2012 17:47:36 +0000 (19:47 +0200)]
drm/i915: don't clobber userspace memory before commiting to the pread

The pagemap.h prefault helpers do the prefaulting by simply writing
some data into every page. Hence we should not prefault when we're not
yet commited to to actually writing data to userspace. The problem is
now that
- we can't prefault while holding dev->struct_mutex for we could
  deadlock with our own pagefault handler
- we need to grab dev->struct_mutex before copying to sync up with any
  outsanding gpu writes.

Therefore only prefault when we're dropping the lock the first time in
the pread slowpath - at that point we're committed to the write, don't
wait on the gpu anymore and hence won't return early (with e.g.
-EINTR).

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: drop gtt slowpath
Daniel Vetter [Sun, 25 Mar 2012 17:47:35 +0000 (19:47 +0200)]
drm/i915: drop gtt slowpath

With the proper prefault, it's extremely unlikely that we fall back
to the gtt slowpath.

So just kill it and use the shmem_pwrite path as fallback.

To further clean up the code, move the preparatory gem calls into the
respective pwrite functions. This way the gtt_fast->shmem fallback
is much more obvious.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: don't call shmem_read_mapping unnecessarily
Daniel Vetter [Sun, 25 Mar 2012 17:47:34 +0000 (19:47 +0200)]
drm/i915: don't call shmem_read_mapping unnecessarily

This speeds up pwrite and pread from ~120 µs ro ~100 µs for
reading/writing 1mb on my snb (if the backing storage pages
are already pinned, of course).

v2: Chris Wilson pointed out a glaring page reference bug - I've
unconditionally dropped the reference. With that fixed (and the
associated reduction of dirt in dmesg) it's now even a notch faster.

v3: Unconditionaly grab a page reference when dropping
dev->struct_mutex to simplify the code-flow.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: don't use gtt_pwrite on LLC cached objects
Daniel Vetter [Sun, 25 Mar 2012 17:47:33 +0000 (19:47 +0200)]
drm/i915: don't use gtt_pwrite on LLC cached objects

~120 µs instead fo ~210 µs to write 1mb on my snb. I like this.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: kill ranged cpu read domain support
Daniel Vetter [Sun, 25 Mar 2012 17:47:32 +0000 (19:47 +0200)]
drm/i915: kill ranged cpu read domain support

No longer needed.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: move clflushing into shmem_pread
Daniel Vetter [Sun, 25 Mar 2012 17:47:31 +0000 (19:47 +0200)]
drm/i915: move clflushing into shmem_pread

This is obviously gonna slow down pread. But for a half-way realistic
micro-benchmark, it doesn't matter: Non-broken userspace reads back
data from the gpu once before the gpu again dirties it.

So all this ranged clflush tracking is just a waste of time.

No pread performance change (neglecting the dumb benchmark of
constantly reading the same data) measured.

As an added bonus, this avoids clflush on read on coherent objects.
Which means that partial preads on snb are now roughly 4x as fast.
This will be usefull for e.g. the libva encoder - when I finally get
around to fix that up.

v2: Properly sync with the gpu on LLC machines.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm: add helper to clflush a virtual address range
Daniel Vetter [Sun, 25 Mar 2012 17:47:30 +0000 (19:47 +0200)]
drm: add helper to clflush a virtual address range

Useful when the page is already mapped to copy date in/out.

For -stable because the next patch (fixing phys obj pwrite) needs this
little helper function.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: merge shmem_pread slow&fast-path
Daniel Vetter [Sun, 25 Mar 2012 17:47:29 +0000 (19:47 +0200)]
drm/i915: merge shmem_pread slow&fast-path

With the previous rewrite, they've become essential identical.

v2: Simplify the page_do_bit17_swizzling logic as suggested by Chris
Wilson.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: merge shmem_pwrite slow&fast-path
Daniel Vetter [Sun, 25 Mar 2012 17:47:28 +0000 (19:47 +0200)]
drm/i915: merge shmem_pwrite slow&fast-path

With the previous rewrite, they've become essential identical.

v2: Simplify the page_do_bit17_swizzling logic as suggested by Chris
Wilson.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Avoid using mappable space for relocation processing through the CPU
Chris Wilson [Mon, 26 Mar 2012 08:10:27 +0000 (10:10 +0200)]
drm/i915: Avoid using mappable space for relocation processing through the CPU

We try to avoid writing the relocations through the uncached GTT, if the
buffer is currently in the CPU write domain and so will be flushed out to
main memory afterwards anyway. Also on SandyBridge we can safely write
to the pages in cacheable memory, so long as the buffer is LLC mapped.
In either of these cases, we therefore do not need to force the
reallocation of the buffer into the mappable region of the GTT, reducing
the aperture pressure.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: clear the entire gtt when using gem
Daniel Vetter [Mon, 26 Mar 2012 07:45:42 +0000 (09:45 +0200)]
drm/i915: clear the entire gtt when using gem

We've lost our guard page somewhere in the gtt rewrite, this patch
here will restore it.

Exercised by i-g-t/tests/gem_cs_prefetch.

v2: Substract the guard page from the range we're supposed to manage
with gem. Suggested by Chris Wilson to increase the odds of old ums +
gem userspace not blowing up. To compensate for the loss of a page,
don't substract the guard page in the modeset init code any longer.

Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44748
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: the intel gtt is _not_ an agp bridge!
Daniel Vetter [Mon, 26 Mar 2012 07:45:41 +0000 (09:45 +0200)]
drm/i915: the intel gtt is _not_ an agp bridge!

So don't call it like that.

Also rip out a confusing comment and instead explain what's really
going on.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: s/i915_gem_do_init/i915_gem_init_global_gtt
Daniel Vetter [Mon, 26 Mar 2012 07:45:40 +0000 (09:45 +0200)]
drm/i915: s/i915_gem_do_init/i915_gem_init_global_gtt

... because this is what it actually doesn now that we have the global
gtt vs. ppgtt split.

Also move it to the other global gtt functions in i915_gem_gtt.c

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: reinstate GM45 TV detection fix
Daniel Vetter [Sun, 25 Mar 2012 20:56:14 +0000 (22:56 +0200)]
drm/i915: reinstate GM45 TV detection fix

This reverts commmit d4b74bf07873da2e94219a7b67a334fc1c3ce649 which
reverted the origin fix fb8b5a39b6310379d7b54c0c7113703a8eaf4a57.

We have at least 3 different bug reports that this fixes things and no
indication what is exactly wrong with this. So try again.

To make matters slightly more fun, the commit itself was cc: stable
whereas the revert has not been.

According to Peter Clifton he discussed this with Zhao Yakui and this
seems to be in contradiction of the GM45 PRM, but rumours have it that
this is how the BIOS does it ... let's see.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Tested-by: Peter Clifton <Peter.Clifton@clifton-electronics.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Eric Anholt <eric@anholt.net>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=16236
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25913
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=14792
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Batch copy_from_user for relocation processing
Chris Wilson [Sat, 24 Mar 2012 20:12:53 +0000 (20:12 +0000)]
drm/i915: Batch copy_from_user for relocation processing

Originally the code tried to allocate a large enough array to perform
the copy using vmalloc, performance wasn't great and throughput was
improved by processing each individual relocation entry separately.
This too is not as efficient as one would desire. A compromise would be
to allocate a single page, or to allocate a few entries on the stack,
and process the copy in batches. The latter gives simpler code and more
consistent performance due to a lack of heuristic.

x11perf -copywinwin10: n450/pnv i3-330m i5-2520m (cpu)
               before:    249000  785000  1280000 (80%)
                 page:   264000  896000  1280000 (65%)
             on-stack:   264000  902000  1280000 (67%)

v2: Use 512-bytes of stack for batching rather than allocate a page.
v3: Tidy the code slightly with more descriptive variable names

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: enable gmbus on gen2
Daniel Vetter [Fri, 2 Mar 2012 18:38:30 +0000 (19:38 +0100)]
drm/i915: enable gmbus on gen2

With the recent set of gmbus fixes, this seems to work on my i855gm.

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add an explict mmio base for gpio/gmbus io
Daniel Vetter [Fri, 23 Mar 2012 22:43:36 +0000 (23:43 +0100)]
drm/i915: add an explict mmio base for gpio/gmbus io

Again, Valleyview modes these around, so make the mmio base more
explicit to consolidate the base address computations to one
HAS_PCH_SPLIT check.

v2: Fix up the PCH_SPLIT braino ... it actually works that way round.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/sdov: switch IS_SDVOB to a flag
Daniel Vetter [Fri, 23 Mar 2012 22:43:35 +0000 (23:43 +0100)]
drm/i915/sdov: switch IS_SDVOB to a flag

With valleyview we'll have these at yet another address, so keeping
track of this with an ever-growing list of registers will get ugly.

This way intel_sdvo.c is fully independent of the base address of the
output ports display register blocks.

While at it, do 2 closely related cleanups:
- use SDVO_NAME some more
- change the sdvo_reg variables to uint32_t like other registers.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: re-order GT IIR bit definitions
Jesse Barnes [Thu, 22 Mar 2012 21:38:44 +0000 (14:38 -0700)]
drm/i915: re-order GT IIR bit definitions

They were all over the place, order them by position and add a few.

v2: add gen indications to the new bits (Ben)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: move NEEDS_FORCE_WAKE to i915_drv.c
Jesse Barnes [Thu, 22 Mar 2012 21:38:43 +0000 (14:38 -0700)]
drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

It's only used by the main read/write functions, so we can keep it with
them.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Release the mmap offset when purging a buffer
Chris Wilson [Fri, 24 Feb 2012 21:13:38 +0000 (21:13 +0000)]
drm/i915: Release the mmap offset when purging a buffer

If we discard a buffer due to memory pressure, also release its alloted
mmap address space. As it may be sometime before userspace wakes up
and notices that it has buffers to purge from its cache, we may waste
valuable address space on unusable objects for a period of time.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47738
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Add lvds_channel module option
Takashi Iwai [Tue, 20 Mar 2012 12:07:06 +0000 (13:07 +0100)]
drm/i915: Add lvds_channel module option

Add a new module optoin lvds_channel to specify the LVDS channel mode
explicitly instead of probing the LVDS register value set by BIOS.
This will be helpful when VBT is broken or incompatible with the
current code.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42842
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Check VBIOS value for determining LVDS dual channel mode, too
Takashi Iwai [Tue, 20 Mar 2012 12:07:05 +0000 (13:07 +0100)]
drm/i915: Check VBIOS value for determining LVDS dual channel mode, too

Currently i915 driver checks [PCH_]LVDS register bits to decide
whether to set up the dual-link or the single-link mode.  This relies
implicitly on that BIOS initializes the register properly at boot.
However, BIOS doesn't initialize it always.  When the machine is
booted with the closed lid, BIOS skips the LVDS reg initialization.
This ends up in blank output on a machine with a dual-link LVDS when
you open the lid after the boot.

This patch adds a workaround for that problem by checking the initial
LVDS register value in VBT.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37742
Tested-By: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: [dinq] shut up six instances of -Warray-bounds
Ben Widawsky [Wed, 15 Feb 2012 13:42:42 +0000 (14:42 +0100)]
drm/i915: [dinq] shut up six instances of -Warray-bounds

Introduced in commits c1cd90ed and d27b1e0e

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: s/fix/shut up in the commit msg and add a comment to the
BUG_ON.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: [dinq] shut up two instances -Wunitialized
Ben Widawsky [Wed, 15 Feb 2012 13:42:43 +0000 (14:42 +0100)]
drm/i915: [dinq] shut up two instances -Wunitialized

Introduced in commit 8461d226 and 8c59967c

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: s/fix/shut up/ in the commit msg.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add HAS_ALIASING_PPGTT parameter for userspace
Daniel Vetter [Wed, 15 Feb 2012 22:50:25 +0000 (23:50 +0100)]
drm/i915: add HAS_ALIASING_PPGTT parameter for userspace

On Sanybridge a few MI read/write commands only work when ppgtt is
enabled.  Userspace therefore needs to be able to check whether ppgtt
is enabled. For added hilarity, you need to reset the "use global GTT"
bit on snb when ppgtt is enabled, otherwise it won't work.  Despite
what bspec says about automatically using ppgtt ...

Luckily PIPE_CONTROL (the only write cmd current userspace uses) is
not affected by all this, as tested by tests/gem_pipe_control_store_loop.

Reviewed-and-tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: enable lazy global-gtt binding
Daniel Vetter [Wed, 15 Feb 2012 22:50:24 +0000 (23:50 +0100)]
drm/i915: enable lazy global-gtt binding

Now that everything is in place, only bind to the global gtt
when actually required. Patch split-up suggested by Chris Wilson.

Reviewed-and-tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: implement SNB workaround for lazy global gtt
Daniel Vetter [Wed, 15 Feb 2012 22:50:23 +0000 (23:50 +0100)]
drm/i915: implement SNB workaround for lazy global gtt

PIPE_CONTROL on snb needs global gtt mappings in place to workaround a
hw gotcha. No other commands need such a workaround. Luckily we can
detect a PIPE_CONTROL commands easily because they have a write_domain
= I915_GEM_DOMAIN_INSTRUCTION (and nothing else has that).

v2: Binding the target of such a reloc into the global gtt actually
works instead of binding the source, which is rather pointless ...

v3: Kill a superflous has_global_gtt_mapping assignement noticed by
Chris Wilson.

Reviewed-and-tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: bind objects to the global gtt only when needed
Daniel Vetter [Wed, 15 Feb 2012 22:50:22 +0000 (23:50 +0100)]
drm/i915: bind objects to the global gtt only when needed

And track the existence of such a binding similar to the aliasing
ppgtt case. Speeds up binding/unbinding in the common case where we
only need a ppgtt binding (which is accessed in a cpu coherent fashion
by the gpu) and no gloabl gtt binding (which needs uc writes for the
ptes).

This patch just puts the required tracking in place.

v2: Check that global gtt mappings exist in the error_state capture
code (with Chris Wilson's llc reloc patches batchbuffers are no longer
relocated as mappable in all situations, so this matters). Suggested
by Chris Wilson.

v3: Adapted to Chris' latest llc-reloc patches.

v4: Fix a bug in the i915 error state capture code noticed by Chris
Wilson.

Reviewed-and-tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: split out dma mapping from global gtt bind/unbind functions
Daniel Vetter [Wed, 15 Feb 2012 22:50:21 +0000 (23:50 +0100)]
drm/i915: split out dma mapping from global gtt bind/unbind functions

Note that there's a functional change buried in this patch wrt the ilk
dmar workaround: We now only idle the gpu while tearing down the dmar
mappings, not while clearing the gtt. Keeping the current semantics
would have made for some really ugly code and afaik the issue is only
with the dmar unmapping that needs a fully idle gpu.

Reviewed-and-tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agoi915: Add and use pr_fmt and pr_<level>
Joe Perches [Sun, 18 Mar 2012 20:00:11 +0000 (13:00 -0700)]
i915: Add and use pr_fmt and pr_<level>

Use a more current logging style.  Ensure that appropriate
logging messages are prefixed with "i915: ".

Convert printks to pr_<level>.  Align arguments.

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: panel: invert brightness acer aspire 5734z
Carsten Emde [Thu, 15 Mar 2012 14:56:27 +0000 (15:56 +0100)]
drm/i915: panel: invert brightness acer aspire 5734z

Mark the Acer Aspire 5734Z that this machines requires the module to
invert the panel backlight brightness value after reading from and prior
to writing to the PCI configuration space.

Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: panel: invert brightness via quirk
Carsten Emde [Thu, 15 Mar 2012 14:56:26 +0000 (15:56 +0100)]
drm/i915: panel: invert brightness via quirk

A machine may need to invert the panel backlight brightness value. This
patch adds the infrastructure for a quirk to do so.

Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: panel: invert brightness via parameter
Carsten Emde [Thu, 15 Mar 2012 14:56:25 +0000 (15:56 +0100)]
drm/i915: panel: invert brightness via parameter

Following the documentation of the Legacy Backlight Brightness (LBB)
Register in the configuration space of some Intel PCI graphics adapters,
setting the LBB register with the value 0x0 causes the backlight to be
turned off, and 0xFF causes the backlight to be set to 100% intensity
(http://download.intel.com/embedded/processors/Whitepaper/324567.pdf).
The Acer Aspire 5734Z, however, turns the backlight off at 0xFF and sets
it to maximum intensity at 0. In consequence, the screen of this systems
becomes dark at an early boot stage which makes it unusable. The same
inversion applies to the BLC_PWM_CTL I915 register. This problem was
introduced in kernel version 2.6.38 when the PCI device of this system
was first supported by the i915 KMS module.

This patch adds a parameter to the i915 module to enable inversion of
the brightness variable (i915.invert_brightness).

Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Add wait_for in init_ring_common
Sean Paul [Fri, 16 Mar 2012 16:43:22 +0000 (12:43 -0400)]
drm/i915: Add wait_for in init_ring_common

I have seen a number of "blt ring initialization failed" messages
where the ctl or start registers are not the correct value. Upon further
inspection, if the code just waited a little bit, it would read the
correct value. Adding the wait_for to these reads should eliminate the
issue.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Don't do MTRR setup if PAT is enabled
Adam Jackson [Wed, 14 Mar 2012 15:22:11 +0000 (11:22 -0400)]
drm/i915: Don't do MTRR setup if PAT is enabled

Some newer BIOSes are shipping with all MTRRs already populated.  These
BIOSes are all on machines with sufficiently new CPUs that the
referenced errata doesn't apply anyway, so just don't try to claim the
MTRR.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41648
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Pull MTRR setup to its own function
Adam Jackson [Wed, 14 Mar 2012 15:22:10 +0000 (11:22 -0400)]
drm/i915: Pull MTRR setup to its own function

No functional change here, just clarifying code flow.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Retry reading the PCH FDI receiver ISR
Sean Paul [Fri, 2 Mar 2012 17:53:39 +0000 (12:53 -0500)]
drm/i915: Retry reading the PCH FDI receiver ISR

According to the PRM (Vol3P2), the PCH FDI receiver ISR read for bit lock
should be retried at least once. This patch retries the read 5 times
with a small delay in between reads. I've had reports of display corruption
on resume with "FDI train 1 fail!", so I'm hoping that adding this retry
will mitigate the issue.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: remove ACPI related DRM_ERRORs
Jesse Barnes [Thu, 12 Jan 2012 17:03:14 +0000 (09:03 -0800)]
drm/i915: remove ACPI related DRM_ERRORs

They're not really errors (well actually I don't know; I don't
understand _DSM and _MUX well enough to say, but I do know they spam
people's logs and seem to be harmless).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: The _DSM error got remove in another patch already]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44250
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agoi915: Add option to bypass vbt table.
Mathias Fröhlich [Thu, 1 Mar 2012 05:44:35 +0000 (06:44 +0100)]
i915: Add option to bypass vbt table.

This change enables the use of displays where the vbt table just
contains inappropriate values, but either the vesa defaults or
the video=... modes do something sensible with the attached display.

The problem happens with an embedded board that contains vbt bios
tables that do not match the attached display.  Using this change and
the appropriate kernel boot command line they are able to use an
otherwise completely unusable secondary display on that embedded
board.

Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Only clear the GPU domains upon a successful finish
Chris Wilson [Wed, 14 Dec 2011 12:57:23 +0000 (13:57 +0100)]
drm/i915: Only clear the GPU domains upon a successful finish

By clearing the GPU read domains before waiting upon the buffer, we run
the risk of the wait being interrupted and the domains prematurely
cleared. The next time we attempt to wait upon the buffer (after
userspace handles the signal), we believe that the buffer is idle and so
skip the wait.

There are a number of bugs across all generations which show signs of an
overly haste reuse of active buffers.

Such as:

  https://bugs.freedesktop.org/show_bug.cgi?id=29046
  https://bugs.freedesktop.org/show_bug.cgi?id=35863
  https://bugs.freedesktop.org/show_bug.cgi?id=38952
  https://bugs.freedesktop.org/show_bug.cgi?id=40282
  https://bugs.freedesktop.org/show_bug.cgi?id=41098
  https://bugs.freedesktop.org/show_bug.cgi?id=41102
  https://bugs.freedesktop.org/show_bug.cgi?id=41284
  https://bugs.freedesktop.org/show_bug.cgi?id=42141

A couple of those pre-date i915_gem_object_finish_gpu(), so may be
unrelated (such as a wild write from a userspace command buffer), but
this does look like a convincing cause for most of those bugs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: reenable gmbus on gen3+ again
Daniel Vetter [Tue, 14 Feb 2012 21:37:25 +0000 (22:37 +0100)]
drm/i915: reenable gmbus on gen3+ again

With the rework to merge the bit-banging fallback into the gmbus
i2c adapter we've gotten rid of the deadlock possibility that
originally lead to the disabling of this code.

This reverts the revert

commit 826c7e4147f902737b281e8a5a7d7aa33fd63316
Author: Jean Delvare <khali@linux-fr.org>
Date:   Sat Jun 4 19:34:56 2011 +0000

    Revert "drm/i915: Enable GMBUS for post-gen2 chipsets"

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=35572
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: i2c: unconditionally set up gpio fallback
Daniel Vetter [Tue, 14 Feb 2012 17:58:49 +0000 (18:58 +0100)]
drm/i915: i2c: unconditionally set up gpio fallback

This way we can simplify the setup and teardown a bit.

Because we don't actually allocate anything anymore for the force_bit
case, we can now convert that into a boolean.

Also and the functionality supported by the bit-banging together with
what gmbus can do, so that this doesn't randomly change any more.

v2: Chris Wilson noticed that I've mixed up && and & ...

v3: Clarify an if block as suggested by Eugeni Dodonov.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: merge gmbus and gpio i2c adpater into one
Daniel Vetter [Mon, 27 Feb 2012 23:43:09 +0000 (00:43 +0100)]
drm/i915: merge gmbus and gpio i2c adpater into one

... and directly call the newly exported i2c bit-banging functions.

The code is still pretty convoluted because we only set up the gpio
i2c stuff when actually falling back, resulting in more complexity
than necessary. This will be fixed up in the next patch.

v2: Use exported i2c_bit_algo vtable instead of exported functions.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: merge struct intel_gpio into struct intel_gmbus
Daniel Vetter [Tue, 14 Feb 2012 21:37:22 +0000 (22:37 +0100)]
drm/i915: merge struct intel_gpio into struct intel_gmbus

When we set up the gpio fallback, we always have a 1:1 relationship
with an intel_gmbus. Exploit that to store all gpio related data in
there, too. This is a preparation step to merge the tw i2c adapters
controlling the same bus into one.

Just mundane code-munging in this patch.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agoi2c: export bit-banging algo functions
Daniel Vetter [Mon, 27 Feb 2012 23:39:39 +0000 (00:39 +0100)]
i2c: export bit-banging algo functions

i915 has a hw i2c controller (gmbus) but for a bunch of stupid reasons
we need to be able to fall back to the bit-banging algo on gpio pins.

The current code sets up a 2nd i2c controller for the same i2c bus using
the bit-banging algo. This has a bunch of issues, the major one being
that userspace can directly access this fallback i2c adaptor behind
the drivers back.

But we need to frob a few registers before and after using fallback
gpio bit-banging, so this horribly fails.

The new plan is to only set up one i2c adaptor and transparently fall
back to bit-banging by directly calling the xfer function of the bit-
banging algo in the i2c core.

To make that possible, export the 2 i2c algo functions.

v2: As suggested by Jean Delvare, simply export the i2c_bit_algo
vtable instead of the individual functions.

Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/nouveau: do a better job at hiding the NIH i2c bit-banging algo
Daniel Vetter [Mon, 27 Feb 2012 23:42:19 +0000 (00:42 +0100)]
drm/nouveau: do a better job at hiding the NIH i2c bit-banging algo

I'd like to export the corresponding functions from the i2c core
so that I can use them in fallback bit-banging in i915.ko

v2: Adapt to new i2c export patch.

Cc: nouveau@lists.freedesktop.org
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add dev_priv to intel_gmbus
Daniel Vetter [Tue, 14 Feb 2012 21:37:19 +0000 (22:37 +0100)]
drm/i915: add dev_priv to intel_gmbus

This way we can free up the bus->adaptor.algo_data pointer and make it
available for use with the bitbanging fallback algo.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Fix single msg gmbus_xfers writes
Benson Leung [Thu, 9 Feb 2012 20:03:17 +0000 (12:03 -0800)]
drm/i915: Fix single msg gmbus_xfers writes

gmbus_xfer with a single message (particularly a single message write) would
set Bus Cycle Select to 100b, the Gen Stop cycle, instead of 101b,
No Index, Stop cycle. This would not start single message i2c transactions.

Also, gmbus_xfer done: will disable the interface without checking if
it is idle. In the case of writes, there will be no wait on status or delay
to ensure the write starts and completes before the interface is turned off.

Fixed the former issue by using the same cycle selection as used in the
I2C_M_RD for the write case.
GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0)
Fixed the latter by waiting on GMBUS_ACTIVE to deassert before disable.

Note from the grumpy d-i-n maintainer: The first hunk that changes the
gmbus read path is just cosmetics to align the code with the write
path.  I.e. the commit message above is slightly lying because the
first issue is _only_ with writes (and not simply "particularly").

Signed-off-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: error_buffer->ring should be signed
Daniel Vetter [Thu, 16 Feb 2012 10:03:29 +0000 (11:03 +0100)]
drm/i915: error_buffer->ring should be signed

gcc seems to get uber-anal recently about these things.

Clarification from Dan Carpenter:

"Sorry, I should have said that it's not a gcc warning, it's a smatch
thing.  But also it's not uber-anal.  It's the exact level of anality
which is required to make the == -1 test work.  You can compare
unsigned int and longs to -1 and it works but for smaller types it
doesn't."

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Silence the error message from i915_wait_request()
Chris Wilson [Wed, 22 Feb 2012 20:39:12 +0000 (20:39 +0000)]
drm/i915: Silence the error message from i915_wait_request()

This error message has since been superseded by the hangcheck, and does
not add any salient information beyond that already printed by hangcheck
discovering the GPU hang that lead to i915_wait_request() bombing out in
the first place.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: use the new hdmi_force_audio enum more
Daniel Vetter [Thu, 23 Feb 2012 16:14:47 +0000 (17:14 +0100)]
drm/i915: use the new hdmi_force_audio enum more

While fixing up a merge conflict with drm-next I've noticed that we
use the same audio drm connector property also for dp and sdvo
outputs.

So put the new enum to some good use and convert these paths, too. The
HDMI_AUDIO_ prefix is a bit a misnomer. But at least for sdvo it makes
sense (and you can also connect a hdmi monitor with a dp->hdmi cable),
so I've decided to stick with it.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: No need to search again after retiring requests
Chris Wilson [Fri, 24 Feb 2012 00:27:22 +0000 (00:27 +0000)]
drm/i915: No need to search again after retiring requests

Retiring requests does not typically free up space in the aperture,
so the additional search is pointless.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Only bump refcnt on objects scheduled for eviction
Chris Wilson [Fri, 24 Feb 2012 00:27:21 +0000 (00:27 +0000)]
drm/i915: Only bump refcnt on objects scheduled for eviction

Incrementing the reference count on all objects walked when searching
for space in the aperture is a non-neglible amount of overhead. In fact,
we only need to hold on to a reference for objects that we will evict,
so we can therefore delay the referencing until we find a suitable hole
and only add those objects that fall inside.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915/bios: Downgrade the "signature missing" DRM_ERROR to debug
Chris Wilson [Fri, 24 Feb 2012 16:53:28 +0000 (16:53 +0000)]
drm/i915/bios: Downgrade the "signature missing" DRM_ERROR to debug

As we warn the user later that we cannot find or load the VBIOS,
explaining why is an exercise in debugging. Shouting *ERROR* upsets
people and produces bug reports.

Reported-by: Michael Rieder <mr@student.ethz.ch>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43751
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Ignore LVDS on hp t5745 and hp st5747 thin client
Marc Gariepy [Thu, 9 Feb 2012 14:35:21 +0000 (09:35 -0500)]
drm/i915: Ignore LVDS on hp t5745 and hp st5747 thin client

Add a no_lvds quirk for the HP t5745 and HP st5747 thin clients

dmidecode for those thin clients are attached in thoses bugs:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/911916
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/911920

Signed-off-by: Marc Gariepy <mgariepy@ubuntu.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Fixes distorted external screen image on HP 2730p
Philipp Grete [Tue, 21 Feb 2012 11:40:20 +0000 (12:40 +0100)]
drm/i915: Fixes distorted external screen image on HP 2730p

Fixes LP: #796030 by removing forced pipe A on HP 2730p.  Quirk has
previously been introduced to fix a sleep mode problem that does not
exist any more.

v2: Added Tested-by and Bugzilla Link

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/796030
Tested-by: Ronny Standtke <ronny.standtke@gmx.net>
Signed-off-by: Philipp Grete <mail@pgrete.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agoMerge remote-tracking branch 'airlied/drm-next' into for-airlied
Daniel Vetter [Thu, 23 Feb 2012 13:54:20 +0000 (14:54 +0100)]
Merge remote-tracking branch 'airlied/drm-next' into for-airlied

Manually resolve the conflict between the new enum drm property
helpers in drm-next and the new "force-dvi" option that the "audio" output
property gained in drm-intel-next.

While resolving this conflict, switch the new drm_prop_enum_list to
use the newly introduced enum defines instead of magic values.

Conflicts:
drivers/gpu/drm/i915/intel_modes.c

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm: add some caps for userspace to discover more info for dumb KMS driver (v2)
Dave Airlie [Thu, 29 Sep 2011 15:20:42 +0000 (16:20 +0100)]
drm: add some caps for userspace to discover more info for dumb KMS driver (v2)

For the simple KMS driver case we need some more info about what the preferred
depth and if a shadow framebuffer is preferred.

I've only added this for intel/radeon which support the dumb ioctls so far.

If you need something really fancy you should be writing a real X.org driver.

v2: drop cursor information, just return an error from the cursor ioctls
and we can make userspace fallback to sw cursor in that case, cursor
info was getting too messy, best to start smaller.

Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: move pci bus master enable into driver.
Dave Airlie [Mon, 19 Dec 2011 11:15:29 +0000 (11:15 +0000)]
drm: move pci bus master enable into driver.

The current enabling of bus mastering in the drm midlayer allows a large
race condition under kexec. When a kexec'ed kernel re-enables bus mastering
for the GPU, previously setup dma blocks may cause writes to random pieces
of memory. On radeon the writeback mechanism can cause these sorts of issues.

This patch doesn't fix the problem, but it moves the bus master enable under
the individual drivers control so they can move enabling it until later in
their load cycle and close the race.

Fix for radeon kms driver will be in a follow-up patch.

Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoRevert "drivers/gpu/drm/i915/intel_overlay.c needs seq_file.h"
Danny Kukawka [Wed, 15 Feb 2012 17:53:55 +0000 (18:53 +0100)]
Revert "drivers/gpu/drm/i915/intel_overlay.c needs seq_file.h"

This reverts commit e167976ee7f5fe4b80f7e8f55e087f6c67cf9562,
Since this was already fixed in commit
3bd3c9329973a93fa3ef5e9840f2fd6fa2889e3f some days before this
commit cause seq_file.h to be included twice.

Signed-off-by: Danny Kukawka <danny.kukawka@bisect.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/radeon/evergreen: make texdw[] array larger
Dan Carpenter [Tue, 14 Feb 2012 07:38:11 +0000 (10:38 +0300)]
drm/radeon/evergreen: make texdw[] array larger

We store stuff in texdw[7] so this array needs to have 8 elements.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/i915/lvds: Always use the presence pin for LVDS on PCH
Chris Wilson [Thu, 9 Feb 2012 09:35:53 +0000 (09:35 +0000)]
drm/i915/lvds: Always use the presence pin for LVDS on PCH

With the introduction of the PCH, we gained an LVDS presence pin but we
continued to use the existing logic that asserted that LVDS was only
supported on certain mobile chipsets. However, there are desktop
IronLake systems with LVDS attached which we fail to detect. So for PCH,
trust the LVDS presence pin and quirk all the lying manufacturers.

Tested-by: Daniel Woff <wolff.daniel@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43171
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Record the position of the request upon error
Chris Wilson [Wed, 15 Feb 2012 11:25:38 +0000 (11:25 +0000)]
drm/i915: Record the position of the request upon error

So that we can tally the request against the command sequence in the
ringbuffer, or merely jump to the interesting locations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Record the in-flight requests at the time of a hang
Chris Wilson [Wed, 15 Feb 2012 11:25:37 +0000 (11:25 +0000)]
drm/i915: Record the in-flight requests at the time of a hang

Being able to tally the list of outstanding requests with the sequence
of commands in the ringbuffer is often useful evidence with respect to
driver corruption.

Note that since this is the umpteenth per-ring data structure to be added
to the error state, I've coallesced the nearby loops (the ringbuffer and
batchbuffer) into a single structure along with the list of requests.  A
later task would be to refactor the ring register state into the same
structure.

v2: Fix pretty printing of requests so that they are parsed correctly by
intel_error_decode and use the 0x%08x format for seqno for consistency

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Record the tail at each request and use it to estimate the head
Chris Wilson [Wed, 15 Feb 2012 11:25:36 +0000 (11:25 +0000)]
drm/i915: Record the tail at each request and use it to estimate the head

By recording the location of every request in the ringbuffer, we know
that in order to retire the request the GPU must have finished reading
it and so the GPU head is now beyond the tail of the request. We can
therefore provide a conservative estimate of where the GPU is reading
from in order to avoid having to read back the ring buffer registers
when polling for space upon starting a new write into the ringbuffer.

A secondary effect is that this allows us to convert
intel_ring_buffer_wait() to use i915_wait_request() and so consolidate
upon the single function to handle the complicated task of waiting upon
the GPU. A necessary precaution is that we need to make that wait
uninterruptible to match the existing conditions as all the callers of
intel_ring_begin() have not been audited to handle ERESTARTSYS
correctly.

By using a conservative estimate for the head, and always processing all
outstanding requests first, we prevent a race condition between using
the estimate and direct reads of I915_RING_HEAD which could result in
the value of the head going backwards, and the tail overflowing once
again. We are also careful to mark any request that we skip over in
order to free space in ring as consumed which provides a
self-consistency check.

Given sufficient abuse, such as a set of unthrottled GPU bound
cairo-traces, avoiding the use of I915_RING_HEAD gives a 10-20% boost on
Sandy Bridge (i5-2520m):
  firefox-paintball  18927ms -> 15646ms: 1.21x speedup
  firefox-fishtank   12563ms -> 11278ms: 1.11x speedup
which is a mild consolation for the performance those traces achieved from
exploiting the buggy autoreported head.

v2: Add a few more comments and make request->tail a conservative
estimate as suggested by Daniel Vetter.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: resolve conflicts with retirement defering and the lack of
the autoreport head removal (that will go in through -fixes).]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add missing SDVO bits for interlaced modes on ILK
Paulo Zanoni [Tue, 14 Feb 2012 19:07:09 +0000 (17:07 -0200)]
drm/i915: add missing SDVO bits for interlaced modes on ILK

This was pointed by Jesse Barnes. The code now seems to follow the
specification but I don't have an SDVO device to really test this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agoMerge tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm...
Dave Airlie [Tue, 14 Feb 2012 14:16:00 +0000 (14:16 +0000)]
Merge tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next

* tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits)
  drm/i915: Handle unmappable buffers during error state capture
  drm/i915: rewrite shmem_pread_slow to use copy_to_user
  drm/i915: rewrite shmem_pwrite_slow to use copy_from_user
  drm/i915: fall through pwrite_gtt_slow to the shmem slow path
  drm/i915: add debugfs file for swizzling information
  drm/i915: fix swizzle detection for gen3
  drm/i915: Remove the upper limit on the bo size for mapping into the CPU domain
  drm/i915: add per-ring fault reg to error_state
  drm/i915: reject GTT domain in relocations
  drm/i915: remove the i915_batchbuffer_info debugfs file
  drm/i915: capture error_state also for stuck rings
  drm/i915: refactor debugfs create functions
  drm/i915: refactor debugfs open function
  drm/i915: don't trash the gtt when running out of fences
  drm/i915: Separate fence pin counting from normal bind pin counting
  drm/i915/ringbuffer: kill snb blt workaround
  drm/i915: collect more per ring error state
  drm/i915: refactor ring error state capture to use arrays
  drm/i915: switch ring->id to be a real id
  drm/i915: set AUD_CONFIG N_value_index for DisplayPort
  ...

12 years agodrm/i915: Fix race condition in accessing GMBUS
Yufeng Shen [Mon, 13 Feb 2012 22:36:54 +0000 (17:36 -0500)]
drm/i915: Fix race condition in accessing GMBUS

GMBUS has several ports and each has it's own corresponding
I2C adpater. When multiple I2C adapters call gmbus_xfer() at
the same time there is a race condition in using the underlying
GMBUS controller. Fixing this by adding a mutex lock when calling
gmbus_xfer().

v2: Moved gmbus_mutex below intel_gmbus and added comments.
Rebased to drm-intel-next-queued.

Signed-off-by: Yufeng Shen <miletus@chromium.org>
[danvet: Shortened the gmbus_mutex comment a bit and add the patch
revision comment to the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add a "force-dvi" HDMI audio mode
Wu Fengguang [Tue, 14 Feb 2012 03:45:36 +0000 (11:45 +0800)]
drm/i915: add a "force-dvi" HDMI audio mode

When HDMI-DVI converter is used, it's not only necessary to turn off
audio, but also to disable HDMI_MODE_SELECT and video infoframe. Since
the DVI mode is mainly tied to audio functionality from end user POV,
add a new "force-dvi" audio mode:

xrandr --output HDMI1 --set audio force-dvi

Note that most users won't need to set this and happily rely on the EDID
based DVI auto detection.

Reported-by: Andrea Arcangeli <aarcange@redhat.com>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Don't lock panel registers when downclocking
Sean Paul [Mon, 13 Feb 2012 18:14:51 +0000 (13:14 -0500)]
drm/i915: Don't lock panel registers when downclocking

This patch replaces the locking from the downclock routines with an assert
to ensure the registers are indeed unlocked. Without this patch, pre-SNB
devices would lock the registers when downclocking which would cause a
WARNING on suspend/resume with downclocking enabled.

Note: To hit this bug, you need to have lvds downclocking enabled.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/radeon: add support for evergreen/ni tiling informations v11
Jerome Glisse [Fri, 16 Dec 2011 22:03:42 +0000 (17:03 -0500)]
drm/radeon: add support for evergreen/ni tiling informations v11

evergreen and northern island gpu needs more informations for 2D tiling
than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace
to provide those.

The v8 cs checking change to track color view on r6xx/r7xx doesn't
affect old userspace as old userspace always emited 0 for this register.

v2 fix r6xx/r7xx 2D tiling computation
v3 fix r6xx/r7xx height align for untiled surface & add support for
   tile split on evergreen and newer
v4 improve tiling debugging output
v5 fix tile split code for evergreen and newer
v6 set proper tile split for crtc register
v7 fix tile split limit value
v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs
   checking, update safe reg for r600, evergreen and cayman.
   Evergreen checking need some work around for stencil alignment
   issues
v9 fix tile split value range, fix compressed texture handling and
   mipmap calculation, allow evergreen check to be silencious in
   front of current broken userspace (depth/stencil alignment issue)
v10 fix eg 3d texture and compressed texture, fix r600 depth array,
    fix r600 color view computation, add support for evergreen stencil
    split
v11 more verbose debugging in some case

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon/kms: add support for streamout v7
Marek Olšák [Fri, 27 Jan 2012 17:17:59 +0000 (12:17 -0500)]
drm/radeon/kms: add support for streamout v7

v2: agd5f: add strmout CS checking, copy_dw register checking

v3: agd5f: don't use cs_check_reg() for copy_dw checking as it
will incorrectly patch the command stream for certain regs.

v4: agd5f: add warning if safe reg check fails for copy_dw

v5: agd5f: add stricter checking for 6xx/7xx

v6: agd5f: add range checking for copy_dw on eg+,
add sx_surface_sync to safe reg list for 7xx.

v7: agd5f: add stricter checking for eg+

Signed-off-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: Fix kcalloc parameters swapped
Axel Lin [Fri, 10 Feb 2012 12:04:52 +0000 (20:04 +0800)]
drm: Fix kcalloc parameters swapped

The first parameter should be "number of elements" and the second parameter
should be "element size".

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoMerge branch 'drm-vmware-next' into drm-core-next
Dave Airlie [Mon, 13 Feb 2012 12:04:11 +0000 (12:04 +0000)]
Merge branch 'drm-vmware-next' into drm-core-next

* drm-vmware-next:
  drm/vmwgfx: Bump driver minor
  vmwgfx: Move function declaration to correct header
  drm/vmwgfx: Treat out-of-range initial width and height as host errors
  vmwgfx: Pick up the initial size from the width and height regs
  vmwgfx: Add page flip support
  vmwgfx: Pipe fence out of screen object dirty functions
  vmwgfx: Make it possible to get fence from execbuf
  vmwgfx: Clean up pending event references to struct drm_file objects on close
  vmwgfx: Rework fence event action

12 years agodrm/vmwgfx: Bump driver minor
Thomas Hellstrom [Thu, 9 Feb 2012 15:56:49 +0000 (16:56 +0100)]
drm/vmwgfx: Bump driver minor

Bump driver minor to signal availability of the page-flip ioctl.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agovmwgfx: Move function declaration to correct header
Thomas Hellstrom [Thu, 9 Feb 2012 15:56:48 +0000 (16:56 +0100)]
vmwgfx: Move function declaration to correct header

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/vmwgfx: Treat out-of-range initial width and height as host errors
Thomas Hellstrom [Thu, 9 Feb 2012 15:56:47 +0000 (16:56 +0100)]
drm/vmwgfx: Treat out-of-range initial width and height as host errors

And assign the initial width and height to the minimum in that case.
Strange values (-1) from these registers have been reported by users.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>