GitHub/LineageOS/android_kernel_motorola_exynos9610.git
10 years agodrm/radeon: rework page flip handling v4
Christian König [Tue, 3 Jun 2014 22:13:21 +0000 (18:13 -0400)]
drm/radeon: rework page flip handling v4

Instead of trying to flip inside the vblank period when
the buffer is idle, offload blocking for idle to a kernel
thread and program the flip directly into the hardware.

v2: add error handling, fix EBUSY handling
v3: add proper exclusive_lock handling
v4: update crtc->primary->fb when the flip actually happens

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoRevert "drm/radeon: rework page flip handling v3"
Dave Airlie [Wed, 4 Jun 2014 01:59:31 +0000 (11:59 +1000)]
Revert "drm/radeon: rework page flip handling v3"

This reverts commit 1aab5514ca9604e0263f658a067da0189c86a35b.

Apply the fixed up version instead.

10 years agoMerge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm...
Dave Airlie [Tue, 3 Jun 2014 00:34:29 +0000 (10:34 +1000)]
Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next

Highlights:
- GPUVM opimtizations
- HDMI audio cleanups
- Deep color HDMI support
- more bug fixes, cleanups

* 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits)
  drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.
  drm/edid: Parse and handle HDMI deep color modes.
  drm/radeon: Limit hdmi deep color bit depth to 12 bpc.
  drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)
  drm/radeon: fix pll setup for hdmi deep color (v7)
  drm/radeon: use hw cts/n values for deep color
  drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi
  drm/radeon/atom: fix dithering on certain panels
  drm/radeon: optimize CIK VM handling v2
  drm/radeon: optimize SI VM handling
  drm/radeon: add define for flags used in R600+ GTT
  drm/radeon: rework page flip handling v3
  drm/radeon: separate vblank and pflip crtc handling
  drm/radeon: split page flip and pending callback
  drm/radeon: remove drm_vblank_get|put from pflip handling
  drm/radeon: remove (pre|post)_page_flip callbacks
  drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices
  drm/radeon: fix typo in radeon_connector_is_dp12_capable()
  radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770
  vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled
  ...

10 years agodrm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.
Mario Kleiner [Fri, 23 May 2014 19:40:55 +0000 (21:40 +0200)]
drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.

The Sony PVM-2541A OLED high precision color display supports
both 10 bpc and 12 bpc hdmi deep color input, but its edid
does not signal any deep color support.

Add a quirk to force it being treated as a 12 bpc panel.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/edid: Parse and handle HDMI deep color modes.
Mario Kleiner [Thu, 27 Mar 2014 18:59:39 +0000 (19:59 +0100)]
drm/edid: Parse and handle HDMI deep color modes.

Check the HDMI cea block for deep color mode bits. If available,
assign the highest supported bpc for a hdmi display, corresponding
to the given deep color modes.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: Limit hdmi deep color bit depth to 12 bpc.
Mario Kleiner [Mon, 5 May 2014 21:03:18 +0000 (23:03 +0200)]
drm/radeon: Limit hdmi deep color bit depth to 12 bpc.

DCE-4/5/6 can't support more than 12 bpc deep color over hdmi,
so clamp to 12 bpc when a hdmi deep color capable display is
connected. This even makes sense on DCE-8+, which could do up
to 16 bpc, as driving with more than 12 bpc would only waste
video bandwidth as long as we don't support framebuffers with
more than 12 bpc depth.

On pre-DCE4 we clamp hdmi bit depth to 8 bpc, as those asics
don't support hdmi deep color.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)
Alex Deucher [Wed, 28 May 2014 23:14:36 +0000 (19:14 -0400)]
drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)

Program HDMI_CONTROL to send general control packets
for hdmi deep color mode signalling at every video
frame if bpc > 8.

This is only supported on evergreen / DCE-4 and later.

v2: rebase

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: fix pll setup for hdmi deep color (v7)
Alex Deucher [Tue, 22 Apr 2014 02:09:19 +0000 (22:09 -0400)]
drm/radeon: fix pll setup for hdmi deep color (v7)

Need to adjust the pll up for deep color modes.
Additionally, the atom bpc defines were wrong in certain
cases.

v2: set the adjusted clock to the pll clock for hdmi deep
color.  This fixes display and audio issues with deep color
as reported by Andy Furniss <adf.lists@gmail.com>

v3: set crtc_clock as well

v4: setcrtcinfo on the adjusted mode

v5: just use the adjusted clock for setting the pll

v6: only use the adjusted clock for hdmi

v7: only DCE5 and DCE6 and bpc > 8

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: use hw cts/n values for deep color
Alex Deucher [Wed, 28 May 2014 23:02:31 +0000 (19:02 -0400)]
drm/radeon: use hw cts/n values for deep color

I'm not really sure how these should be calculated
for deep color.  The hw generated values seem to work.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi
Alex Deucher [Tue, 22 Apr 2014 01:45:09 +0000 (21:45 -0400)]
drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi

May fix display issues with non-HDMI displays.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
10 years agodrm/radeon/atom: fix dithering on certain panels
Alex Deucher [Tue, 27 May 2014 20:40:51 +0000 (16:40 -0400)]
drm/radeon/atom: fix dithering on certain panels

We need to specify the encoder mode as LVDS for eDP
when using the Crtc_Source atom table in order to properly
set up the FMT hardware.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=73911

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
10 years agodrm/radeon: optimize CIK VM handling v2
Christian König [Tue, 27 May 2014 18:10:28 +0000 (20:10 +0200)]
drm/radeon: optimize CIK VM handling v2

Fill VM page tables from the GART page table if applicable.

v2: fix copy&paste error

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: optimize SI VM handling
Christian König [Tue, 27 May 2014 14:47:38 +0000 (16:47 +0200)]
drm/radeon: optimize SI VM handling

Fill VM page tables from the GART page table if applicable.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: add define for flags used in R600+ GTT
Christian König [Tue, 27 May 2014 14:47:37 +0000 (16:47 +0200)]
drm/radeon: add define for flags used in R600+ GTT

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: rework page flip handling v3
Christian König [Tue, 27 May 2014 14:49:22 +0000 (16:49 +0200)]
drm/radeon: rework page flip handling v3

Instead of trying to flip inside the vblank period when
the buffer is idle, offload blocking for idle to a kernel
thread and program the flip directly into the hardware.

v2: add error handling, fix EBUSY handling
v3: add proper exclusive_lock handling

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: separate vblank and pflip crtc handling
Christian König [Tue, 27 May 2014 14:49:21 +0000 (16:49 +0200)]
drm/radeon: separate vblank and pflip crtc handling

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: split page flip and pending callback
Christian König [Tue, 27 May 2014 14:49:20 +0000 (16:49 +0200)]
drm/radeon: split page flip and pending callback

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: remove drm_vblank_get|put from pflip handling
Christian König [Tue, 27 May 2014 14:49:19 +0000 (16:49 +0200)]
drm/radeon: remove drm_vblank_get|put from pflip handling

We activate the VBLANK irq manually anyway, so this is unnecessary.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: remove (pre|post)_page_flip callbacks
Christian König [Tue, 27 May 2014 14:49:18 +0000 (16:49 +0200)]
drm/radeon: remove (pre|post)_page_flip callbacks

They are doing the same on all generations anyway.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices
Alex Deucher [Tue, 27 May 2014 17:48:05 +0000 (13:48 -0400)]
drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices

Only DCE5+ asics support DP 1.2.

Noticed by ArtForz on IRC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
10 years agodrm/radeon: fix typo in radeon_connector_is_dp12_capable()
Alex Deucher [Tue, 27 May 2014 17:11:36 +0000 (13:11 -0400)]
drm/radeon: fix typo in radeon_connector_is_dp12_capable()

We were checking the ext clock rather than the display clock.

Noticed by ArtForz on IRC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
10 years agoradeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770
Émeric MASCHINO [Fri, 23 May 2014 15:02:24 +0000 (11:02 -0400)]
radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770

Removes useless quirk a7f465f73363fce409870f62173d518b1bc02ae6 introduced with
fdo #7770 as a failed attempt to minimize stability issues with hp zx1 chipset/
ATI FireGL X1 graphics adapter configuration
(see http://marc.info/?l=linux-ia64&m=140077543819871&w=2 for details/reason)

Signed-off-by: Émeric MASCHINO <emeric.maschino@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agovgaswitcheroo: switch the mux to the igp on power down when runpm is enabled
Alex Deucher [Mon, 19 May 2014 18:04:43 +0000 (14:04 -0400)]
vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled

Avoids blank screens on muxed systems when runpm is active.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=75917

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
10 years agodrm/radeon: use NULL instead of zero in clearstate headers
Michele CURTI [Mon, 19 May 2014 15:23:55 +0000 (11:23 -0400)]
drm/radeon: use NULL instead of zero in clearstate headers

Signed-off-by: Michele Curti <michele.curti@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: use NULL instead of zero in object functions
Michele CURTI [Mon, 19 May 2014 15:18:52 +0000 (11:18 -0400)]
drm/radeon: use NULL instead of zero in object functions

Signed-off-by: Michele Curti <michele.curti@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon/hdmi: DCE2: simplify audio workaround
Rafał Miłecki [Fri, 16 May 2014 09:10:31 +0000 (11:10 +0200)]
drm/radeon/hdmi: DCE2: simplify audio workaround

Thanks to advanced RE of fglrx we finally know what exactly needs to be
handled of AFMT change.

This has been tested for possible regressions on:
1) DCE2 HD2400 (RV610)
2) DCE3 HD3470 (RV620)

For a reference and details see:
https://bugzilla.kernel.org/show_bug.cgi?id=76231

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon/hdmi: DCE2: update setmode
Rafał Miłecki [Fri, 16 May 2014 09:10:30 +0000 (11:10 +0200)]
drm/radeon/hdmi: DCE2: update setmode

Recent RE efforts revealed ops performed by fglrx during HDMI setup.
This mostly adds masks to r/w ops plus few single missing bits.

This has been tested for possible regressions on:
1) DCE2 HD2400 (RV610)
2) DCE3 HD3470 (RV620)

For a reference and details see:
https://bugzilla.kernel.org/show_bug.cgi?id=76231

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon/hdmi: DCE3: clean ACR control
Rafał Miłecki [Fri, 16 May 2014 09:10:29 +0000 (11:10 +0200)]
drm/radeon/hdmi: DCE3: clean ACR control

What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

This has been tested for possible regressions on DCE3 HD3470 (RV620).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon/hdmi: use separated file for DCE 3.1/3.2 code
Rafał Miłecki [Fri, 16 May 2014 09:36:24 +0000 (11:36 +0200)]
drm/radeon/hdmi: use separated file for DCE 3.1/3.2 code

DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and
DCE 3. The order of setting registers and sets of registers are
different.
It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they
have few differences as well.
For now separate DCE 2 and DCE 3 path, so we can work on it without a
risk of breaking DCE 3.1+.

This has been tested for possible regressions on DCE32 HD4550 (RV710).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2
Christian König [Sat, 10 May 2014 10:17:56 +0000 (12:17 +0200)]
drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2

This patch makes it possible to decide how many address
bits are spend on the page directory vs the page tables.

v2: remove unintended change

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: add large PTE support for NI, SI and CIK v5
Christian König [Sat, 10 May 2014 10:17:55 +0000 (12:17 +0200)]
drm/radeon: add large PTE support for NI, SI and CIK v5

This patch implements support for VRAM page table entry compression.
PTE construction is enhanced to identify physically contiguous page
ranges and mark them in the PTE fragment field. L1/L2 TLB support is
enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly
improving TLB utilization for VRAM allocations.

Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn.
Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS
on default settings at 1920x1200 resolution with vsync disabled.

See main comment in radeon_vm.c for a technical description.

v2 (chk): rebased and simplified.
v3 (chk): add missing hw setup
v4 (chk): rebased on current drm-fixes-3.15
v5 (chk): fix comments and commit text

Signed-off-by: Jay Cornwall <jay@jcornwall.me>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: add a i2c bus mutex
Alex Deucher [Thu, 8 May 2014 14:58:04 +0000 (10:58 -0400)]
drm/radeon: add a i2c bus mutex

The i2c and aux buses use the same pads so add
a mutex to protect access to the pads.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
10 years agoMerge tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel...
Dave Airlie [Mon, 2 Jun 2014 09:55:04 +0000 (19:55 +1000)]
Merge tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel into drm-next

- prep refactoring for execlists (Oscar Mateo)
- corner-case fixes for runtime pm (Imre)
- tons of vblank improvements from Ville
- prep work for atomic plane/sprite updates (Ville)
- more chv code, now almost complete (tons of different people)
- refactoring and improvements for drm_irq.c merged through drm-intel-next
- g4x/ilk reset improvements (Ville)
- removal of encoder->mode_set
- moved audio state tracking into pipe_config
- shuffled fb pinning out of the platform crtc modeset callbacks into core code
- userptr support (Chris)
- OOM handling improvements from Chris, with now have a neat oom notifier which
  jumps additional debug information.
- topdown allocation of ppgtt PDEs (Ben)
- fixes and small improvements all over

* tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits)
  drm/i915: Kill private_default_ctx off
  drm/i915: s/i915_hw_context/intel_context
  drm/i915: Split the ringbuffers from the rings (3/3)
  drm/i915: Split the ringbuffers from the rings (2/3)
  drm/i915: Split the ringbuffers from the rings (1/3)
  drm/i915: s/intel_ring_buffer/intel_engine_cs
  drm/i915: disable GT power saving early during system suspend
  drm/i915: fix possible RPM ref leaking during RPS disabling
  drm/i915: remove user GTT mappings early during runtime suspend
  drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk
  drm/i915: Fix gen2 and hsw+ scanline counter
  drm/i915: Draw a picture about video timings
  drm/i915: Improve gen3/4 frame counter
  drm/i915: Add a small adjustment to the pixel counter on interlaced modes
  drm/i915: Hold CRTC lock whilst freezing the planes
  drm/i915: Only discard backing storage on releasing the last ref
  drm/i915: Wait for pending page flips before enabling/disabling the primary plane
  drm/i915: grab the audio power domain when enabling audio on HSW+
  drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off
  drm/i915: move bsd dispatch index somewhere better
  ...

10 years agodrm: add DP MST encoder type
Dave Airlie [Fri, 2 May 2014 01:09:54 +0000 (11:09 +1000)]
drm: add DP MST encoder type

This adds an encoder type for DP MST encoders.

Reviewed-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm: store encoder name in encoder struct
Jani Nikula [Wed, 14 May 2014 13:58:20 +0000 (16:58 +0300)]
drm: store encoder name in encoder struct

This makes drm_get_encoder_name() thread safe.

Reference: http://lkml.kernel.org/r/645ee6e22cad47d38a2b35c21c8d5fe3@DC1-MBX-01\
.ptsecurity.ru
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm: store connector name in connector struct (v2)
Jani Nikula [Wed, 14 May 2014 13:58:19 +0000 (16:58 +0300)]
drm: store connector name in connector struct (v2)

This makes drm_get_connector_name() thread safe.

[airlied: fix to build.]

Reference: http://lkml.kernel.org/r/645ee6e22cad47d38a2b35c21c8d5fe3@DC1-MBX-01.ptsecurity.ru
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/dp: Add missing kernel-doc
Thierry Reding [Wed, 23 Apr 2014 13:49:04 +0000 (15:49 +0200)]
drm/dp: Add missing kernel-doc

Commit 9dc4056026e0 (drm/dp: let drivers specify the name of the I2C-
over-AUX adapter) introduced a new field but didn't add the proper
kernel-doc for it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/armada: use shmem helpers if possible
David Herrmann [Sun, 25 May 2014 12:34:09 +0000 (14:34 +0200)]
drm/armada: use shmem helpers if possible

shmem_read_mapping_page() uses mapping_gfp_mask(mapping) as default gfp
mask. No reason to use shmem_read_mapping_page_gfp() directly if we want
the default behavior.

Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/gem: replace misleading comment
David Herrmann [Sun, 25 May 2014 12:34:08 +0000 (14:34 +0200)]
drm/gem: replace misleading comment

shmem supports page-relocations during swapin since quite some time. It
was implemented in:

    commit bde05d1ccd512696b09db9dd2e5f33ad19152605
    Author: Hugh Dickins <hughd@google.com>
    Date:   Tue May 29 15:06:38 2012 -0700

        shmem: replace page if mapping excludes its zone

The gem-comment about wrongly placed DMA32 pages is no longer valid.
Replace it with a proper comment but keep the BUG_ON() to verify correct
shmem behavior.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/edid: Use kmemdup instead of kmalloc + memcpy
Benoit Taine [Mon, 26 May 2014 15:21:22 +0000 (17:21 +0200)]
drm/edid: Use kmemdup instead of kmalloc + memcpy

This issue was reported by coccicheck using the semantic patch
at scripts/coccinelle/api/memdup.cocci

Signed-off-by: Benoit Taine <benoit.taine@lip6.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/shmobile: Add run-time dependencies
Jean Delvare [Mon, 26 May 2014 12:52:13 +0000 (14:52 +0200)]
drm/shmobile: Add run-time dependencies

The shmobile DRM driver is only useful on SuperH and shmobile unless
build testing. I am dropping the SuperH dependencies though because
the driver doesn't even build there, so in practice it is an arm-only
driver for now.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/rcar-du: Add run-time dependencies
Jean Delvare [Mon, 26 May 2014 11:01:35 +0000 (13:01 +0200)]
drm/rcar-du: Add run-time dependencies

The Renesas R-Car Display Unit driver is only useful on shmobile
unless build testing. The LVDS output is useful on an even more
reduced hardware set.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoMAINTAINERS: Shovel drivers/gpu/vga/* to Dave
Daniel Vetter [Mon, 26 May 2014 21:44:42 +0000 (23:44 +0200)]
MAINTAINERS: Shovel drivers/gpu/vga/* to Dave

DRM is pretty much the main user of this stuff (if we ignore the sysfs
interface used by X, i.e. by the same gang of people writing the drm
drivers). So shovel it into Dave's responsibility to avoid patches
getting lost on lkml.

With this get_maintainers will rout vgaarb and switcheroo patches
correctly.

Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: linux-kernel@vger.kernel.org
References: https://lkml.org/lkml/2014/5/25/94
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoDocumentation: drm: describing drm properties exposed by various drivers
Sagar Kamble [Tue, 11 Mar 2014 14:25:29 +0000 (19:55 +0530)]
Documentation: drm: describing drm properties exposed by various drivers

Started documenting drm properties for drm drivers. This patch provides
information about properties in drm, i915, psb and cdv/gma-500. Information
about other properties can be added on top of these.

v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau,
omap, qxl, radeon, rcar-du

v3: Removed "Property Object" column since it is implementation related. Property
type column refined.[Ville's review comments]

v4: Removed whitespace warnings and minor nits. [Randy's review comments]

v5: Restructured output for ENUM properties

v6: Review comments on formatting the table. [Laurent's review comments]

v7: Minor restructuring. [Laurent's review comments]

Cc: Rob Landley <rob@landley.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Sagar Kamble <sagar.a.kamble@intel.com>
Cc: "Purushothaman, Vijay A" <vijay.a.purushothaman@intel.com>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/ttm: fix kerneldoc of ttm_bo_create
Alexandre Courbot [Fri, 23 May 2014 03:58:06 +0000 (12:58 +0900)]
drm/ttm: fix kerneldoc of ttm_bo_create

The kerneldoc header of ttm_bo_create() was referring to another
(nonexisting) function and had a few obsolete or incorrect arguments.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm: Add 800x600 (SVGA) screen resolution to the built-in EDIDs
Daniel Thompson [Fri, 23 May 2014 15:01:43 +0000 (16:01 +0100)]
drm: Add 800x600 (SVGA) screen resolution to the built-in EDIDs

The 800x600 (SVGA) screen resolution was lacking in the set of
built-in selectable EDID screen resolutions that can be used to
repair misbehaving monitor firmware.

This patch adds the related data set and expands the documentation.
Note that the SVGA bit occupies a different byte to all the existing
users of the established timing bits forcing a rework of the
ESTABLISHED_TIMINGS_BITS macro.

Tested new EDID on an aged (and misbehaving) industrial LCD panel;
existing EDIDs still pass edid-decode's checksum checks.

Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: David Airlie <airlied@linux.ie>
Cc: Carsten Emde <C.Emde@osadl.org>
Cc: linux-doc@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoDocumentation: fix typos in drm docbook
Masanari Iida [Thu, 15 May 2014 20:54:06 +0000 (13:54 -0700)]
Documentation: fix typos in drm docbook

Fix spelling typo in DocBook/drm.tmpl

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm: fix typo
Rob Clark [Sat, 24 May 2014 18:30:10 +0000 (14:30 -0400)]
drm: fix typo

Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/dp_helper: add defines for DP 1.2 and MST support. (v2)
Dave Airlie [Fri, 2 May 2014 01:05:21 +0000 (11:05 +1000)]
drm/dp_helper: add defines for DP 1.2 and MST support. (v2)

This just adds the defines from the DP 1.2 spec, which we
will use later.

fix some DP MST to 1.2 MST

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
10 years agodrm/i915: Kill private_default_ctx off
Oscar Mateo [Thu, 22 May 2014 13:13:38 +0000 (14:13 +0100)]
drm/i915: Kill private_default_ctx off

It's barely alive now anyway, so give it the "coup de grâce".

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: s/i915_hw_context/intel_context
Oscar Mateo [Thu, 22 May 2014 13:13:37 +0000 (14:13 +0100)]
drm/i915: s/i915_hw_context/intel_context

Up until now, contexts had one (and only one) backing object that was
used by the hardware to save/restore render ring contexts (via the
MI_SET_CONTEXT command). Other rings did not have or need this, so
our i915_hw_context struct had a 1:1 relationship with a a real HW
context.

With Logical Ring Contexts and Execlists, this is not possible anymore:
all rings need a backing object, and it cannot be reused. To prepare
for that, rename our contexts to the more generic term intel_context.

No functional changes.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Split the ringbuffers from the rings (3/3)
Oscar Mateo [Thu, 22 May 2014 13:13:36 +0000 (14:13 +0100)]
drm/i915: Split the ringbuffers from the rings (3/3)

Manual cleanup after the previous Coccinelle script.

Yes, I could write another Coccinelle script to do this but I
don't want labor-replacing robots making an honest programmer's
work obsolete (also, I'm lazy).

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Split the ringbuffers from the rings (2/3)
Oscar Mateo [Thu, 22 May 2014 13:13:35 +0000 (14:13 +0100)]
drm/i915: Split the ringbuffers from the rings (2/3)

This refactoring has been performed using the following Coccinelle
semantic script:

    @@
    struct intel_engine_cs r;
    @@
    (
    - (r).obj
    + r.buffer->obj
    |
    - (r).virtual_start
    + r.buffer->virtual_start
    |
    - (r).head
    + r.buffer->head
    |
    - (r).tail
    + r.buffer->tail
    |
    - (r).space
    + r.buffer->space
    |
    - (r).size
    + r.buffer->size
    |
    - (r).effective_size
    + r.buffer->effective_size
    |
    - (r).last_retired_head
    + r.buffer->last_retired_head
    )

    @@
    struct intel_engine_cs *r;
    @@
    (
    - (r)->obj
    + r->buffer->obj
    |
    - (r)->virtual_start
    + r->buffer->virtual_start
    |
    - (r)->head
    + r->buffer->head
    |
    - (r)->tail
    + r->buffer->tail
    |
    - (r)->space
    + r->buffer->space
    |
    - (r)->size
    + r->buffer->size
    |
    - (r)->effective_size
    + r->buffer->effective_size
    |
    - (r)->last_retired_head
    + r->buffer->last_retired_head
    )

    @@
    expression E;
    @@
    (
    - LP_RING(E)->obj
    + LP_RING(E)->buffer->obj
    |
    - LP_RING(E)->virtual_start
    + LP_RING(E)->buffer->virtual_start
    |
    - LP_RING(E)->head
    + LP_RING(E)->buffer->head
    |
    - LP_RING(E)->tail
    + LP_RING(E)->buffer->tail
    |
    - LP_RING(E)->space
    + LP_RING(E)->buffer->space
    |
    - LP_RING(E)->size
    + LP_RING(E)->buffer->size
    |
    - LP_RING(E)->effective_size
    + LP_RING(E)->buffer->effective_size
    |
    - LP_RING(E)->last_retired_head
    + LP_RING(E)->buffer->last_retired_head
    )

Note: On top of this this patch also removes the now unused ringbuffer
fields in intel_engine_cs.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
[danvet: Add note about fixup patch included here.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Split the ringbuffers from the rings (1/3)
Oscar Mateo [Thu, 22 May 2014 13:13:34 +0000 (14:13 +0100)]
drm/i915: Split the ringbuffers from the rings (1/3)

As advanced by the previous patch, the ringbuffers and the engine
command streamers belong in different structs. This is so because,
while they used to be tightly coupled together, the new Logical
Ring Contexts (LRC for short) have a ringbuffer each.

In legacy code, we will use the buffer* pointer inside each ring
to get to the pertaining ringbuffer (the actual switch will be
done in the next patch). In the new Execlists code, this pointer
will be NULL and we will use instead the one inside the context
instead.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: s/intel_ring_buffer/intel_engine_cs
Oscar Mateo [Thu, 22 May 2014 13:13:33 +0000 (14:13 +0100)]
drm/i915: s/intel_ring_buffer/intel_engine_cs

In the upcoming patches we plan to break the correlation between
engine command streamers (a.k.a. rings) and ringbuffers, so it
makes sense to refactor the code and make the change obvious.

No functional changes.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: disable GT power saving early during system suspend
Imre Deak [Mon, 12 May 2014 15:35:05 +0000 (18:35 +0300)]
drm/i915: disable GT power saving early during system suspend

Atm, we disable GT power saving during the end of the suspend sequence
in i915_save_state(). Doing the disabling at that point seems arbitrary.
One reason to disable it early though is to have a quiescent HW state
before we do anything else (for example save registers). So move the
disabling earlier, which also takes care canceling of the deferred RPS
enabling work done by intel_disable_gt_powersave().

Note that after the move we'll call intel_disable_gt_powersave() only
in case modeset is enabled, but that's anyway the only case where we
have it enabled in the first place.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: fix possible RPM ref leaking during RPS disabling
Imre Deak [Mon, 12 May 2014 15:35:04 +0000 (18:35 +0300)]
drm/i915: fix possible RPM ref leaking during RPS disabling

In

commit c6df39b5ea6342323a42edfbeeca0a28c643d7ae
Author: Imre Deak <imre.deak@intel.com>
Date:   Mon Apr 14 20:24:29 2014 +0300

    drm/i915: get a runtime PM ref for the deferred GT powersave enabling

I added an RPM get-ref when enabling RPS from a deferred work, but forgot
to add the corresponding put-ref when canceling the work. This may leave
RPM disabled.

Note that the race is real since we run the rps enabling with a
delayed work item after resume, so leaves enough time (in contrived
examples) to fit a quick autoresum in.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Testecase: igt/pm_rpm/system-suspend
[danvet: Mention testcase and add note.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: remove user GTT mappings early during runtime suspend
Imre Deak [Wed, 7 May 2014 16:57:49 +0000 (19:57 +0300)]
drm/i915: remove user GTT mappings early during runtime suspend

Currently user space can access GEM buffers mapped to GTT through
existing mappings concurrently while the platform specific suspend
handlers are running. Since these handlers may change the HW state in a
way that would break such accesses, remove the mappings before calling
the handlers. Spotted by Ville.

Also Chris pointed out that the lists that i915_gem_release_all_mmaps()
walks through need dev->struct_mutex, so take this lock. There is a
potential deadlock against a concurrent RPM resume, resolve this by
aborting and rescheduling the suspend (Daniel).

v2:
- take struct_mutex around i915_gem_release_all_mmaps() (Chris, Daniel)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk
Ville Syrjälä [Mon, 19 May 2014 16:23:27 +0000 (19:23 +0300)]
drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk

Apparently we need to disable VCP unit clock gating around media reset
on g4x.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix gen2 and hsw+ scanline counter
Ville Syrjälä [Thu, 15 May 2014 17:23:23 +0000 (20:23 +0300)]
drm/i915: Fix gen2 and hsw+ scanline counter

On gen2 the scanline counter behaves a bit differently from the
later generations. Instead of adding one to the raw scanline
counter value, we must subtract one.

On HSW/BDW the scanline counter requires a +2 adjustment on HDMI
outputs. DP outputs on the on the other require the typical +1
adjustment.

As the fixup we must apply to the hardware scanline counter
depends on several factors, compute the desired offset at modeset
time and tuck it away for when it's needed.

v2: Clarify HSW+ situation

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: "Akash Goel <akash.goels@gmail.com>"
Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78997
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Draw a picture about video timings
Ville Syrjälä [Thu, 15 May 2014 17:20:36 +0000 (20:20 +0300)]
drm/i915: Draw a picture about video timings

The docs are a bit lacking when it comes to describing when certain
timing related events occur in the hardware. Draw a picture which
tries to capture the most important ones.

v2: Clarify a few details (Imre)
v3: Add HSW+ HDMI scanline counter numbers

Acked-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Akash Goel <akash.goels@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>"
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Improve gen3/4 frame counter
Ville Syrjälä [Tue, 29 Apr 2014 10:35:50 +0000 (13:35 +0300)]
drm/i915: Improve gen3/4 frame counter

Currently the logic to fix up the frame counter on gen3/4 assumes that
start of vblank occurs at vblank_start*htotal pixels, when in fact
it occurs htotal-hsync_start pixels earlier. Apply the appropriate
adjustment to make the frame counter more accurate.

Also fix the vblank start position for interlaced display modes.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: "Akash Goel <akash.goels@gmail.com>"
Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>"
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add a small adjustment to the pixel counter on interlaced modes
Ville Syrjälä [Tue, 29 Apr 2014 10:35:49 +0000 (13:35 +0300)]
drm/i915: Add a small adjustment to the pixel counter on interlaced modes

In interlaced modes, the pixel counter counts all pixels,
so one field will have htotal more pixels. In order to avoid
the reported position from jumping backwards when the pixel
counter is beyond the length of the shorter field, just
clamp the position the length of the shorter field. This
matches how the scanline counter based position works since
the scanline counter doesn't count the two half lines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: "Akash Goel <akash.goels@gmail.com>"
Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>"
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Hold CRTC lock whilst freezing the planes
Chris Wilson [Thu, 22 May 2014 08:44:40 +0000 (09:44 +0100)]
drm/i915: Hold CRTC lock whilst freezing the planes

Daniel keeps on ramping up the warning level of the DRM and our display
core to make it complain whenever the locking rules are not followed.
This caught

commit 24576d23976746cb52e7700c4cadbf4bc1bc3472
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Tue Mar 26 09:25:45 2013 -0700

    drm/i915: enable VT switchless resume v3

introducing an unlocked access to the CRTC whilst disabling it for
suspend.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78114
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Only discard backing storage on releasing the last ref
Chris Wilson [Thu, 22 May 2014 08:16:52 +0000 (09:16 +0100)]
drm/i915: Only discard backing storage on releasing the last ref

Before purging our pages (as opposed to copying back the contents from
the GPU), make sure that there is not an exposed CPU mmapping through
which the user can inspect the results.

Regression from

commit 5537252b6b6d71fb1a8ed7395a8e5babf91953fd
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Mar 25 13:23:06 2014 +0000

    drm/i915: Invalidate our pages under memory pressure

Testcase: igt/gem_mmap/new-object
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79005
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Guo Jinxian <jinxianx.guo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Wait for pending page flips before enabling/disabling the primary plane
Ville Syrjälä [Wed, 21 May 2014 11:04:46 +0000 (14:04 +0300)]
drm/i915: Wait for pending page flips before enabling/disabling the primary plane

We have to write to the primary plane base address registrer when we
enable/disable the primary plane in response to sprite coverage. Those
writes will cause the flip counter to increment which could interfere
with the detection of CS flip completion. We could end up completing
CS flips before the CS has even executed the commands from the ring.

To avoid such issues, wait for CS flips to finish before we toggle the
primary plane on/off.

v2: Rebased due to atomic sprite update changes

Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: grab the audio power domain when enabling audio on HSW+
Paulo Zanoni [Wed, 21 May 2014 20:29:31 +0000 (17:29 -0300)]
drm/i915: grab the audio power domain when enabling audio on HSW+

With the current code, we unconditionally touch
HSW_AUD_PIN_ELD_CP_VLD, which means we can touch it when the power
well is off, and that will trigger an "Unclaimed register" message.

Just adding the intel_crtc->config.has_audio should already avoid the
unclaimed register messsages, but since we actually need the power
well to make the Audio code work, it makes sense to also grab the
audio power domain reference, and release it when it's not needed
anymore.

I used IGT's pm_rpm to reproduce this bug, but it can probably be
reproduced on other tests that do modesets. I'm using a machine with
eDP+HDMI connected.

Regression introduced by:

commit acfa75b02e72bad7c93564ac379712e29c001432
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Apr 24 23:54:51 2014 +0200
    drm/i915: Simplify audio handling on DDI ports

Credits to Daniel for suggesting this implementation.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off
Paulo Zanoni [Wed, 21 May 2014 19:23:20 +0000 (16:23 -0300)]
drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off

Because this will trigger "Unclaimed register" messages. All I need to
reproduce this problem is to boot my HSW machine with eDP+HDMI
connected.

Regression introduced by:

commit 9ed109a7b445e3f073d8ea72f888ec80c0532465
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Apr 24 23:54:52 2014 +0200
    drm/i915: Track has_audio in the pipe config

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: move bsd dispatch index somewhere better
Daniel Vetter [Wed, 21 May 2014 15:37:52 +0000 (17:37 +0200)]
drm/i915: move bsd dispatch index somewhere better

Adding stuff at the bottom is really no how this should be done, since
that's the place for ums/dri dungeons.

This was added in

commit a8ebba75b358f9c912cbcba0c14a2072e7280b2f
Author: Zhao Yakui <yakui.zhao@intel.com>
Date:   Thu Apr 17 10:37:40 2014 +0800

    drm/i915: Use the coarse ping-pong mechanism based on drm fd to dispatch the BSD command on BDW GT3

Also add a note to prevent this from happening again - people really
should be less lazy and take more time to look for a good home of
their new driver-global state.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Shuffle fifo underrun disable/enable points for gmch platforms
Ville Syrjälä [Fri, 16 May 2014 16:40:25 +0000 (19:40 +0300)]
drm/i915: Shuffle fifo underrun disable/enable points for gmch platforms

Gen2 reports FIFO underruns whenever no planes are enabled on the pipe.
So in order to avoid false positives we must enable the FIFO underrun
reporting only when at least one plane is enabled on the pipe. For
now just move the underrun reporting enable/disable points to the
other side of the plane enable/disable point. That doesn't cover cases
when we turn off all the planes for the pipe but leave the pipe running
on purpose, but it's better than the current situation.

On gen4+ we can actually move the underrun reporting enable/disable to
the opposite ends of the crtc enable/disable hooks. I suppose in theory
we could leave the underrun reporting enabled all the time, except on
VLV where PIPESTAT stops working when the display power well is down.
If we ever get around to unifying the PIPESTAT irq handling for all
gmch platforms, we should still follow the VLV route for other platforms.
It would also micro-optimize the irq handler a bit since we could then
skip the PIPESTAT reads for all disabled pipes.

Gen3 is still a mystery, but for now I'm going to assume it behaves
like gen4+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Simplify the uncleared FIFO underrun detection
Ville Syrjälä [Fri, 16 May 2014 16:40:24 +0000 (19:40 +0300)]
drm/i915: Simplify the uncleared FIFO underrun detection

Checking whether the error interrupt was enabled or not isn't really
necessary when we check for uncleared FIFO underruns. If it was enabled
we'll race with the interrupt handler a bit, but that seems OK as we
still claim the interrupt.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Check for FIFO underruns at the end of modeset on gmch
Ville Syrjälä [Fri, 16 May 2014 16:40:22 +0000 (19:40 +0300)]
drm/i915: Check for FIFO underruns at the end of modeset on gmch

FIFO underruns don't generate interrupts on gmch platforms, so
if we want to know whether a modeset triggered FIFO underruns we
need to explicitly check for them.

As a modeset on one pipe could cause underruns on other pipes,
check for underruns on all pipes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
[danvet: Fix up merge error, kudos to Ville for noticing it.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Check for FIFO underuns when disabling reporting on gmch platforms
Ville Syrjälä [Fri, 16 May 2014 16:40:21 +0000 (19:40 +0300)]
drm/i915: Check for FIFO underuns when disabling reporting on gmch platforms

FIFO underruns don't generate an interrupt on gmch platforms, so we
should check whether there were any that we failed to notice when
we're disabling FIFO underrun reporting.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/irq: Coding style fix
Daniel Vetter [Wed, 21 May 2014 13:11:33 +0000 (15:11 +0200)]
drm/irq: Coding style fix

Noticed by Thierry Reding in his review, but I've merged the drm
vblank rework topic branch a bit too quickly. So separate fixup.

Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Provide DPIO diagrams as docboox tables
Ville Syrjälä [Fri, 25 Apr 2014 17:14:32 +0000 (20:14 +0300)]
drm/i915: Provide DPIO diagrams as docboox tables

The ascii art version of the DPIO diagram gets mangled by docbook, so
we can't use it there. Insted provide another version built using
<table>.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add a brief description of the VLV display PHY internals
Ville Syrjälä [Fri, 25 Apr 2014 17:14:31 +0000 (20:14 +0300)]
drm/i915: Add a brief description of the VLV display PHY internals

Document the internal structure of the VLV display PHY a bit to help
people understand how the different register blocks relate to each
other.

v2: Add a bit more text
    Make it a DOC: comment, but leave the ascii art out since
    it would get mangled

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add null state batch to active list
Mika Kuoppala [Wed, 21 May 2014 16:01:06 +0000 (19:01 +0300)]
drm/i915: Add null state batch to active list

for proper refcounting to take place as we use
i915_add_request() for it.

i915_add_request() also takes the context for the request
from ring->last_context so move the null state batch
submission after the ring context has been set.

v2: we need to check for correct ring now (Ville Syrjälä)
v3: no need to expose i915_gem_move_object_to_active (Chris Wilson)
v4: cargoculted vma/active/inactive error handling removed (Chris Wilson)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Re-enable vblank irqs for already active pipes
Ville Syrjälä [Tue, 20 May 2014 14:20:05 +0000 (17:20 +0300)]
drm/i915: Re-enable vblank irqs for already active pipes

If a pipe is already active when we init/resume there might not be a
full modeset afterwards so drm_vblank_on() may not get called. In such
a case if someone is holding a vblank reference across a suspend/resume
cycle drm_vblank_get() called after resuming won't re-enable the vblank
interrupts.

So in order to make sure vblank interrupts get re-enabled post-resume,
call drm_vblank_on() in intel_sanitize_crtc() if the crtc is already
active.

v2: Also drm_vblank_off() if the pipe got disabled magically

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Testecase: igt/kms_flip/vblank-vs-suspend
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agoMerge branch 'topic/drm-vblank-rework' into drm-intel-next-queued
Daniel Vetter [Wed, 21 May 2014 09:45:40 +0000 (11:45 +0200)]
Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queued

Pull in the drm vblank rework from Ville and me. drm core parts acked
by Dave Airlie

Conflicts:
drivers/gpu/drm/i915/intel_display.c

Just a bit of fun around the placement of drm_vblank_on. This merge
resolution has been tested in drm-intel-nightly for a while already.

Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Accurately initialize fifo underrun state on gmch platforms
Daniel Vetter [Wed, 14 May 2014 13:40:34 +0000 (15:40 +0200)]
drm/i915: Accurately initialize fifo underrun state on gmch platforms

We don't have hardware based disable bits on gmch platforms, so need
to block spurious underrun reports in software. Which means that we
_must_ start out with fifo underrun reporting disabled everywhere.

This is in big contrast to ilk/hsw/cpt where there's only _one_
disable bit for all platforms and hence we must allow underrun
reporting on disabled pipes. Otherwise nothing really works,
especially the CRC support since that's key'ed off the same irq
disable bit.

This allows us to ditch the fifo underrun reporting hack from the vlv
runtime pm code and unexport the internal function from i915_irq.c
again. Yay!

v2: Keep the display irq disabling, spotted by Imre.

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: rip our vblank reset hacks for runtime PM
Daniel Vetter [Wed, 14 May 2014 13:26:49 +0000 (15:26 +0200)]
drm/i915: rip our vblank reset hacks for runtime PM

Now that we unconditionally dtrt when disabling/enabling crtcs we
don't need any hacks any longer to keep the vblank logic sane when
all the registers go poof. So let's rip it all out.

This essentially undoes

commit 9dbd8febb4dbc9199fcf340b882eb930e36b65b6
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date:   Tue Jul 23 10:48:11 2013 -0300

    drm/i915: update last_vblank when disabling the power well

Apparently igt/kms_flip is already powerful enough to exercise this
properly, yay! See the reference regression report for details.

v2: Update testcase name

References: https://bugs.freedesktop.org/show_bug.cgi?id=66808
Testcase: igt/kms_flip/vblank-vs-*-rpm
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use new kms-native vblank functions
Daniel Vetter [Thu, 15 May 2014 13:33:46 +0000 (15:33 +0200)]
drm/i915: Use new kms-native vblank functions

Only the low-level irq handling functions still use integer crtc
indices with this. But fixing that will require a lot more sugery
and some good ideas for backwards compat with old ums userspace.
Both in drivers and in the drm core.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/irq: Add kms-native crtc interface functions
Daniel Vetter [Thu, 15 May 2014 13:32:12 +0000 (15:32 +0200)]
drm/irq: Add kms-native crtc interface functions

We need to start somewhere ... With this the only places left in i915
where we use pipe integers is in the interrupt handling code. And
there it actually makes some amount of sense.

v2:
- Polish kerneldoc a bit (Thierry).
- Drop "dev" parameter since it's unecessary.
- Split out i915 changes (Thierry).

Cc: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/irq: kerneldoc polish
Daniel Vetter [Thu, 8 May 2014 14:41:51 +0000 (16:41 +0200)]
drm/irq: kerneldoc polish

- Integrate into the drm DocBook
- Disable kerneldoc for functions not exported to drivers.
- Properly document the new drm_vblank_on|off and add cautious
  comments explaining when drm_vblank_pre|post_modesets shouldn't be
  used.
- General polish and OCD.

v2: Polish as suggested by Thierry.

Cc: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/doc: Discourage usage of MODESET_CTL ioctl
Daniel Vetter [Thu, 8 May 2014 13:39:19 +0000 (15:39 +0200)]
drm/doc: Discourage usage of MODESET_CTL ioctl

Leftover from the old days of ums and should be used any longer. Since

commit 29935554b384b1b3a7377d6f0b03b21d18a61683
Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Date:   Wed May 30 00:58:09 2012 +0200

    drm: Disallow DRM_IOCTL_MODESET_CTL for KMS drivers

it is a complete no-Op for kms drivers.

v2: Fix up mangled sentence spotted by Michel.

Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Remove drm_vblank_pre/post_modeset calls
Daniel Vetter [Tue, 11 Mar 2014 16:09:31 +0000 (17:09 +0100)]
drm/i915: Remove drm_vblank_pre/post_modeset calls

Originally these functions have been for user modesetting drivers to
ensure vblank processing doesn't fall over completely around modeset
changes. This has been carried over ever since then.

Now that Ville cleaned our vblank handling with an explicit
drm_vblank_off/on braket when disabling/enabling crtcs. So this seems
to be unnecessary now. The most important side effect was that due to
the delayed vblank disabling we have been pretty much guaranteed to
receive a vblank interrupt soonish after a crtc was enabled.

Note that our vblank handling across modeset is still fairly decent
fubar - we don't actually handle vblank counter all to well.
drm_update_vblank_count will make sure that the frame counter always
rolls forward, but userspace isn't really all to ready to cope with
the big jumps this causes.

This isn't a big mostly because the hardware retains the frame
counter. But with runtime pm and also across suspend/resume we fall
over.

Fixing this is a lot more involved and also needs som i-g-ts. So
material for another patch series.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Move buffer pinning and ring selection to intel_crtc_page_flip()
Ville Syrjälä [Tue, 15 Apr 2014 18:41:38 +0000 (21:41 +0300)]
drm/i915: Move buffer pinning and ring selection to intel_crtc_page_flip()

All of the .queue_flip() callbacks duplicate the same code to pin the
buffers and calculate the gtt_offset. Move that code to
intel_crtc_page_flip(). In order to do that we must also move the ring
selection logic there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Drop the excessive vblank waits from modeset codepaths
Ville Syrjälä [Fri, 25 Apr 2014 10:30:12 +0000 (13:30 +0300)]
drm/i915: Drop the excessive vblank waits from modeset codepaths

Now that we've plugged the mmio vs. ring flip race, we shouldn't need
these vblank waits in the modeset codepaths anymore. So get rid of
them.

v2: gen2 needs to wait for planes to turn off before disabling pipe

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Wait for vblank in hsw_enable_ips()
Ville Syrjälä [Tue, 15 Apr 2014 18:41:35 +0000 (21:41 +0300)]
drm/i915: Wait for vblank in hsw_enable_ips()

Now that the vblank wait is gone from intel_enable_primary_plane(),
hsw_enable_ips() needs to do the vblank wait itself.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix mmio vs. CS flip race on ILK+
Ville Syrjälä [Tue, 15 Apr 2014 18:41:34 +0000 (21:41 +0300)]
drm/i915: Fix mmio vs. CS flip race on ILK+

Starting from ILK, mmio flips also cause a flip done interrupt to be
signalled. This means if we first do a set_base and follow it
immediately with the CS flip, we might mistake the flip done interrupt
caused by the set_base as the flip done interrupt caused by the CS
flip.

The hardware has a flip counter which increments every time a mmio or
CS flip is issued. It basically counts the number of DSPSURF register
writes. This means we can sample the counter before we put the CS
flip into the ring, and then when we get a flip done interrupt we can
check whether the CS flip has actually performed the surface address
update, or if the interrupt was caused by a previous but yet
unfinished mmio flip.

Even with the flip counter we still have a race condition of the CS flip
base address update happens after the mmio flip done interrupt was
raised but not yet processed by the driver. When the interrupt is
eventually processed, the flip counter will already indicate that the
CS flip has been executed, but it would not actually complete until the
next start of vblank. We can use the DSPSURFLIVE register to check
whether the hardware is actually scanning out of the buffer we expect,
or if we managed hit this race window.

This covers all the cases where the CS flip actually changes the base
address. If the base address remains unchanged, we might still complete
the CS flip before it has actually completed. But since the address
didn't change anyway, the premature flip completion can't result in
userspace overwriting data that's still being scanned out.

CTG already has the flip counter and DSPSURFLIVE registers, and
although the flip done interrupt is still limited to CS flips alone,
the code now also checks the flip counter on CTG as well.

v2: s/dspsurf/gtt_offset/ (Chris)

Testcase: igt/kms_mmio_vs_cs_flip/setcrtc_vs_cs_flip
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73027
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Add g4x_ prefix to flip_count_after_eq.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: drop encoder hot_plug calls at resume
Jesse Barnes [Tue, 20 May 2014 22:25:33 +0000 (15:25 -0700)]
drm/i915: drop encoder hot_plug calls at resume

We really just want to go detect displays again and fire off a hotplug
event if things have changed, not go through full hotplug processing.

Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Drop now misleading DDI comment from dp_link_down
Daniel Vetter [Tue, 20 May 2014 20:46:50 +0000 (22:46 +0200)]
drm/i915: Drop now misleading DDI comment from dp_link_down

Since

commit 2e82a7203182d0883d0f9450d40ad6e1c6578ad9
Author: Imre Deak <imre.deak@intel.com>
Date:   Fri Jan 17 15:46:43 2014 +0200

    drm/i915: don't disable DP port after a failed link training

and

commit 5d6a1116c6475404e6505b708320f9579ae19acd
Author: Imre Deak <imre.deak@intel.com>
Date:   Thu Jan 16 18:35:57 2014 +0200

    drm/i915: don't disable the DP port if the link is lost

we no longer call intel_dp_link_down from generic DP code, but only
from the !HAS_DDI dp encoder functions. hsw/bdw have their own encoder
disabling callback in intel_ddi.c.

Hence the early return is no longer needed and the big comment just
confusing, so let's rip it out. To ensure what we don't accidentally
use this again on ddi encoders add a WARN_ON instead.

Spotted while reading through intel_dp.c

Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Add drm_vblank_on()
Ville Syrjälä [Wed, 19 Feb 2014 19:29:49 +0000 (21:29 +0200)]
drm: Add drm_vblank_on()

drm_vblank_off() will turn off vblank interrupts, but as long as the
refcount is elevated drm_vblank_get() will not re-enable them. This
is a problem is someone is holding a vblank reference while a modeset is
happening, and the driver requires vblank interrupt to work during that
time.

Add drm_vblank_on() as a counterpart to drm_vblank_off() which will
re-enabled vblank interrupts if the refcount is already elevated. This
will allow drivers to choose the specific places in the modeset sequence
at which vblank interrupts get disabled and enabled.

Testcase: igt/kms_flip/*-vs-suspend
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add Testcase tag for the igt I've written.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Make blocking vblank wait return when the vblank interrupts get disabled
Ville Syrjälä [Thu, 6 Mar 2014 15:27:39 +0000 (17:27 +0200)]
drm: Make blocking vblank wait return when the vblank interrupts get disabled

If there's a blocking vblank wait in progress while the vblank interrupt
gets disabled, the current code will just let the vblank wait time out.
Instead make it return immediately when vblank interrupts get disabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Make the vblank disable timer per-crtc
Ville Syrjälä [Wed, 19 Feb 2014 17:36:08 +0000 (19:36 +0200)]
drm: Make the vblank disable timer per-crtc

Currently there's one per-device vblank disable timer, and it gets
reset wheneven the vblank refcount for any crtc drops to zero. That
means that one crtc could accidentally be keeping the vblank interrupts
for other crtcs enabled even if there are no users for them. Make the
disable timer per-crtc to avoid this issue.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Use correct spinlock flavor in drm_vblank_get()
Peter Hurley [Wed, 21 Aug 2013 01:51:12 +0000 (21:51 -0400)]
drm: Use correct spinlock flavor in drm_vblank_get()

The irq flags state is already established by the outer
spin_lock_irqsave(); re-disabling irqs is redundant.

Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: shuffle panel code
Jani Nikula [Tue, 29 Apr 2014 20:30:48 +0000 (23:30 +0300)]
drm/i915: shuffle panel code

Somehow a few functions have been dropped in the middle of backlight
code. Move them around. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Clear GDSR after reset on ILK
Ville Syrjälä [Mon, 19 May 2014 16:23:26 +0000 (19:23 +0300)]
drm/i915: Clear GDSR after reset on ILK

Clear the reset domain after a succesful GPU reset on ilk. We already
do that on gen4, so let's try to be a bit more consistent. And if
ether render or media reset fails, we might use the leftover value
in the register to pinpoint the culprit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Kill RMW from ILK reset code
Ville Syrjälä [Mon, 19 May 2014 16:23:25 +0000 (19:23 +0300)]
drm/i915: Kill RMW from ILK reset code

All the other bits in the GDSR register are read-only, so we don't have
to preserve them when we perform a GPU reset.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: add missing unregister_oom_notifier to the error/unload path
Imre Deak [Tue, 20 May 2014 16:47:20 +0000 (19:47 +0300)]
drm/i915: add missing unregister_oom_notifier to the error/unload path

I'm trying to reduce the WARNs during driver reload and this was one of
them. Also while at it remove the redundant condition from before
unregister_shrinker().

v2:
- fix the error path too and move the unregister to its logical place
(Chris)
- remove redundant condition from before unregister_shrinker()

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>