GitHub/moto-9609/android_kernel_motorola_exynos9610.git
7 years agodrm/amdgpu/vce4: alloc mm table for MM sriov
Xiangliang Yu [Tue, 7 Mar 2017 08:40:55 +0000 (16:40 +0800)]
drm/amdgpu/vce4: alloc mm table for MM sriov

Allocate MM table for sriov device.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/virt: add structure for MM table
Xiangliang Yu [Tue, 28 Feb 2017 09:24:52 +0000 (17:24 +0800)]
drm/amdgpu/virt: add structure for MM table

Add new structure for MM table for multi media scheduler of sriov.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: disable uvd for sriov
Xiangliang Yu [Wed, 15 Feb 2017 09:25:43 +0000 (17:25 +0800)]
drm/amdgpu: disable uvd for sriov

disable uvd for sriov temporarily.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/vce4: enable doorbell for SRIOV
Xiangliang Yu [Tue, 7 Mar 2017 06:52:24 +0000 (14:52 +0800)]
drm/amdgpu/vce4: enable doorbell for SRIOV

VCE SRIOV need use doorbell and only works on VCN0 ring now

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Don't touch PG&CG for SRIOV MM
Xiangliang Yu [Tue, 7 Mar 2017 06:45:25 +0000 (14:45 +0800)]
drm/amdgpu: Don't touch PG&CG for SRIOV MM

For SRIOV, MM don't need to care about PG & CG, skip it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/vega10:fix DOORBELL64 scheme
Monk Liu [Fri, 30 Dec 2016 08:18:56 +0000 (16:18 +0800)]
drm/amdgpu/vega10:fix DOORBELL64 scheme

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:vega10: enable virtual display if set via module option
Alex Deucher [Wed, 22 Mar 2017 14:49:25 +0000 (10:49 -0400)]
drm/amdgpu:vega10: enable virtual display if set via module option

Enable virtual displays if the user has enabled them via the
kernel command line.  Useful in virtual or headless environments.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/soc15: enable virtual dce for vf
Xiangliang Yu [Tue, 28 Feb 2017 09:22:03 +0000 (17:22 +0800)]
drm/amdgpu/soc15: enable virtual dce for vf

VF need virtual dce, enable it if device is vf.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/soc15: init virt ops for vf
Xiangliang Yu [Wed, 8 Mar 2017 07:06:47 +0000 (15:06 +0800)]
drm/amdgpu/soc15: init virt ops for vf

If gpu device is vf, set virt ops so that guest can talk with GPU
hypervisor.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/virt: impl mailbox for ai
Xiangliang Yu [Fri, 10 Mar 2017 06:18:17 +0000 (14:18 +0800)]
drm/amdgpu/virt: impl mailbox for ai

Implement mailbox protocol for AI so that guest vf can communicate
with GPU hypervisor.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/dce_virtual: bypass DPM for vf
Xiangliang Yu [Tue, 14 Feb 2017 08:08:18 +0000 (16:08 +0800)]
drm/amdgpu/dce_virtual: bypass DPM for vf

If enable DPM for VF, always get lot of warn_slow_patch_null in
dmesg and vf doesn't support DPM.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
Xiangliang Yu [Tue, 28 Feb 2017 09:06:36 +0000 (17:06 +0800)]
drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush

two reasons:
1. there is a spinlock around;
2. vm register is pf/vf copy, vf can access via mmio safely.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/soc15: bypass PSP for VF
Xiangliang Yu [Tue, 28 Feb 2017 08:59:28 +0000 (16:59 +0800)]
drm/amdgpu/soc15: bypass PSP for VF

Bypass PSP block for VF device.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/sdma4:re-org SDMA initial steps for sriov
Monk Liu [Thu, 15 Dec 2016 05:56:53 +0000 (13:56 +0800)]
drm/amdgpu/sdma4:re-org SDMA initial steps for sriov

Rework sdma init to support SR-IOV.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:bypass RLC init for SRIOV
Monk Liu [Mon, 12 Dec 2016 09:18:37 +0000 (17:18 +0800)]
drm/amdgpu:bypass RLC init for SRIOV

one issue unresolved for RLC:
rlc will go wrong completely if there is a soft_reset
before RLC ucode loading.

to workaround above issue, we can totally ignore RLC
in guest driver side due to there was already full
initialization on RLC side by GIM

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx9: impl gfx9 meta data emit
Xiangliang Yu [Tue, 7 Mar 2017 05:56:03 +0000 (13:56 +0800)]
drm/amdgpu/gfx9: impl gfx9 meta data emit

Insert ce meta prior to cntx_cntl and de follow it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu:impl gfx9 cond_exec (v2)
Monk Liu [Fri, 18 Nov 2016 09:16:36 +0000 (17:16 +0800)]
drm/amdgpu:impl gfx9 cond_exec (v2)

it is needed for virtualization

v2: squash in wptr value fix

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: init kiq and kcq for vega10
Xiangliang Yu [Tue, 28 Feb 2017 08:48:47 +0000 (16:48 +0800)]
drm/amdgpu: init kiq and kcq for vega10

Init kiq via cpu mmio and init kcq through kiq.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx9: fullfill kiq irq funcs (v2)
Xiangliang Yu [Mon, 13 Feb 2017 08:49:34 +0000 (16:49 +0800)]
drm/amdgpu/gfx9: fullfill kiq irq funcs (v2)

Fullfill KIQ irq funcs to support kiq interrupt.

v2: squash in adding interrupt src

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx9: fullfill kiq funcs (v2)
Xiangliang Yu [Mon, 13 Feb 2017 08:36:17 +0000 (16:36 +0800)]
drm/amdgpu/gfx9: fullfill kiq funcs (v2)

Fullfill kiq funcs to support kiq ring.

v2: squash in 64bit ptr fix

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add kiq ring for gfx9
Xiangliang Yu [Mon, 13 Feb 2017 08:13:46 +0000 (16:13 +0800)]
drm/amdgpu: add kiq ring for gfx9

Allocate KIQ ring in sw_init for gfx9.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: impl sriov detection for vega10
Xiangliang Yu [Wed, 8 Mar 2017 07:00:48 +0000 (15:00 +0800)]
drm/amdgpu: impl sriov detection for vega10

Read vega10 hw register to detect if sriov is enabled, and call
it before IP blocks setting.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx9: programing wptr_poll_addr register
Monk Liu [Wed, 2 Nov 2016 07:33:46 +0000 (15:33 +0800)]
drm/amdgpu/gfx9: programing wptr_poll_addr register

Required for SR-IOV.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add Vega10 Device IDs (v2)
Junwei Zhang [Fri, 3 Mar 2017 21:54:00 +0000 (16:54 -0500)]
drm/amdgpu: add Vega10 Device IDs (v2)

v2: add AMD_EXP_HW_SUPPORT for now

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Set the IP blocks for vega10
Ken Wang [Mon, 6 Mar 2017 19:53:16 +0000 (14:53 -0500)]
drm/amdgpu: Set the IP blocks for vega10

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: soc15 enable (v3)
Ken Wang [Mon, 6 Mar 2017 19:49:53 +0000 (14:49 -0500)]
drm/amdgpu: soc15 enable (v3)

Add soc15 support and enable all the IPs for vega10.

v2: squash in xclk fix
v3: disable HDP MGCG

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add Vega10 powerplay support (v5)
Eric Huang [Mon, 6 Mar 2017 19:03:02 +0000 (14:03 -0500)]
drm/amd/powerplay: add Vega10 powerplay support (v5)

Adds power management support for vega10.

v2: squash in fan control and led config fixes from Rex
v3: squash in dead code removal and socvid fixes from Rex
v4: squash in dpm force level fix from Rex
v5: squash in latest headless, gpu load fixes from Rex

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add some display/powerplay interfaces
Eric Huang [Mon, 6 Mar 2017 18:13:48 +0000 (13:13 -0500)]
drm/amd/powerplay: add some display/powerplay interfaces

New interfaces needed to handle the new clock trees and
bandwidth requirements on vega10.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd: add structures for display/powerplay interface
Eric Huang [Mon, 6 Mar 2017 18:01:48 +0000 (13:01 -0500)]
drm/amd: add structures for display/powerplay interface

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add some new structures for Vega10
Eric Huang [Mon, 6 Mar 2017 17:34:32 +0000 (12:34 -0500)]
drm/amd/powerplay: add some new structures for Vega10

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add global PowerPlay mutex.
Rex Zhu [Mon, 20 Feb 2017 09:07:36 +0000 (17:07 +0800)]
drm/amd/powerplay: add global PowerPlay mutex.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add new atomfirmware based helpers for powerplay
Eric Huang [Sat, 4 Mar 2017 00:20:47 +0000 (19:20 -0500)]
drm/amdgpu: add new atomfirmware based helpers for powerplay

New helpers for fetching info out of atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Ken.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add new Vega10's ppsmc header file
Eric Huang [Fri, 3 Mar 2017 23:50:50 +0000 (18:50 -0500)]
drm/amd/powerplay: add new Vega10's ppsmc header file

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: add smu9 header files for Vega10
Eric Huang [Fri, 3 Mar 2017 23:49:56 +0000 (18:49 -0500)]
drm/amd/powerplay: add smu9 header files for Vega10

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add SMC firmware into global ucode list for psp loading
Huang Rui [Thu, 16 Feb 2017 03:53:38 +0000 (11:53 +0800)]
drm/amdgpu: add SMC firmware into global ucode list for psp loading

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add psp firmware info into info query and debugfs
Huang Rui [Sat, 4 Mar 2017 00:15:26 +0000 (19:15 -0500)]
drm/amdgpu: add psp firmware info into info query and debugfs

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add PSP driver for vega10 (v2)
Huang Rui [Fri, 3 Mar 2017 23:37:23 +0000 (18:37 -0500)]
drm/amdgpu: add PSP driver for vega10 (v2)

PSP is responsible for firmware loading on SOC-15 asics.

v2: fix memory leak (Ken)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add initial vce 4.0 support for vega10
Leo Liu [Fri, 3 Mar 2017 23:27:49 +0000 (18:27 -0500)]
drm/amdgpu: add initial vce 4.0 support for vega10

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add initial uvd 7.0 support for vega10
Leo Liu [Fri, 3 Mar 2017 23:13:26 +0000 (18:13 -0500)]
drm/amdgpu: add initial uvd 7.0 support for vega10

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add vega10 interrupt handler
Ken Wang [Fri, 3 Mar 2017 23:06:01 +0000 (18:06 -0500)]
drm/amdgpu: add vega10 interrupt handler

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: implement GFX 9.0 support (v2)
Ken Wang [Fri, 3 Mar 2017 22:59:39 +0000 (17:59 -0500)]
drm/amdgpu: implement GFX 9.0 support (v2)

Add support for gfx v9.0.

v2: update golden settings from Ken

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add SDMA v4.0 implementation (v2)
Ken Wang [Fri, 3 Mar 2017 22:31:51 +0000 (17:31 -0500)]
drm/amdgpu: add SDMA v4.0 implementation (v2)

v2: fix Makefile

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Add GMC 9.0 support (v2)
Alex Xie [Thu, 9 Mar 2017 16:36:26 +0000 (11:36 -0500)]
drm/amdgpu: Add GMC 9.0 support (v2)

On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

v2: drop sdma from Makefile, fix duplicate return statement.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add NBIO 6.1 driver
Junwei Zhang [Fri, 3 Mar 2017 22:46:40 +0000 (17:46 -0500)]
drm/amdgpu: add NBIO 6.1 driver

This handles nbio 6.1 specific implementations which
are used by various other IPs.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
Alex Xie [Fri, 3 Mar 2017 21:49:39 +0000 (16:49 -0500)]
drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
Alex Xie [Fri, 3 Mar 2017 21:47:11 +0000 (16:47 -0500)]
drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: gart fixes for vega10
Alex Deucher [Fri, 3 Mar 2017 21:42:27 +0000 (16:42 -0500)]
drm/amdgpu: gart fixes for vega10

Flags need to be 0 to be considered invalid.

Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add psp firmware header info
Huang Rui [Fri, 3 Mar 2017 21:25:23 +0000 (16:25 -0500)]
drm/amdgpu: add psp firmware header info

Defines the header info for the psp firmware.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: rework common ucode handling for vega10
Huang Rui [Fri, 3 Mar 2017 21:20:35 +0000 (16:20 -0500)]
drm/amdgpu: rework common ucode handling for vega10

Handle ucode differences in vega10.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: don't validate TILE_SPLIT on GFX9
Marek Olšák [Fri, 3 Mar 2017 21:03:15 +0000 (16:03 -0500)]
drm/amdgpu: don't validate TILE_SPLIT on GFX9

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add tiling flags for GFX9 (v2)
Alex Deucher [Fri, 3 Mar 2017 21:00:11 +0000 (16:00 -0500)]
drm/amdgpu: add tiling flags for GFX9 (v2)

v2: Marek: allow shifts >32 in AMDGPU_TILING_SET/GET

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Add asic family for vega10
Alex Deucher [Fri, 3 Mar 2017 20:54:06 +0000 (15:54 -0500)]
drm/amdgpu: Add asic family for vega10

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add NGG parameters
Alex Deucher [Tue, 28 Mar 2017 16:52:08 +0000 (12:52 -0400)]
drm/amdgpu: add NGG parameters

NGG (Next Generation Graphics) is a new feature in GFX9.0.  This
adds the relevant parameters.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add PTE defines for MTYPE
Alex Deucher [Fri, 3 Mar 2017 20:23:14 +0000 (15:23 -0500)]
drm/amdgpu: add PTE defines for MTYPE

New on SOC-15 asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add IV trace point
Christian König [Tue, 6 Dec 2016 08:41:55 +0000 (03:41 -0500)]
drm/amdgpu: add IV trace point

This allows us to grab IVs without spamming the log.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: update IH IV ring entry for soc-15
Alex Deucher [Fri, 3 Mar 2017 20:08:30 +0000 (15:08 -0500)]
drm/amdgpu: update IH IV ring entry for soc-15

Reflect the new format on soc-15 asics.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
Alex Deucher [Fri, 3 Mar 2017 19:26:51 +0000 (14:26 -0500)]
drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore

If the board is atomfirmware based.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
Alex Xie [Tue, 14 Feb 2017 17:04:52 +0000 (12:04 -0500)]
drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add 64bit doorbell assignments
Ken Wang [Fri, 18 Mar 2016 07:41:42 +0000 (15:41 +0800)]
drm/amdgpu: add 64bit doorbell assignments

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: gb_addr_config struct
Andrey Grodzovsky [Mon, 12 Dec 2016 18:40:37 +0000 (13:40 -0500)]
drm/amdgpu: gb_addr_config struct

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: use new flag to handle different firmware loading method
Huang Rui [Tue, 1 Nov 2016 07:35:38 +0000 (15:35 +0800)]
drm/amdgpu: use new flag to handle different firmware loading method

This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add clinetid definition for vega10
ken [Thu, 9 Mar 2017 16:34:42 +0000 (11:34 -0500)]
drm/amdgpu: add clinetid definition for vega10

Signed-off-by: ken <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add vega10 chip name
Ken Wang [Wed, 9 Mar 2016 01:28:32 +0000 (09:28 +0800)]
drm/amdgpu: add vega10 chip name

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add common soc15 headers
Ken Wang [Mon, 6 Mar 2017 17:41:22 +0000 (12:41 -0500)]
drm/amdgpu: add common soc15 headers

These are used by various IP modules.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add SDMA 4.0 packet header
Alex Deucher [Thu, 2 Mar 2017 22:49:04 +0000 (17:49 -0500)]
drm/amdgpu: add SDMA 4.0 packet header

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add gfx9 clearstate header
Alex Deucher [Thu, 2 Mar 2017 22:48:14 +0000 (17:48 -0500)]
drm/amdgpu: add gfx9 clearstate header

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd: Add MQD structs for GFX V9
Felix Kuehling [Thu, 2 Mar 2017 21:57:08 +0000 (16:57 -0500)]
drm/amd: Add MQD structs for GFX V9

This header defines the gfx v9 MEC structures.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add the VCE 4.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:43:33 +0000 (16:43 -0500)]
drm/amdgpu: add the VCE 4.0 register headers

These are the Video Compression Engine registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add the UVD 7.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:42:58 +0000 (16:42 -0500)]
drm/amdgpu: add the UVD 7.0 register headers

These are the Unifed Video Decoder registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add THM 9.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:42:12 +0000 (16:42 -0500)]
drm/amdgpu: add THM 9.0 register headers

These are the THerMal control registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add SMUIO 9.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:41:21 +0000 (16:41 -0500)]
drm/amdgpu: add SMUIO 9.0 register headers

These are the System Managment Unit IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add SDMA 4.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:40:41 +0000 (16:40 -0500)]
drm/amdgpu: add SDMA 4.0 register headers

These are the System DMA register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add OSSSYS 4.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:39:12 +0000 (16:39 -0500)]
drm/amdgpu: add OSSSYS 4.0 register headers

These are the OS Services register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add NBIO 6.1 register headers
Alex Deucher [Thu, 2 Mar 2017 21:38:26 +0000 (16:38 -0500)]
drm/amdgpu: add NBIO 6.1 register headers

These are the Bus IO registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add NBIF 6.1 register headers
Alex Deucher [Thu, 2 Mar 2017 21:37:25 +0000 (16:37 -0500)]
drm/amdgpu: add NBIF 6.1 register headers

These are the Bus InterFace registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add MP 9.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:36:07 +0000 (16:36 -0500)]
drm/amdgpu: add MP 9.0 register headers

MP is the system management controller on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add the MMHUB 1.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:34:19 +0000 (16:34 -0500)]
drm/amdgpu: add the MMHUB 1.0 register headers

Add the MultiMedia Hub registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add the HDP 4.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:33:31 +0000 (16:33 -0500)]
drm/amdgpu: add the HDP 4.0 register headers

These are the Host Data Path registers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add the GC 9.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:32:16 +0000 (16:32 -0500)]
drm/amdgpu: add the GC 9.0 register headers

Add the Graphics Core register headers for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Add the DCE 12.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:31:08 +0000 (16:31 -0500)]
drm/amdgpu: Add the DCE 12.0 register headers

These are the register headers for the Display
and Composition Engine on vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: Add ATHUB 1.0 register headers
Alex Deucher [Thu, 2 Mar 2017 21:30:06 +0000 (16:30 -0500)]
drm/amdgpu: Add ATHUB 1.0 register headers

ATHUB is part of the memory controller on soc15 asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add vega10_enum.h
Alex Deucher [Thu, 2 Mar 2017 21:29:09 +0000 (16:29 -0500)]
drm/amdgpu: add vega10_enum.h

This adds the register bitfield enums for vega10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add soc15ip.h
Alex Deucher [Thu, 2 Mar 2017 21:28:29 +0000 (16:28 -0500)]
drm/amdgpu: add soc15ip.h

This header defines the IP layout for soc15 based SoCs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add basic support for atomfirmware.h (v3)
Alex Deucher [Fri, 23 Sep 2016 20:23:41 +0000 (16:23 -0400)]
drm/amdgpu: add basic support for atomfirmware.h (v3)

This adds basic support for asics that use atomfirmware.h
to define their vbios tables.

v2: rebase
v3: squash in num scratch reg fix

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: move atom scratch setup into amdgpu_atombios.c
Alex Deucher [Fri, 23 Sep 2016 17:10:49 +0000 (13:10 -0400)]
drm/amdgpu: move atom scratch setup into amdgpu_atombios.c

There will be a slightly different version for atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agoamdgpu: detect if we are using atomfirmware or atombios for vbios (v2)
Alex Deucher [Mon, 13 Feb 2017 21:01:58 +0000 (16:01 -0500)]
amdgpu: detect if we are using atomfirmware or atombios for vbios (v2)

Supposedly atomfirmware rom header is 3.3 atombios is 1.1.

v2: rebased on newer kernel

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add the new atomfirmware interface header
Alex Deucher [Thu, 2 Mar 2017 21:55:42 +0000 (16:55 -0500)]
drm/amdgpu: add the new atomfirmware interface header

soc15 asics have a new vbios interface.  These headers
define that interface.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freed
Nicolai Hähnle [Thu, 23 Mar 2017 18:36:31 +0000 (19:36 +0100)]
drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freed

We will add the fence to freed buffer objects in a later commit, to ensure
that the underlying memory can only be re-used after all references in
page tables have been cleared.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amd/powerplay: restore disabling power containment on Fiji (v2)
Eric Huang [Mon, 13 Mar 2017 18:15:48 +0000 (14:15 -0400)]
drm/amd/powerplay: restore disabling power containment on Fiji (v2)

Power containment will degrade performance in some compute tests.
Restore disabling it as before code refining in powerplay.

v2: only in the compute profile

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: further KIQ parameter cleanup
Alex Deucher [Thu, 23 Mar 2017 17:00:20 +0000 (13:00 -0400)]
drm/amdgpu/gfx8: further KIQ parameter cleanup

The ring structure already has what we need.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: store the eop gpu addr in the ring structure
Alex Deucher [Thu, 23 Mar 2017 06:16:07 +0000 (02:16 -0400)]
drm/amdgpu/gfx8: store the eop gpu addr in the ring structure

Avoids passing around additional parameters during setup.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: reduce the functon params for mpq setup
Alex Deucher [Thu, 23 Mar 2017 06:06:04 +0000 (02:06 -0400)]
drm/amdgpu/gfx8: reduce the functon params for mpq setup

Everything we need is in the ring structure.  No need to
pass all the bits explicitly.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: reserve kiq eop object before unmapping it
Alex Deucher [Thu, 23 Mar 2017 05:51:53 +0000 (01:51 -0400)]
drm/amdgpu/gfx8: reserve kiq eop object before unmapping it

It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: fold loops in kiq_resume()
Alex Deucher [Thu, 23 Mar 2017 05:40:19 +0000 (01:40 -0400)]
drm/amdgpu/gfx8: fold loops in kiq_resume()

No need to loop through the compute queues twice.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: test KIQ before compute rings
Alex Deucher [Thu, 23 Mar 2017 05:38:11 +0000 (01:38 -0400)]
drm/amdgpu/gfx8: test KIQ before compute rings

If KIQ isn't working, the compute rings won't work either.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: reserve mqd objects before mapping them
Alex Deucher [Thu, 23 Mar 2017 05:35:44 +0000 (01:35 -0400)]
drm/amdgpu/gfx8: reserve mqd objects before mapping them

It's required.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: rename some functions
Alex Deucher [Tue, 28 Mar 2017 16:50:32 +0000 (12:50 -0400)]
drm/amdgpu/gfx8: rename some functions

To better match where they are used.  Called from sw_init
and sw_fini.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu/gfx8: whitespace cleanup
Alex Deucher [Thu, 23 Mar 2017 05:05:08 +0000 (01:05 -0400)]
drm/amdgpu/gfx8: whitespace cleanup

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: load mc firware in driver for Polaris.
Rex Zhu [Tue, 21 Mar 2017 04:51:48 +0000 (12:51 +0800)]
drm/amdgpu: load mc firware in driver for Polaris.

load mc ucode in driver if VBIOS not loaded
a full version of MC ucode,

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: jimqu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
7 years agodrm/amdgpu: fix duplicated code
Chunming Zhou [Tue, 21 Mar 2017 02:09:33 +0000 (10:09 +0800)]
drm/amdgpu: fix duplicated code

it could come from branch merge.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>