GitHub/moto-9609/android_kernel_motorola_exynos9610.git
9 years agodrm/i915: Drop a spurious intel_pre_plane_update() call
Ville Syrjälä [Fri, 3 Jul 2015 08:22:27 +0000 (11:22 +0300)]
drm/i915: Drop a spurious intel_pre_plane_update() call

Kill the extra intel_pre_plane_update() I accidentally added in

 commit 852eb00dc44ea2b8896e2fa27c6a36a1f697ba5a
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Wed Jun 24 22:00:07 2015 +0300

    drm/i915: Try to make sure cxsr is disabled around plane
    enable/disable

This fixes a load of warnings from the frontbuffer tracking.

Testcase: igt/kms_frontbuffer_tracking/fbc-1p-rte
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/opregion: start using extended didl
Jani Nikula [Thu, 2 Jul 2015 14:43:25 +0000 (17:43 +0300)]
drm/i915/opregion: start using extended didl

Adding support for did2, or the extended support display devices ID
list, increases the total to 15.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/opregion: abstract didl and did2 getter and setter
Jani Nikula [Thu, 2 Jul 2015 14:43:24 +0000 (17:43 +0300)]
drm/i915/opregion: abstract didl and did2 getter and setter

Make it easier to handle the extended didl. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/opregion: prefer DRM logging functions over pr_warn and dev_dbg
Jani Nikula [Thu, 2 Jul 2015 14:43:23 +0000 (17:43 +0300)]
drm/i915/opregion: prefer DRM logging functions over pr_warn and dev_dbg

Conform to same style as the rest of the driver.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/opregion: add new opregion stuff
Jani Nikula [Thu, 2 Jul 2015 14:43:22 +0000 (17:43 +0300)]
drm/i915/opregion: add new opregion stuff

Inluding extended didl and cpdl fields

Present since opregion version 3.0.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/opregion: use BUILD_BUG_ON to verify mailbox struct sizes
Jani Nikula [Thu, 2 Jul 2015 14:43:21 +0000 (17:43 +0300)]
drm/i915/opregion: use BUILD_BUG_ON to verify mailbox struct sizes

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/hotplug: document the hotplug handling in the driver
Jani Nikula [Thu, 2 Jul 2015 13:05:28 +0000 (16:05 +0300)]
drm/i915/hotplug: document the hotplug handling in the driver

Add an overview of the drm/i915 hotplug handling.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/audio: clarify HD audio documentation wrt modeset
Jani Nikula [Thu, 2 Jul 2015 13:05:27 +0000 (16:05 +0300)]
drm/i915/audio: clarify HD audio documentation wrt modeset

Clarify that audio enable/disable sequences are part of the modeset
sequence.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: set FDI translations to NULL on SKL
Paulo Zanoni [Fri, 3 Jul 2015 15:31:30 +0000 (12:31 -0300)]
drm/i915: set FDI translations to NULL on SKL

drivers/gpu/drm/i915/intel_ddi.c: In function ‘intel_prepare_ddi’:
drivers/gpu/drm/i915/intel_ddi.c:517:6: warning:
‘ddi_translations_fdi’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
   if (ddi_translations_fdi)
      ^
drivers/gpu/drm/i915/intel_ddi.c:446:30: note: ‘ddi_translations_fdi’
was declared here
  const struct ddi_buf_trans *ddi_translations_fdi;
                              ^

This line used to be there, but was removed by:

commit f8896f5d58e64bfd3c2b5f7c5ba5c3f3967e93c7
Author: David Weinehall <david.weinehall@linux.intel.com>
Date:   Thu Jun 25 11:11:03 2015 +030
    drm/i915/skl: Buffer translation improvements

Cc: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag and getparam
Abdiel Janulgue [Wed, 1 Jul 2015 07:12:23 +0000 (10:12 +0300)]
drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag and getparam

Ensures that the batch buffer is executed by the resource streamer.
And will let userspace know whether Resource Streamer is supported in
the kernel.

v2: Don't skip 1<<15 for the exec flags (Jani Nikula)
v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)

(from getparam patch)

v2: Update I915_PARAM_HAS_RESOURCE_STREAMER so it's after
    I915_PARAM_HAS_GPU_RESET.
v3: Only advertise RS support for hardware that supports it.
v4: Add HAS_RESOURCE_STREAMER() macro (Chris)

Testcase: igt/gem_exec_params
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
[danvet: squash in getparam patch since it'd break bisect, suggested
by Chris.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Enable resource streamer on Execlists
Abdiel Janulgue [Tue, 16 Jun 2015 10:39:42 +0000 (13:39 +0300)]
drm/i915: Enable resource streamer on Execlists

GEN8 and above uses Execlists by default instead of the legacy
ringbuffer for batch execution. This patch enables the resource
streamer bits when required.

Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com>
This version also adds the required bits to enable GEN8 Resource
Streamer context save and restore for Execlists.

Cc: ville.syrjala@linux.intel.com
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Enable Resource Streamer state save/restore on MI_SET_CONTEXT
Abdiel Janulgue [Tue, 16 Jun 2015 10:39:41 +0000 (13:39 +0300)]
drm/i915: Enable Resource Streamer state save/restore on MI_SET_CONTEXT

Also clarify comments on context size that the extra state for
Resource Streamer is included.

v2: Don't remove the extended save/restore enabled for older
    platforms. (Ville)
    Use new MI_SET_CONTEXT defines for HSW RS save/restore state
    instead of extended save/restore. (Daniel)

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
Abdiel Janulgue [Tue, 16 Jun 2015 10:39:40 +0000 (13:39 +0300)]
drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START

Adds support for enabling the resource streamer on the legacy
ringbuffer for HSW and GEN8.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: BUNs related to port PLL
Vandana Kannan [Wed, 1 Jul 2015 11:32:57 +0000 (17:02 +0530)]
drm/i915/bxt: BUNs related to port PLL

This patch contains changes based on 2 updates to the spec:
Port PLL VCO restriction raised up to 6700.
Port PLL now needs DCO amp override enable for all VCO frequencies.

v2: Sonika's review comment addressed
- dcoampovr_en_h variable not required
Based on a discussion with Siva, the following changes have been made.
- replace dco_amp var with #define BXT_DCO_AMPLITUDE
- set pll10 in a single assignment

v3:
Move DCO amplitude default value to i915_reg.h. Suggested by Siva.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2]
[danvet: Spell out BUN since not everyone knows what this means.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agoRevert "drm/i915: Disable 12bpc hdmi for now"
Ville Syrjälä [Tue, 30 Jun 2015 12:33:54 +0000 (15:33 +0300)]
Revert "drm/i915: Disable 12bpc hdmi for now"

HDMI 12bpc should be working fine now. Let it loose.

This reverts commit 5e3daaca09f5158eff9c92290faa1d2001ecc6e4.

v2: Rebased due to CHV/BXT port clock check improvemnts

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Account for CHV/BXT DPLL clock limitations
Ville Syrjälä [Tue, 30 Jun 2015 16:23:59 +0000 (19:23 +0300)]
drm/i915: Account for CHV/BXT DPLL clock limitations

CHV/BXT DPLL can't generate frequencies in the 216-240 MHz range.
Account for that when checking whether the HDMI port clock is valid.
This is particularly important for BXT since it can otherwise do
12bpc, and standard 1920x1080p60 CEA modes land right in the middle
of that range when the clock gets multiplied to account for 12bpc.

With the extra checks we will now filter out any mode where both
8bpc and 12bpc clock are within the gap. During modeset we then
pick whichever mode works, favoring 12bpc if both are possible.

12bpc isn't supported on CHV so we simply end up filtering out any
mode where the 8bpc port clock is in the gap.

v2: Fix crtc_clock vs. port_clock fumble in compute_config() (Imre)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Bump HDMI min port clock to 25 MHz
Ville Syrjälä [Tue, 30 Jun 2015 12:33:52 +0000 (15:33 +0300)]
drm/i915: Bump HDMI min port clock to 25 MHz

Increase the HDMI port minimum port clock from 20 to 25 MHz. This is
is the minimum listed in the DVI/HDMI specs, and it's also the
documented minimum DPLL frequency for most of our platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platforms
Ville Syrjälä [Tue, 30 Jun 2015 12:33:51 +0000 (15:33 +0300)]
drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platforms

Take the HDMI 12bpc mode and pixel repeat into account when extracting
the dotclock from the hardware on DDI platforms.

Tested on HSW only.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-and-tested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agoGPU-DRM: Delete an unnecessary check before drm_property_unreference_blob()
Markus Elfring [Sun, 5 Jul 2015 19:55:10 +0000 (21:55 +0200)]
GPU-DRM: Delete an unnecessary check before drm_property_unreference_blob()

The drm_property_unreference_blob() function tests whether its argument
is NULL and then returns immediately.
Thus the test around the call is not needed.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Zhao Junwang <zhjwpku@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update DRIVER_DATE to 20150703
Daniel Vetter [Fri, 3 Jul 2015 13:53:23 +0000 (15:53 +0200)]
drm/i915: Update DRIVER_DATE to 20150703

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Per ppgtt scratch page
Mika Kuoppala [Tue, 30 Jun 2015 15:16:40 +0000 (18:16 +0300)]
drm/i915/gtt: Per ppgtt scratch page

Previously we have pointed the page where the individual ppgtt
scratch structures refer to, to be the instance which GGTT setup have
allocated. So it has been shared.

To achieve full isolation between ppgtts also in this regard,
allocate per ppgtt scratch page.

Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Changes required to enable DSI Video Mode on CHT
Gaurav K Singh [Wed, 1 Jul 2015 12:58:52 +0000 (15:58 +0300)]
drm/i915: Changes required to enable DSI Video Mode on CHT

On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct
dividor & ctrl values are written in cck regs for DSI. This patch has
been tested on CHT RVP with 1200 x 1920 panel.

v2 by Jani, rebased on earlier refactoring, original at [1].

[1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Support for higher DSI clk
Gaurav K Singh [Wed, 1 Jul 2015 12:58:51 +0000 (15:58 +0300)]
drm/i915: Support for higher DSI clk

For MIPI panels requiring higher DSI clk, values needs to be added
in lfsr_converts table for getting the correct values of pll ctrl
and dividor values which gets programmed in cck regs, otherwise DSI
PLL does not get locked leading to no display on the MIPI panel.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/dsi: abstract dsi bpp derivation from pixel format
Jani Nikula [Wed, 1 Jul 2015 12:58:50 +0000 (15:58 +0300)]
drm/i915/dsi: abstract dsi bpp derivation from pixel format

Nuke three copies of the same switch case.

Hopefully we can switch to a drm generic function later on, but that
will require us to swich to enum mipi_dsi_pixel_format first.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: don't increment the FBC threshold at fbc_enable
Paulo Zanoni [Tue, 30 Jun 2015 13:53:05 +0000 (10:53 -0300)]
drm/i915: don't increment the FBC threshold at fbc_enable

We first set the threshold value when we're allocating the CFB, and
then later at {ilk,gen7}_fbc_enable() we increment it in case we're
using 16bpp. While that is correct, it is dangerous: if we rework the
code a little bit in a way that allows us to call intel_fbc_enable()
without necessarily calling i915_gem_stolen_setup_compression() first,
we might end up incrementing threshold more than once. To prevent
that, increment a temporary variable instead.

v2: Rebase.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Report correct GGTT space usage
Tvrtko Ursulin [Wed, 1 Jul 2015 10:51:10 +0000 (11:51 +0100)]
drm/i915: Report correct GGTT space usage

Currently only normal views were accounted which under-accounts
the usage as reported in debugfs.

Introduce new helper, i915_gem_obj_total_ggtt_size, and use it
from call sites which want to know how much GGTT space are
objects using.

v2: Single loop in i915_gem_get_aperture_ioctl. (Chris Wilson)

v3: Walk GGTT active/inactive lists in i915_gem_get_aperture_ioctl
    for better efficiency. (Chris Wilson, Daniel Vetter)

v4: Make i915_gem_obj_total_ggtt_size private to debugfs. (Chris Wilson)

v5: Change unsigned long to u64. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Return struct i915_scratch_page from alloc_scratch
Mika Kuoppala [Tue, 30 Jun 2015 15:16:39 +0000 (18:16 +0300)]
drm/i915/gtt: Return struct i915_scratch_page from alloc_scratch

Every other alloc_* function return the pointer to the page
they alloc. Follow the convention with scratch page also.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Reorder page alloc/free/init functions
Mika Kuoppala [Tue, 30 Jun 2015 15:16:37 +0000 (18:16 +0300)]
drm/i915/gtt: Reorder page alloc/free/init functions

Maintain base page handling functions in order of
alloc, free, init. No functional changes.

v2: s/Introduce/Maintain (Michel)
v3: Rebase

Cc: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Reserve space improvements
John Harrison [Tue, 30 Jun 2015 11:40:55 +0000 (12:40 +0100)]
drm/i915: Reserve space improvements

An earlier patch was added to reserve space in the ring buffer for the
commands issued during 'add_request()'. The initial version was
pessimistic in the way it handled buffer wrapping and would cause
premature wraps and thus waste ring space.

This patch updates the code to better handle the wrap case. It no
longer enforces that the space being asked for and the reserved space
are a single contiguous block. Instead, it allows the reserve to be on
the far end of a wrap operation. It still guarantees that the space is
available so when the wrap occurs, no wait will happen. Thus the wrap
cannot fail which is the whole point of the exercise.

Also fixed a merge failure with some comments from the original patch.

v2: Incorporated suggestion by David Gordon to move the wrap code
inside the prepare function and thus allow a single combined
wait_for_space() call rather than doing one before the wrap and
another after. This also makes the prepare code much simpler and
easier to follow.

v3: Fix for 'effective_size' vs 'size' during ring buffer remainder
calculations (spotted by Tomas Elf).

For: VIZ-5115
CC: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: mask off the DPLL state checker bits we don't program
Imre Deak [Thu, 18 Jun 2015 14:25:53 +0000 (17:25 +0300)]
drm/i915/bxt: mask off the DPLL state checker bits we don't program

For the purpose of state checking we only care about the DPLL HW flags
that we actually program, so mask off the ones that we don't.

This fixes one set of DPLL state check failures.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: add DDI port HW readout support
Imre Deak [Mon, 22 Jun 2015 20:35:52 +0000 (23:35 +0300)]
drm/i915/bxt: add DDI port HW readout support

Add support for reading out the HW state for DDI ports. Since the actual
programming is very similar to the CHV/VLV DPIO PLL programming we can
reuse much of the logic from there.

This fixes the state checker failures I saw on my BXT with HDMI output.

v2:
- rebased on v2 of patch 4/5

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: calculate the port clock rate along with other PLL params
Imre Deak [Mon, 22 Jun 2015 20:35:51 +0000 (23:35 +0300)]
drm/i915: calculate the port clock rate along with other PLL params

Depending on the platform the port clock fed to the pipe can be the PLL's
post-divided fast clock rate or a /5 divided version of it. To make this
more obvious across the platforms calculate this port clock along with
the rest of the PLL parameters.

This is also needed by the next patch where we can reuse the CHV helper
for the BXT PLL HW readout code; so export the corresponding helper.

While at it also add a more descriptive name to the helpers and a
comment explaining what's being calculated.

No functional change.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/vlv: move the vlv PLL helper next to its platform counterparts
Imre Deak [Mon, 22 Jun 2015 20:35:50 +0000 (23:35 +0300)]
drm/i915/vlv: move the vlv PLL helper next to its platform counterparts

Move the helper next to the PLL helpers of the other platforms for
clarity.

No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: add PLL10 to the PLL state dumper
Imre Deak [Thu, 18 Jun 2015 14:25:55 +0000 (17:25 +0300)]
drm/i915/bxt: add PLL10 to the PLL state dumper

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: add missing DDI PLL registers to the state checking
Imre Deak [Thu, 18 Jun 2015 14:25:54 +0000 (17:25 +0300)]
drm/i915/bxt: add missing DDI PLL registers to the state checking

Although we have a fixed setting for the PLL9 and EBB4 registers, it
still makes sense to check them together with the rest of PLL registers.

While at it also remove a redundant comment about 10 bit clock enabling.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Buffer translation improvements
David Weinehall [Thu, 25 Jun 2015 08:11:03 +0000 (11:11 +0300)]
drm/i915/skl: Buffer translation improvements

This patch adds support for 0.85V VccIO on Skylake Y,
separate buffer translation tables for Skylake U,
and support for I_boost for the entries that needs this.

Changes in v2:
* Refactored the code a bit to move all DDI signal level setup to
  intel_ddi.c

Issue: VIZ-5677
Signed-off-by: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
[danvet: Apply style polish checkpatch suggested.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Zero unused WM1 watermarks on VLV/CHV
Ville Syrjälä [Wed, 24 Jun 2015 19:00:10 +0000 (22:00 +0300)]
drm/i915: Zero unused WM1 watermarks on VLV/CHV

The hardware supposedly ignores the WM1 watermarks while the PND
deadline mode is enabled, but clear out the register just in case.
This is what the other OS does, and it does make register dumps look
more consistent when we don't have partial WM1 values lingering in
the registers (some WM1 watermarks already get zeroed when the actually
used DSPFW registers get written).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add debugfs knobs for VLVCHV memory latency values
Ville Syrjälä [Wed, 24 Jun 2015 19:00:09 +0000 (22:00 +0300)]
drm/i915: Add debugfs knobs for VLVCHV memory latency values

Allow tweaking the VLV/CHV memory latencies thorugh sysfs, like we do
for ILK+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Don't do PM5/DDR DVFS with multiple pipes
Ville Syrjälä [Wed, 24 Jun 2015 19:00:08 +0000 (22:00 +0300)]
drm/i915: Don't do PM5/DDR DVFS with multiple pipes

Enabling PM5/DDR DVFS with multiple active pipes isn't a validated
configuration. It does seem to work most of the time at least, but
there is clearly an additional risk of underruns, so let's not play
with fire.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Try to make sure cxsr is disabled around plane enable/disable
Ville Syrjälä [Wed, 24 Jun 2015 19:00:07 +0000 (22:00 +0300)]
drm/i915: Try to make sure cxsr is disabled around plane enable/disable

CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control
register (enable bit at least, not quite sure about the rest). So in
order to have the plane enable/disable when we want we need to first
kick the hardware out of cxsr.

Unfortunateloy this requires some extra vblank waits. For the CxSR
enable after the plane update we should eventually use an async
vblank worker, but since we don't have that just do sync vblank
waits. For the disable case we have no choice but to do it
synchronously.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use the memory latency based WM computation on VLV too
Ville Syrjälä [Wed, 24 Jun 2015 19:00:06 +0000 (22:00 +0300)]
drm/i915: Use the memory latency based WM computation on VLV too

In order to get decnet memory self refresh residency on VLV, flip it
over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS
so it's a bit simpler.

I'm not sure the currently memory latency used for CHV is really
appropriate for VLV. Some further testing will probably be needed to
figure that out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Compute display FIFO split dynamically for CHV
Ville Syrjälä [Wed, 24 Jun 2015 19:00:05 +0000 (22:00 +0300)]
drm/i915: Compute display FIFO split dynamically for CHV

Consider which planes are active and compute the FIFO split based on the
relative data rates. Since we only consider the pipe src width rather
than the plane width when computing watermarks it seems best to do the
same when computing the FIFO split as well. This means the only thing we
actually have to consider for the FIFO splut is the bpp, and we can
ignore the rest.

I've just stuffed the logic into the watermark code for now. Eventually
it'll need to move into the atomic update for the crtc.

There's also one extra complication I've not yet considered; Some of the
DSPARB registers contain bits related to multiple pipes. The registers
are double buffered but apparently they update on the vblank of any
active pipe. So doing the FIFO reconfiguration properly when multiple
pipes are active is not going to be fun. But let's ignore that mess for
now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: CHV DDR DVFS support and another watermark rewrite
Ville Syrjälä [Wed, 24 Jun 2015 19:00:04 +0000 (22:00 +0300)]
drm/i915: CHV DDR DVFS support and another watermark rewrite

Turns out the VLV/CHV system agent doesn't understand memory
latencies, so trying to rely on the PND deadline mechanism is not
going to fly especially when DDR DVFS is enabled. Currently we try to
avoid the problems by lying to the system agent about the deadlines
and setting the FIFO watermarks to 8 cachelines. This however leads to
bad memory self refresh residency.

So in order to satosfy everyone we'll just give up on the deadline
scheme and program the watermarks old school based on the worst case
memory latency.

I've modelled this a bit on the ILK+ approach where we compute multiple
sets of watermarks for each pipe (PM2,PM5,DDR DVFS) and when merge thet
appropriate one later with the watermarks from other pipes. There isn't
too much to merge actually since each pipe has a totally independent
FIFO (well apart from the mess with the partially shared DSPARB
registers), but still decopuling the pipes from each other seems like a
good idea.

Eventually we'll want to perform the watermark update in two phases
around the plane update to avoid underruns due to the single buffered
watermark registers. But that's still in limbo for ILK+ too, so I've not
gone that far yet for VLV/CHV either.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Read wm values from hardware at init on CHV
Ville Syrjälä [Wed, 24 Jun 2015 19:00:03 +0000 (22:00 +0300)]
drm/i915: Read wm values from hardware at init on CHV

Read out the current watermark settings from the hardware at driver init
time. This will allow us to compare the newly calculated values against
the currrent ones and potentially avoid needless WM updates.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Split atomic wm update to pre and post variants
Ville Syrjälä [Wed, 24 Jun 2015 19:00:02 +0000 (22:00 +0300)]
drm/i915: Split atomic wm update to pre and post variants

Try to update the watermarks on the right side of the plane update. This
is just a temporary hack until we get the proper two part update into
place. However in the meantime this might have some chance of at least
working.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: POSTING_READ() in intel_set_memory_cxsr()
Ville Syrjälä [Wed, 24 Jun 2015 19:00:01 +0000 (22:00 +0300)]
drm/i915: POSTING_READ() in intel_set_memory_cxsr()

We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to
make sure things are really kicked off.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Unconditionally do fb tracking invalidate in set_domain
Daniel Vetter [Fri, 26 Jun 2015 17:35:16 +0000 (19:35 +0200)]
drm/i915: Unconditionally do fb tracking invalidate in set_domain

We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written this already before but must have gotten lost
unfortunately :(

v2: Chris observed that all internal set_domain users already
correctly do the fb invalidate on their own, hence we can move this
just into the set_domain ioctl instead.

v3: I screwed up setting the invalidate ORIGIN_* correctly (Chris).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reported-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix IPS related flicker
Rodrigo Vivi [Fri, 26 Jun 2015 20:55:54 +0000 (13:55 -0700)]
drm/i915: Fix IPS related flicker

We cannot let IPS enabled with no plane on the pipe:

BSpec: "IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank." and "IPS must be
disabled while there is still at least one plane enabled on the
same pipe as IPS." This restriction apply to HSW and BDW.

However a shortcut path on update primary plane function
to make primary plane invisible by setting DSPCTRL to 0
was leting IPS enabled while there was no
other plane enabled on the pipe causing flickerings that we were
believing that it was caused by that other restriction where
ips cannot be used when pixel rate is greater than 95% of cdclok.

v2: Don't mess with Atomic path as pointed out by Ville.

v3: Rebase after a long time and atomic path changes.
    Accept Ville suggestion of not check !fb

v4: Re-factore on dinq

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85583
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: Make it compile]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Skip remaining dividers when deviation is 0
Damien Lespiau [Fri, 26 Jun 2015 17:34:29 +0000 (18:34 +0100)]
drm/i915/skl: Skip remaining dividers when deviation is 0

We can't improve a 0 deviation, so when we find such a divider, skip the
remaining ones they won't be better.

This short-circuit the search for 34 of the 373 test frequencies in the
corresponding i-g-t test (tools/skl_compute_wrpll)

v2: Place the short-circuiting code in skl_compute_wrpll() (Paulo)

(I'm sure nobody will notice the spurious removal of a blank line)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update rps frequencies for BXT
Bob Paauwe [Thu, 25 Jun 2015 21:54:07 +0000 (14:54 -0700)]
drm/i915: Update rps frequencies for BXT

Broxton is using a different register and different bit ordering
for rps status capabilities.

Also GT perf freqency register is different for Broxton so update
that.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Prefer even dividers for SKL DPLLs
Damien Lespiau [Thu, 25 Jun 2015 15:19:24 +0000 (16:19 +0100)]
drm/i915/skl: Prefer even dividers for SKL DPLLs

Currently, if an odd divider improves the deviation (minimizes it), we
take that divider. The recommendation is to prefer even dividers.

v2: Move the check at the right place after having inverted the two for
    loops in the previous patch.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Replace the HDMI DPLL divider computation algorithm
Damien Lespiau [Thu, 25 Jun 2015 15:15:06 +0000 (16:15 +0100)]
drm/i915/skl: Replace the HDMI DPLL divider computation algorithm

The HW validation team came back from further testing with a slightly
changed constraint on the deviation between the DCO frequency and the
central frequency. Instead of +-4%, it's now +1%/-6%.

Unfortunately, the previous algorithm didn't quite cope with these new
constraints, the reason being that it wasn't thorough enough looking at
the possible divider candidates.

The new algorithm looks at all dividers, which is definitely a hammer
approach (we could reduce further the set of dividers to good ones as a
follow up, at the cost of a bit more complicated code). But, at least,
we can now satisfy the +1%/+6% rule for all the "Well known" HDMI
frequencies of my test set (373 entries).

On that subject, the new code is quite extensively tested in
intel-gpu-tools (tools/skl_compute_wrpll).

v2: Fix cycling between central frequencies and dividers (Paulo)
    Properly choose the minimal deviation between postive and negative
    candidates (Paulo).

    On the 373 test frequencies, v2 computes better dividers than v1 (ie
    more even dividers and lower deviation on average):

    v1: average deviation: 206.52
    v2: average deviation: 194.47

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Switch gen8_free_page_tables params
Michel Thierry [Wed, 10 Jun 2015 16:46:39 +0000 (17:46 +0100)]
drm/i915/gtt: Switch gen8_free_page_tables params

After Mika's ppgtt cleanup series, all the other free functions have
drm_device as the first parameter, except this one.

No functional changes.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/lrc: Update PDPx registers with lri commands
Michel Thierry [Fri, 26 Jun 2015 12:46:14 +0000 (13:46 +0100)]
drm/i915/lrc: Update PDPx registers with lri commands

A safer way to update the PDPx registers is sending lri commands, added
in the ring before the batchbuffer start. Otherwise, the ctx must be idle
before trying to change anything (but the ring-tail) in the ctx image. An
example where the ctx won't be idle is lite-restore.

This patch depends on 5b7e4c9ce ("drm/i915/gtt: Mark TLBS dirty for gen8+").

v2: Combine lri writes (and save 8 commands). (Mika)
v3: Rebase after ring/req changes, and removed references to deprecated patches.

Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Use nonatomic bitmap ops
Mika Kuoppala [Thu, 25 Jun 2015 15:35:19 +0000 (18:35 +0300)]
drm/i915/gtt: Use nonatomic bitmap ops

There is no need for atomicity here. Convert all bitmap
operations to nonatomic variants.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Move scratch_pd and scratch_pt into vm struct
Mika Kuoppala [Thu, 25 Jun 2015 15:35:17 +0000 (18:35 +0300)]
drm/i915/gtt: Move scratch_pd and scratch_pt into vm struct

Scratch page is part of struct i915_address_space. Move other
scratch entities into the same struct. This is a preparatory patch
for having only one instance of each scratch_pt/pd.

v2: make commit msg more readable

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com> (v1)
[danvet: Bikeshed summary to avoid confusion with vmas.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Cleanup page directory encoding
Mika Kuoppala [Thu, 25 Jun 2015 15:35:16 +0000 (18:35 +0300)]
drm/i915/gtt: Cleanup page directory encoding

Write page directory entry without using superfluous
indirect function. Also remove unused device parameter
from the encode function.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Pin vma during virtual address allocation
Mika Kuoppala [Thu, 25 Jun 2015 15:35:15 +0000 (18:35 +0300)]
drm/i915/gtt: Pin vma during virtual address allocation

Dynamic page table allocation might wake the shrinker
when memory is requested for page table structures.
As this happens when we try to allocate the virtual address
during binding, our vma might be among the targets for eviction.
We should do i915_vma_pin() and do pin early in there like Chris
suggests but this is interim solution.

Shield our vma from shrinker by incrementing pin count before
the virtual address is allocated.

The proper place to fix this would be in gem, inside of
i915_vma_pin(). But we don't have that yet so take the short
cut as a intermediate solution.

Testcase: igt/gem_ctx_thrash
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Make scratch page i915_page_dma compatible
Mika Kuoppala [Thu, 25 Jun 2015 15:35:13 +0000 (18:35 +0300)]
drm/i915/gtt: Make scratch page i915_page_dma compatible

Lay out scratch page structure in similar manner than other
paging structures. This allows us to use the same tools for
setup and teardown.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Use macros to access dma mapped pages
Mika Kuoppala [Thu, 25 Jun 2015 15:35:12 +0000 (18:35 +0300)]
drm/i915/gtt: Use macros to access dma mapped pages

Make paging structure type agnostic *_px macros to access
page dma struct, the backing page and the dma address.

This makes the code less cluttered on internals of
i915_page_dma.

v2: Superfluous const -> nonconst removed
v3: Rebased

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Introduce kmap|kunmap for dma page
Mika Kuoppala [Thu, 25 Jun 2015 15:35:11 +0000 (18:35 +0300)]
drm/i915/gtt: Introduce kmap|kunmap for dma page

As there is flushing involved when we have done the cpu
write, make functions for mapping for cpu space. Make macros
to map any type of paging structure.

v2: Make it clear tha flushing kunmap is only for ppgtt (Ville)
v3: Flushing fixed (Ville, Michel). Removed superfluous semicolon

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Introduce fill_page_dma()
Mika Kuoppala [Thu, 25 Jun 2015 15:35:10 +0000 (18:35 +0300)]
drm/i915/gtt: Introduce fill_page_dma()

When we setup page directories and tables, we point the entries
to a to the next level scratch structure. Make this generic
by introducing a fill_page_dma which maps and flushes. We also
need 32 bit variant for legacy gens.

v2: Fix flushes and handle valleyview (Ville)
v3: Now really fix flushes (Michel, Ville)

Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Remove superfluous free_pd with gen6/7
Mika Kuoppala [Thu, 25 Jun 2015 15:35:09 +0000 (18:35 +0300)]
drm/i915/gtt: Remove superfluous free_pd with gen6/7

This has slipped in somewhere but it was harmless
as we check the page pointer before teardown.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Rename unmap_and_free_px to free_px
Mika Kuoppala [Thu, 25 Jun 2015 15:35:08 +0000 (18:35 +0300)]
drm/i915/gtt: Rename unmap_and_free_px to free_px

All the paging structures are now similar and mapped for
dma. The unmapping is taken care of by common accessors, so
don't overload the reader with such details.

v2: Be consistent with goto labels (Michel)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Introduce struct i915_page_dma
Mika Kuoppala [Thu, 25 Jun 2015 15:35:07 +0000 (18:35 +0300)]
drm/i915/gtt: Introduce struct i915_page_dma

All our paging structures have struct page and dma address
for that page.

Add struct for page/dma address pairs and use it to make
the setup and teardown for different paging structures
identical.

Include the page directory offset also in the struct for legacy
gens. Rename it to clearly point out that it is offset into the
ggtt.

v2: Add comment about ggtt_offset (Michel)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Introduce i915_page_dir_dma_addr
Mika Kuoppala [Thu, 25 Jun 2015 15:35:06 +0000 (18:35 +0300)]
drm/i915/gtt: Introduce i915_page_dir_dma_addr

The legacy mode mm switch and the execlist context assignment
needs dma address for the page directories.

Introduce a function that encapsulates the scratch_pd dma
fallback if no pd is found.

v2: Rebase, s/ring/req

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Allow >= 4GB sizes for vm.
Mika Kuoppala [Thu, 25 Jun 2015 15:35:05 +0000 (18:35 +0300)]
drm/i915/gtt: Allow >= 4GB sizes for vm.

We can have exactly 4GB sized ppgtt with 32bit system.
size_t is inadequate for this.

v2: Convert a lot more places (Daniel)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Check va range against vm size
Mika Kuoppala [Thu, 25 Jun 2015 15:35:04 +0000 (18:35 +0300)]
drm/i915/gtt: Check va range against vm size

Check the allocation area against the known end
of address space instead of against fixed value.

v2: Return ENODEV on internal bugs (Chris)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gtt: Mark TLBS dirty for gen8+
Mika Kuoppala [Thu, 25 Jun 2015 15:35:03 +0000 (18:35 +0300)]
drm/i915/gtt: Mark TLBS dirty for gen8+

When we touch gen8+ page maps, mark them dirty like we
do with previous gens.

v2: Update comment (Joonas)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add debug messages for pipe enable/disable
Ville Syrjälä [Wed, 24 Jun 2015 18:59:35 +0000 (21:59 +0300)]
drm/i915: Add debug messages for pipe enable/disable

Currently we don't have any real indication when a pipe gets
enabled/disabled. Add some.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Store frontbuffer_bits in the plane
Ville Syrjälä [Wed, 24 Jun 2015 18:59:34 +0000 (21:59 +0300)]
drm/i915: Store frontbuffer_bits in the plane

Avoid some 'switch (plane->type)' by storing the fronbuffer_bits in
intel_plane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: use singular frontbuffer_bits in intel_plane since a plan can
only ever have one bit. Discussed with Ville on irc.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add the ddi get cdclk code for BXT (v3)
Bob Paauwe [Tue, 23 Jun 2015 21:14:26 +0000 (14:14 -0700)]
drm/i915: Add the ddi get cdclk code for BXT (v3)

The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause reprogramming of the hardware.

v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
v3: Make less assumptions about the hardware state (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Return correct size for rotated views
Tvrtko Ursulin [Tue, 23 Jun 2015 11:57:43 +0000 (12:57 +0100)]
drm/i915: Return correct size for rotated views

Currently object size is returned for the rotated VMA size which can be
bigger than the rotated view itself. Since the binding code pads all
excess size with scratch pages the only minor issue with this is wasting
some GGTT space, but still feels nicer to fix and report the real size.

v2: Rebase for tracking size in bytes instead of pages.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Move rotated geometry calculations into the fill helper
Tvrtko Ursulin [Tue, 23 Jun 2015 13:26:46 +0000 (14:26 +0100)]
drm/i915: Move rotated geometry calculations into the fill helper

This way data is available as soon as the view is passed into the call chain.

v2: Store size in bytes instead of pages under the appropriate name. (Chris Wilson)

v3: Use uint64_t instead of size_t. (Daniel Vetter)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove mostly unused variable in intel_rotate_fb_obj_pages
Tvrtko Ursulin [Wed, 24 Jun 2015 08:55:20 +0000 (09:55 +0100)]
drm/i915: Remove mostly unused variable in intel_rotate_fb_obj_pages

It is only used in logging and it doesn't need to exist on its own.

Also it was misleading to log view size as object size.

v2: Improve commit message. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
[danvet: s/%lu/%zu/ where needed, reported by 0-day.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Nuke lvds downclock support
Daniel Vetter [Thu, 18 Jun 2015 08:30:23 +0000 (10:30 +0200)]
drm/i915: Nuke lvds downclock support

With the new DRRS code it kinda sticks out, and we never managed to
get this to work well enough without causing issues. Time to wave
goodbye.

I've decided to keep the logic for programming the reduced clocks
intact, but everything else is gone. If anyone ever wants to resurrect
this we need to redo it all anyway on top of the frontbuffer tracking.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gen9: fix typo when setting up the crtc scaler
Imre Deak [Tue, 23 Jun 2015 17:40:27 +0000 (20:40 +0300)]
drm/i915/gen9: fix typo when setting up the crtc scaler

This typo lead to the crtc scaler getting enabled incorrectly and an
evantual state checker mismatch about the scaler_id.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround
Arun Siluvery [Tue, 23 Jun 2015 14:46:57 +0000 (15:46 +0100)]
drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround

In Indirect context w/a batch buffer,
WaClearSlmSpaceAtContextSwitch

This WA performs writes to scratch page so it must be valid, this check
is performed before initializing the batch with this WA.

v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville)

v3: GTT bit in scratch address should be mbz (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use to_i915 in intel_frontbuffer.c
Daniel Vetter [Thu, 18 Jun 2015 08:30:28 +0000 (10:30 +0200)]
drm/i915: Use to_i915 in intel_frontbuffer.c

Must have missed the transition.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915/psr: Restrict single-shot updates to the PSR pipe
Daniel Vetter [Thu, 18 Jun 2015 08:30:27 +0000 (10:30 +0200)]
drm/i915/psr: Restrict single-shot updates to the PSR pipe

The frontbuffer code gives us accurate information about activity,
let's use it. Again this should avoid unecessary updates when multiple
screens are on.

Also realign function paramaters, I couldn't resist that bit of OCD.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915/psr: Restrict buffer tracking to the PSR pipe
Daniel Vetter [Thu, 18 Jun 2015 08:30:26 +0000 (10:30 +0200)]
drm/i915/psr: Restrict buffer tracking to the PSR pipe

The current code tracks business across all pipes, but we're only
really interested in the one pipe DRRS is enabled on. Fairly tiny
optimization, but something I noticed while reading the code. But it
might matter a bit when e.g. showing a video or something only on the
external screen, while the panel is kept static.

Also regroup the code slightly: First compute new bitmasks, then take
appropriate actions.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915/drrs: Restrict buffer tracking to the DRRS pipe
Daniel Vetter [Thu, 18 Jun 2015 08:30:25 +0000 (10:30 +0200)]
drm/i915/drrs: Restrict buffer tracking to the DRRS pipe

The current code tracks business across all pipes, but we're only
really interested in the one pipe DRRS is enabled on. Fairly tiny
optimization, but something I noticed while reading the code. But it
might matter a bit when e.g. showing a video or something only on the
external screen, while the panel is kept static.

Also regroup the code slightly: First compute new bitmasks, then take
appropriate actions.

Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: s/update/compute/ for gmch dpll register functions
Daniel Vetter [Thu, 18 Jun 2015 08:30:24 +0000 (10:30 +0200)]
drm/i915: s/update/compute/ for gmch dpll register functions

I was momentarily confused until I've double-checked that these
functions really only compute state and don't update the hardware
state. They once did that, but since Ander's rework of the dpll
computation flow that's no longer the case.

Rename them to avoid further confusion.

Note that the ilk code already follows the compute_dpll naming scheme
for computing the actual register value. DDI code goes with _calc_,
but that is close enough.

Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: debugfs for frontbuffer tracking
Daniel Vetter [Thu, 18 Jun 2015 08:30:22 +0000 (10:30 +0200)]
drm/i915: debugfs for frontbuffer tracking

Useful to figure out whether stuck bits are due to the frontbuffer
tracking code as opposed to individual consumers (who have their own
bitmask tracking).

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Filter out no-op frontbuffer tracking flushes
Daniel Vetter [Thu, 18 Jun 2015 08:30:21 +0000 (10:30 +0200)]
drm/i915: Filter out no-op frontbuffer tracking flushes

Paulo noticed that the fbc frontbuffer tracking flush callback
occasionally gets a call without any bit set. This can happen when we
have to filter flush calls due to e.g. gpu rendering. Filter these
out.

Reported-by: Paulo Zanoni <przanoni@gmail.com>
Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Clear fb_tracking.busy_bits also for synchronous flips
Daniel Vetter [Thu, 18 Jun 2015 09:23:24 +0000 (11:23 +0200)]
drm/i915: Clear fb_tracking.busy_bits also for synchronous flips

The current/old frontbuffer might still have gpu frontbuffer rendering
pending. But once flipped it won't have the corresponding frontbuffer
bits any more and hence the request retire function won't ever clear
the corresponding busy bits. The async flip tracking (with the
flip_prepare and flip_complete functions) already does this, but
somehow I've forgotten to do this for synchronous flips.

Note that we don't track outstanding rendering of the new framebuffer
with busy_bits since all our plane update code waits for previous
rendering to complete before displaying a new buffer. Hence a new
buffer will never be busy.

v2: Drop the spurious inline Ville spotted.

v3: Don't touch flip_bits in the synchronsou frontbuffer_flip
function, noticed by Paulo.

v4: Remove one more inline that slipped through (Paulo).

Reported-by: Paulo Zanoni <przanoni@gmail.com>
Cc: Paulo Zanoni <przanoni@gmail.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Testcase: igt/kms_frontbuffer_tracking/fbc-modesetfrombusy
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Bail out early if WA batch is not available for given Gen
Arun Siluvery [Tue, 23 Jun 2015 14:50:44 +0000 (15:50 +0100)]
drm/i915: Bail out early if WA batch is not available for given Gen

To initialize WA batch, at the moment we first allocate batch and then check
whether we have any WA to be initialized for the given Gen; if we don't have
any WA then we WARN the user, destroy the batch and return but this is causing
another WARN in cleanup code complaining about sleeping in atomic context.
Till we understand this better and to keep things simpler, bail out early
if we don't have WA.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix warnings reported by 0-day
Arun Siluvery [Tue, 23 Jun 2015 14:50:43 +0000 (15:50 +0100)]
drm/i915: Fix warnings reported by 0-day

Kernel 0-day framework reported warnings with WA batch patches, this patch
fixes those warnings and an additional warning reported in intel_lrc.c file.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove the now obsolete 'i915_gem_check_olr()'
John Harrison [Fri, 29 May 2015 16:44:15 +0000 (17:44 +0100)]
drm/i915: Remove the now obsolete 'i915_gem_check_olr()'

As there is no OLR to check, the check_olr() function is now a no-op and can be
removed.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update a bunch of LRC functions to take requests
John Harrison [Fri, 29 May 2015 16:44:14 +0000 (17:44 +0100)]
drm/i915: Update a bunch of LRC functions to take requests

A bunch of the low level LRC functions were passing around ringbuf and ctx
pairs. In a few cases, they took the r/c pair and a request as well. This is all
quite messy and unnecesary. The context_queue() call is especially bad since the
fake request code got removed - it takes a request and three extra things that
must be extracted from the request and then it checks them against what it finds
in the request. Removing all the derivable data makes the code much simpler all
round.

This patch updates those functions to just take the request structure.

Note that logical_ring_wait_for_space now takes a request structure but already
had a local request pointer that it uses to scan for something to wait on. To
avoid confusion the local variable has been renamed 'target' (it is searching
for a target request to do something with) and the parameter has been called req
(to guarantee anything accidentally missed gets a compiler error).

v2: Updated commit message re wait_for_space (Tomas Elf review comment).

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove 'faked' request from LRC submission
John Harrison [Fri, 29 May 2015 16:44:13 +0000 (17:44 +0100)]
drm/i915: Remove 'faked' request from LRC submission

The LRC submission code requires a request for tracking purposes. It does not
actually require that request to 'complete' it simply uses it for keeping hold
of reference counts on contexts and such like.

Previously, the fall back path of polling for space in the ring would start by
submitting any outstanding work that was sat in the buffer. This submission was
not done as part of the request that that work was owned by because that would
lead to complications with the request being submitted twice. Instead, a null
request structure was passed in to the submit call and a fake one was created.

That fall back path has long since been obsoleted and has now been removed. Thus
there is never any need to fake up a request structure. This patch removes that
code. A couple of sanity check warnings are added as well, just in case.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Thomas Daniel <thomas.daniel@intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Move the request/file and request/pid association to creation time
John Harrison [Fri, 29 May 2015 16:44:12 +0000 (17:44 +0100)]
drm/i915: Move the request/file and request/pid association to creation time

In _i915_add_request(), the request is associated with a userland client.
Specifically it is linked to the 'file' structure and the current user process
is recorded. One problem here is that the current user process is not
necessarily the same as when the request was submitted to the driver. This is
especially true when the GPU scheduler arrives and decouples driver submission
from hardware submission. Note also that it is only in the case where the add
request comes from an execbuff call that there is a client to associate. Any
other add request call is kernel only so does not need to do it.

This patch moves the client association into a separate function. This is then
called from the execbuffer code path itself at a sensible time. It also removes
the now redundant 'file' pointer from the add request parameter list.

An extra cleanup of the client association is also added to the request clean up
code for the eventuality where the request is killed after association but
before being submitted (e.g. due to out of memory error somewhere). Once the
submission has happened, the request is on the request list and the regular
request list removal will clear the association. Note that this still needs to
happen at this point in time because the request might be kept floating around
much longer (due to someone holding a reference count) and the client should not
be worrying about this request after it has been retired.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove the now obsolete 'outstanding_lazy_request'
John Harrison [Fri, 29 May 2015 16:44:11 +0000 (17:44 +0100)]
drm/i915: Remove the now obsolete 'outstanding_lazy_request'

The outstanding_lazy_request is no longer used anywhere in the driver.
Everything that was looking at it now has a request explicitly passed in from on
high. Everything that was relying upon it behind the scenes is now explicitly
creating/passing/submitting its own private request. Thus the OLR can be
removed.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove the now obsolete intel_ring_get_request()
John Harrison [Fri, 29 May 2015 16:44:10 +0000 (17:44 +0100)]
drm/i915: Remove the now obsolete intel_ring_get_request()

Much of the driver has now been converted to passing requests around instead of
rings/ringbufs/contexts. Thus the function for retreiving the request from a
ring (i.e. the OLR) is no longer used and can be removed.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add *_ring_begin() to request allocation
John Harrison [Fri, 29 May 2015 16:44:09 +0000 (17:44 +0100)]
drm/i915: Add *_ring_begin() to request allocation

Now that the *_ring_begin() functions no longer call the request allocation
code, it is finally safe for the request allocation code to call *_ring_begin().
This is important to guarantee that the space reserved for the subsequent
i915_add_request() call does actually get reserved.

v2: Renamed functions according to review feedback (Tomas Elf).

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update intel_logical_ring_begin() to take a request structure
John Harrison [Fri, 29 May 2015 16:44:08 +0000 (17:44 +0100)]
drm/i915: Update intel_logical_ring_begin() to take a request structure

Now that everything above has been converted to use requests,
intel_logical_ring_begin() can be updated to take a request instead of a
ringbuf/context pair. This also means that it no longer needs to lazily allocate
a request if no-one happens to have done it earlier.

Note that this change makes the execlist signature the same as the legacy
version. Thus the two functions could be merged into a ring->begin() wrapper if
required.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update intel_ring_begin() to take a request structure
John Harrison [Fri, 29 May 2015 16:44:07 +0000 (17:44 +0100)]
drm/i915: Update intel_ring_begin() to take a request structure

Now that everything above has been converted to use requests, intel_ring_begin()
can be updated to take a request instead of a ring. This also means that it no
longer needs to lazily allocate a request if no-one happens to have done it
earlier.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update cacheline_align() to take a request structure
John Harrison [Fri, 29 May 2015 16:44:06 +0000 (17:44 +0100)]
drm/i915: Update cacheline_align() to take a request structure

Updated intel_ring_cacheline_align() to take a request instead of a ring.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update ring->signal() to take a request structure
John Harrison [Fri, 29 May 2015 16:44:05 +0000 (17:44 +0100)]
drm/i915: Update ring->signal() to take a request structure

Updated the various ring->signal() implementations to take a request instead of
a ring. This removes their reliance on the OLR to obtain the seqno value that
should be used for the signal.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update ring->sync_to() to take a request structure
John Harrison [Fri, 29 May 2015 16:44:04 +0000 (17:44 +0100)]
drm/i915: Update ring->sync_to() to take a request structure

Updated the ring->sync_to() implementations to take a request instead of a ring.
Also updated the tracer to include the request id.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
[danvet: Rebase since I didn't merge the patch which added ->uniq.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>