Mika Westerberg [Fri, 18 Aug 2017 10:05:55 +0000 (13:05 +0300)]
pinctrl: intel: Add Intel Lewisburg GPIO support
Intel Lewisburg has the same GPIO hardware than Intel Sunrisepoint-H
except few differences in register offsets and pin lists. Because of
this we add a separate pinctrl driver for Lewisburg.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Fri, 18 Aug 2017 10:05:54 +0000 (13:05 +0300)]
pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support
This is desktop version Intel Cannon Lake PCH. The GPIO hardware is the
same but pin list differs a bit. Add support for this to the existing
Cannon Lake pin controller driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 22 Aug 2017 13:32:28 +0000 (15:32 +0200)]
Merge tag 'sh-pfc-for-v4.14-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.14
- Propagate errors on group config, now r8a7740-armadillo800eva.dts is
fixed,
- Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0,
- Add USB2.0 and USB3.0 pin groups on R-Car M3-W,
- Add a missing MMC pin group on R-Car M2-W and RZ/G1M,
- Add initial support for R-Car D3,
- Small fixes and cleanups.
Yong Li [Tue, 15 Aug 2017 16:21:50 +0000 (00:21 +0800)]
pinctrl: aspeed: Fix ast2500 strap register write logic
On AST2500, the hardware strap register(SCU70) only accepts write ‘1’,
to clear it to ‘0’, must set bits(write ‘1’) to SCU7C
Signed-off-by: Yong Li <sdliyong@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Icenowy Zheng [Fri, 11 Aug 2017 14:27:34 +0000 (22:27 +0800)]
pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl
The pin controller of Allwinner H5 has three IRQ banks, however in old
versions of drivers and device trees, only two are set, which makes
PG bank IRQ not available.
If it's directly set to 3, the old device trees will fail to boot.
Add a workaround (and a warning) for older device trees, and allow new
device trees to use correct 3 IRQ banks.
Fixes:
838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rushikesh S Kadam [Fri, 11 Aug 2017 08:23:44 +0000 (13:53 +0530)]
pinctrl: intel: Disable GPIO pin interrupts in suspend
The fix prevents unintended wakes from second level GPIO pin interrupts.
On some Intel Kabylake platforms, it is observed that GPIO pin interrupts
can wake the platform from suspend-to-idle, even though the IRQ is not
configured as IRQF_NO_SUSPEND or enable_irq_wake().
This can cause undesired wakes on Mobile devices such as Laptops and
Chromebook devices. For example a headset jack insertion is not a desired
wake source on Chromebook devices.
The pinctrl-intel (GPIO controller) driver implements a "Shared IRQ" model.
All GPIO pin interrupts are OR'ed and mapped to a first level IRQ14 (or
IRQ15). The driver registers an irq_chip struct and maps an irq_domain for
the GPIO pin interrupts. The IRQ14 handler demuxes and calls the second
level IRQ for the respective pin.
In the suspend entry flow, at suspend_noirq stage, the kernel disables IRQs
that are not marked for wake. The pinctrl-intel driver does not implement a
irq_disable() callback (to take advantage of lazy disabling). The
pinctrl-intel GPIO interrupts are not disabled in hardware during suspend
entry, and thus are able to wake the SoC out of suspend-to-idle.
This patch sets the IRQCHIP_MASK_ON_SUSPEND flag for the GPIO irq_chip, to
disable the second level interrupts at suspend_noirq stage via the irq_mask
callbacks. The irq_mask callback disables the IRQs in hardware by
programming the corresponding GPIO pad registers. Only IRQs that are not
marked for wake are disabled.
Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-and-tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:29 +0000 (12:06 +0200)]
pinctrl: vt8500: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:28 +0000 (12:06 +0200)]
pinctrl: ti-iodelay: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops and pctlops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:27 +0000 (12:06 +0200)]
pinctrl: tz1090: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:26 +0000 (12:06 +0200)]
pinctrl: tz1090-pdc: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:25 +0000 (12:06 +0200)]
pinctrl: tb10x: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:24 +0000 (12:06 +0200)]
pinctrl: rza1: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinmux_ops structure is only stored in the const pmxops field
of a pinctrl_desc structure. Make the pinmux_ops structure const as
well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:23 +0000 (12:06 +0200)]
pinctrl: ingenic: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:22 +0000 (12:06 +0200)]
pinctrl: adi2: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:21 +0000 (12:06 +0200)]
pinctrl: aspeed: g5: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:20 +0000 (12:06 +0200)]
pinctrl: aspeed: g4: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:19 +0000 (12:06 +0200)]
pinctrl: digicolor: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:18 +0000 (12:06 +0200)]
pinctrl: sirf: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (pctlops and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:17 +0000 (12:06 +0200)]
pinctrl: sirf: atlas7: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinmux_ops structure is only stored in the const pmxops field
of a pinctrl_desc structure. Make the pinmux_ops structure const as
well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:16 +0000 (12:06 +0200)]
pinctrl: st: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
These structures are only stored in fields of a pinctrl_desc
structure (confops, pctlops, and pmxops) that are const. Make the
structures const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:15 +0000 (12:06 +0200)]
pinctrl: armada-37xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinconf_ops structure is only stored in the const pinconf_ops
field of a pinctrl_desc structure. Make the pinconf_ops structure
const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:14 +0000 (12:06 +0200)]
pinctrl: artpec6: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinctrl_ops structure is only stored in the const pctlops
field of a pinctrl_desc structure. Make the pinctrl_ops structure
const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Lars Persson <lars.persson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Julia Lawall [Thu, 10 Aug 2017 10:06:13 +0000 (12:06 +0200)]
pinctrl: bcm281xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures
This pinconf_ops structure is only stored in the const confops
field of a pinctrl_desc structure. Make the pinconf_ops structure
const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Katsuhiro Suzuki [Wed, 9 Aug 2017 13:16:14 +0000 (22:16 +0900)]
pinctrl: uniphier: add Audio out pin-mux settings
The UniPhier LD11/20 SoC audio core use following 8 pins:
AO1IEC, AO1ARC, AO1DACCK, AO1BCK, AO1LRCK, AO1D[0-2]
Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Wed, 9 Aug 2017 16:09:33 +0000 (11:09 -0500)]
pinctrl: amd: fix error return code in amd_gpio_probe()
platform_get_irq() returns an error code, but the pinctrl-amd driver
ignores it and always returns -EINVAL. This is not correct and,
prevents -EPROBE_DEFER from being propagated properly.
Print and propagate the return value of platform_get_irq on failure.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 15 Jul 2017 17:50:54 +0000 (19:50 +0200)]
MAINTAINERS: Update the Gemini maintainer list
This patch:
- Adds myself as comaintainer for the Gemini.
- Adds the Gemini main bindings to the file list.
- Adds the pin controller plus bindings to the Gemini
file list.
- Fixes up the path of the RTC binding and driver.
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Takeshi Kihara [Wed, 9 Aug 2017 12:19:47 +0000 (21:19 +0900)]
pinctrl: sh-pfc: r8a77995: Add voltage switch operations for MMC
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Wed, 9 Aug 2017 12:19:46 +0000 (21:19 +0900)]
pinctrl: sh-pfc: r8a77995: Add MMC pins, groups and functions
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Wed, 9 Aug 2017 12:19:43 +0000 (21:19 +0900)]
pinctrl: sh-pfc: r8a77995: Add I2C pins, groups and functions
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Wed, 9 Aug 2017 12:19:42 +0000 (21:19 +0900)]
pinctrl: sh-pfc: r8a77995: Add SCIF pins, groups and functions
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77995
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[geert: Fix swapped RX3_B and SCK3_B pins]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Wed, 9 Aug 2017 12:19:41 +0000 (21:19 +0900)]
pinctrl: sh-pfc: Initial R8A77995 PFC support
This patch adds initial pinctrl driver to support for the R8A77995 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[geert: whitespace]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Wed, 9 Aug 2017 12:19:40 +0000 (21:19 +0900)]
pinctrl: sh-pfc: Add PORT_GP_{10,2[01]} helper macros
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77995 SoC.
Extracted from the initial r8a77995 patch in the BSP by Takeshi Kihara.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Wed, 2 Aug 2017 12:51:10 +0000 (21:51 +0900)]
pinctrl: sh-pfc: r8a7796: Add USB3.0 host pins, groups and functions
This patch adds USB30 (USB3.0 host) pin, group and function to R8A7796
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Wed, 2 Aug 2017 12:51:09 +0000 (21:51 +0900)]
pinctrl: sh-pfc: r8a7796: Add USB2.0 host pins, groups and functions
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to
R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:21 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix to reserved MOD_SEL2 bit22
This is a correction because MOD_SEL register specification for R8A7795
ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:20 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Rename CS1# pin function definitions
This patch renames the pin function macro definitions of the GPSR1 and
IPSR4 registers value for the CS1# pin.
This is a correction because GPSR and IPSR register specification for
R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual
Rev.0.54E.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:19 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions
This patch fixes the macro definitions of FSCLKST pins function and IPSR7
bit[15:12] register deleted.
This is a correction because IPSR register specification for R8A7795
ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or
later.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:18 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for TCLK{1,2}_{A,B} pins group
This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is
selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected
for IPSR17 bit[27:24]. And renames MOD_SEL2 bit26 value definition name
to SEL_TIMER_TMU1.
This is a correction because MOD_SEL register specification for R8A7795
ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:17 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin function definitions
This patch fixes the implementation incorrect of IPSR register value
definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function.
This is a correction to the incorrect implementation of IPSR register pin
assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car
Gen3 Hardware User's Manual Rev.0.53E.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:16 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function definitions
This patch fixes the implementation incorrect of IPSR register value
definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function.
This is a correction to the incorrect implementation of IPSR register pin
assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car
Gen3 Hardware User's Manual Rev.0.53E.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:15 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1 bit10
This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1
bit11 to MOD_SEL1 bit10.
This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.53E or later.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:14 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A
This patch fixes the implementation incorrect of MOD_SEL2 bit26 value
when SCK5_A pin function is selected for IPSR16 bit[31:28].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 ES2.0 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes:
b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Takeshi Kihara [Fri, 28 Jul 2017 11:41:13 +0000 (20:41 +0900)]
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes:
0b0ffc96dbe30fa9 ("pinctrl: sh-pfc: Initial R8A7795 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Wed, 26 Jul 2017 11:28:11 +0000 (20:28 +0900)]
pinctrl: sh-pfc: r8a7795: Add USB 2.0 pins, groups and functions
Add pins, groups, and functions for USB 2.0 on R-Car H3 ES2.0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yoshihiro Shimoda [Wed, 26 Jul 2017 11:28:10 +0000 (20:28 +0900)]
pinctrl: sh-pfc: r8a7795: Change USB3_{OVC,PWEN} definitions
Since the latest datasheet revises the names, this patch changes
the definitions from USB3_{OVC,PWEN} to USB2_CH3_{OVC,PWEN}.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fenglin Wu [Tue, 15 Aug 2017 00:38:38 +0000 (08:38 +0800)]
pinctrl: qcom: spmi-gpio: Add dtest route for digital input
Add property "qcom,dtest-buffer" to specify which dtest rail to feed
when the pin is configured as a digital input.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fenglin Wu [Tue, 15 Aug 2017 00:38:37 +0000 (08:38 +0800)]
pinctrl: qcom: spmi-gpio: Add support for GPIO LV/MV subtype
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 14 Aug 2017 14:55:01 +0000 (16:55 +0200)]
Merge tag 'samsung-pinctrl-4.14' of git://git./linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl driver changes for v4.14:
1. Fix NULL pointer dereference on S3C24XX. This was reported some time ago and
unfortunately it took few releases to fix.
2. Fix invalid register offset used for external interrupts on Exynos5433.
This was caused by the same commit as above, although on different path.
3. Consolidate between drivers and bindings the defines for pin mux functions.
4. Minor code improvements.
Linus Walleij [Sat, 5 Aug 2017 21:04:08 +0000 (23:04 +0200)]
pinctrl: add a Gemini SoC pin controller
This adds a pin control (only multiplexing) driver for the Gemini
SoC so we can sort out this complex platform in an orderly manner.
This driver will detect the chip/package version as SL3512 or SL3516
(also known as CS3512 and CS3516 etc) and register the apropriate
pin set.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 02:59:32 +0000 (11:59 +0900)]
pinctrl: check ops->pin_config_set in pinconf_set_config()
pinconf_set_config() is called by pinctrl_gpio_set_config().
If a GPIO driver is backed by a pinctrl driver and it does not
support .pin_config_set() hook, it causes NULL pointer dereference.
Fixes:
15381bc7c7f5 ("pinctrl: Allow configuration of pins from gpiolib based drivers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Thu, 3 Aug 2017 16:36:02 +0000 (19:36 +0300)]
pinctrl: intel: Add Intel Denverton pin controller support
This driver adds pinctrl/GPIO support for Intel Denverton SoC. The GPIO
controller is based on the same hardware design that is already used in
Intel Sunrisepoint so we leverage the core driver here.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 04:52:05 +0000 (13:52 +0900)]
pinctrl: add __rcu annotations to fix sparse warnings
Sparse reports "warning: incorrect type in assignment (different
address spaces)".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 04:49:47 +0000 (13:49 +0900)]
pinctrl: nomadik: fix incorrect type in return expression
Sparse reports "warning: incorrect type in return expression (different
address spaces)" because nmk_gpio_populate_chip() is supposed to return
(struct nmk_gpio_chip *) whereas devm_ioremap_resource() returns
(void __iomem *). ERR_CAST() is needed to fix the warning.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 04:47:37 +0000 (13:47 +0900)]
pinctrl: sirf: add static to local data
Detected by sparse.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 04:47:00 +0000 (13:47 +0900)]
pinctrl: armada-37xx: add static to local data
Detected by sparse.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 04:01:25 +0000 (13:01 +0900)]
pinctrl: uniphier: widen all pinconf-derived arguments to u32
Since commit
58957d2edfa1 ("pinctrl: Widen the generic pinconf argument
from 16 to 24 bits"), the generic pinconf arguments are handled by u32.
UniPhier pinctrl drivers do not support debouncing, so u16 is working,
but align the argument type to u32 for consistency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Icenowy Zheng [Tue, 1 Aug 2017 14:54:16 +0000 (22:54 +0800)]
pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not worked around when
developing the driver, which makes IRQ not working.
Fix the IRQ bank base.
Fixes:
56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Fri, 4 Aug 2017 02:22:31 +0000 (11:22 +0900)]
pinctrl: move const qualifier before struct
Update subsystem wide for consistency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Zhiyong Tao [Mon, 31 Jul 2017 08:22:11 +0000 (16:22 +0800)]
dt-bindings: pinctrl: mt2712: add binding document
The commit adds mt2712 compatible node in binding document.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sergei Shtylyov [Sat, 29 Jul 2017 18:07:07 +0000 (21:07 +0300)]
pinctrl-st: fix of_irq_to_resource() result check
of_irq_to_resource() has recently been fixed to return negative error #'s
along with 0 in case of failure, however the ST driver still only regards
0 as failure indication -- fix it up.
Fixes:
7a4228bbff76 ("of: irq: use of_irq_get() in of_irq_to_resource()")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 31 Jul 2017 21:30:50 +0000 (23:30 +0200)]
pinctrl: Add DT bindings for Cortina Gemini
The Cortina Gemini pin controller uses the standard pin control
bindings for muxing functions with groups so these bindings
should be entirely uncontroversial.
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Yan [Mon, 31 Jul 2017 10:10:22 +0000 (18:10 +0800)]
pinctrl: rockchip: add input schmitt support for rv1108
Some pins like i2c SCL/SDA need the schmitt input function
to avoid crosstalk problems.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Peter Robinson [Tue, 4 Jul 2017 06:49:47 +0000 (07:49 +0100)]
pinctrl: intel: wrap Intel pin control drivers in an architecture check
The Intel pin control drivers are architecture specific so add an if arch
to check for X86 or compile test to ensure continued test coverage.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sergei Shtylyov [Sun, 30 Jul 2017 19:38:48 +0000 (22:38 +0300)]
pinctrl: sirf: atlas7: fix of_irq_get() error check
of_irq_get() may return any negative error number as well as 0 on failure,
while the driver only checks for -EPROBE_DEFER, blithely continuing with
the call to gpiochip_set_chained_irqchip() -- that function expects the
parent IRQ as *unsigned int*, so would probably do nothing when a large
IRQ number resulting from a conversion of a negative error number is passed
to it, however passing 0 would probably work but the driver won't receive
valid GPIO bank interrupts.
Check for 'ret <= 0' instead and return -ENXIO from the driver's probe iff
of_irq_get() returned 0.
Fixes:
f9367793293d ("pinctrl: sirf: add sirf atlas7 pinctrl and gpio support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Vivek Gautam [Fri, 28 Jul 2017 13:18:12 +0000 (18:48 +0530)]
pinctrl: Add pmi8994 gpio bindings
Update the binding doc for qcom pmi8994-gpio devices.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 21 Jul 2017 06:27:15 +0000 (14:27 +0800)]
pinctrl: rockchip: Add rk3128 pinctrl support
There are 3 IP blocks pin routes need to be switched, that are
emmc-cmd, spi, i2s. And there are some pins need to be recalced,
which are gpio2c4~gpio2c7 and gpio2d0.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
David Wu [Fri, 21 Jul 2017 06:27:14 +0000 (14:27 +0800)]
pinctrl: rockchip: Use common interface for recalced iomux
The other Socs also need the feature of recalced iomux, so
make it as a common interface like iomux route feature.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thierry Reding [Thu, 20 Jul 2017 16:59:12 +0000 (18:59 +0200)]
pinctrl: bcm2835: Remove unneeded irq_group field
The irq_group field stores a 1:1 mapping. Use the loop variable to
derive the values instead of storing them in an extra array.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thierry Reding [Thu, 20 Jul 2017 17:01:07 +0000 (19:01 +0200)]
pinctrl: sirf: atlas7: Initialize GPIO offset
The GPIO offset is never initialized, which means that it will end up
being zero as per the devm_kzalloc() of the parent structure.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rob Herring [Tue, 18 Jul 2017 21:43:23 +0000 (16:43 -0500)]
pinctrl: Convert to using %pOF instead of full_name
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Barry Song <baohua@kernel.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: kernel@stlinux.com
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Philipp Zabel [Wed, 19 Jul 2017 15:26:12 +0000 (17:26 +0200)]
pinctrl: tegra: explicitly request exclusive reset control
Commit
a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.
No functional changes.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Philipp Zabel [Wed, 19 Jul 2017 15:26:11 +0000 (17:26 +0200)]
pinctrl: sunxi: explicitly request exclusive reset control
Commit
a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.
No functional changes.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Philipp Zabel [Wed, 19 Jul 2017 15:26:10 +0000 (17:26 +0200)]
pinctrl: stm32: explicitly request exclusive reset control
Commit
a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.
No functional changes.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andrew Jeffery [Tue, 18 Jul 2017 05:24:53 +0000 (14:54 +0930)]
pinctrl: aspeed: g5: Add USB device and host support
Implement the AST2500 USB functions as described by the devicetree
bindings. The AST2500 exposes five USB controllers through two USB
ports. Similar to the AST2400, the pins exposing USB are outliers with
respect to the rest of the pinmux as they not capable of GPIO.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andrew Jeffery [Tue, 18 Jul 2017 05:24:52 +0000 (14:54 +0930)]
pinctrl: aspeed: g4: Add USB device and host support
Implement the AST2400 USB functions as described by the devicetree
bindings. Three ports are fully documented in the datasheet and exposed
through the bindings and pinctrl, though there are remnants of
documentation for a fourth port muxed with GPIO pins GPIOQ6 and GPIOQ7.
The implementation is updated to reflect this but the function and
group are not exposed.
Disregarding the mostly undocumented fourth port, the USB functions are
an outlier with respect to the rest of the muxed functionality on the
AST2400 as GPIO is not supported on these pins.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andrew Jeffery [Tue, 18 Jul 2017 05:24:51 +0000 (14:54 +0930)]
dt-bindings: pinctrl: aspeed: Add g5 USB functions
The Aspeed AST2500 SoC contains a number of USB controllers:
* USB 1.1 Host Controller
* USB 2.0 Host Controller (x2)
* USB 2.0 Virtual Hub
* USB 2.0 Device Controller
* USB 1.1 HID Controller
The controllers are exposed via two USB ports with functionality muxed
as required. The following table illustrates the relationships between
the ports and the controllers via the mux function names:
Port | USB Version | USB Mode | Mux Function
------|--------------|--------------|-------------
A | 2.0 | Virtual Hub | USB2AD
A | 2.0 | Host | USB2AH
B | 1.1 | HID | USB11BHID
B | 2.0 | Device | USB2BD
B | 2.0 | Host | USB2BH
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andrew Jeffery [Tue, 18 Jul 2017 05:24:50 +0000 (14:54 +0930)]
dt-bindings: pinctrl: aspeed: Add g4 USB functions
The AST2400 contains several USB controllers:
* USB 1.1 Host Controller
* USB 2.0 Host Controller
* USB 2.0 Virtual Hub
* USB 1.1 HID Controller
Pins for three ports are routed to the three controllers such that:
* Port 1 is a dedicated USB 1.1 host port
* Port 2 is shared between the USB 1.1 host and HID controllers
* Port 3 is shared between the USB 2.0 host and Hub controllers
As the pins for port 1 are fixed function there is no associated mux
function or group described in the bindings. Ports 2 and 3 are muxed as
above, and the table below describes the mapping between pinmux function
names and ports:
Port | USB Version | USB Mode | Mux Function
------|--------------|-----------|-------------
1 | 1.1 | Host | -
2 | 1.1 | Host | USB11H2
2 | 1.1 | HID | USB11D1
3 | 2.0 | Host | USB2H1
3 | 2.0 | Device | USB2D1
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Shawn Guo [Sun, 16 Jul 2017 13:33:28 +0000 (21:33 +0800)]
pinctrl: zte: fix 'functions' allocation in zx_pinctrl_build_state()
It fixes the following Smatch static check warning:
drivers/pinctrl/zte/pinctrl-zx.c:338 zx_pinctrl_build_state()
warn: passing devm_ allocated variable to kfree.
As we will be calling krealloc() on pointer 'functions', which means
kfree() will be called in there, devm_kzalloc() shouldn't be used with
the allocation in the first place. Fix the warning by calling kcalloc()
and managing the free procedure in error path on our own.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes:
cbff0c4d27f4 ("pinctrl: add ZTE ZX pinctrl driver support")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 21:18:36 +0000 (16:18 -0500)]
pinctrl: qcom: ssbi: mpp: constify gpio_chip structure
This structure is only used to copy into another structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
15136 5112 0 20248 4f18 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.o
after:
bss dec hex filename
14849 5024 0 19873 4da1 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 18:03:39 +0000 (13:03 -0500)]
pinctrl: bcm2835: constify gpio_chip structure
This structure is only used to copy into other structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
18958 9000 128 28086 6db6 drivers/pinctrl/bcm/pinctrl-bcm2835.o
after:
text data bss dec hex filename
18764 8912 128 27804 6c9c drivers/pinctrl/bcm/pinctrl-bcm2835.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nava kishore Manne [Thu, 13 Jul 2017 09:12:43 +0000 (11:12 +0200)]
pinctrl: zynq: Fix warnings in the driver
This patch fixes the below warning
--> Prefer 'unsigned int' to bare use of 'unsigned'.
--> line over 80 characters.
--> Prefer 'unsigned int **' to bare use of 'unsigned **'.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nava kishore Manne [Thu, 13 Jul 2017 09:12:42 +0000 (11:12 +0200)]
pinctrl: zynq: Fix kernel doc warnings
This patch fixes the kernel doc warnings in the driver.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 18:15:19 +0000 (13:15 -0500)]
pinctrl: st: constify gpio_chip structure
This structure is only used to copy into other structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
21671 3632 128 25431 6357 drivers/pinctrl/pinctrl-st.o
after:
text data bss dec hex filename
21366 3576 128 25070 61ee drivers/pinctrl/pinctrl-st.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Hans de Goede [Wed, 12 Jul 2017 12:31:01 +0000 (14:31 +0200)]
pinctrl: baytrail: Do not call WARN_ON for a firmware bug
WARN_ON causes a backtrace to get logged which is only useful for
kernel bugs. For signalling a firmware bug dev_warn(dev, FW_BUG "...")
should be used.
This fixes users running userspace software to monitor kernel oopses
getting a false positive bug-report every boot because of the wrong
use of WARN_ON.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Tue, 25 Jul 2017 13:41:56 +0000 (21:41 +0800)]
pinctrl: pinctrl-imx7ulp: add gpio_set_direction support
Add gpio_set_direction support. This makes the driver support
GPIO input/output dynamically change from userspace.
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Tue, 25 Jul 2017 13:41:55 +0000 (21:41 +0800)]
pinctrl: imx: make imx_pmx_ops.gpio_set_direction platform specific callbacks
Various IMX platforms may have different imx_pmx_ops.gpio_set_direction
implementations, so let's make it platform specific callbacks instead of
the fixed common one.
Currently only VF610 platform implements it. No function level changes.
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Tue, 25 Jul 2017 13:41:54 +0000 (21:41 +0800)]
pinctrl: imx: remove gpio_request_enable and gpio_disable_free
gpio_request_enable/disable_free actually are not quite necessary as
standard IMX pinctrl binding already sets GPIO mux from device tree,
e.g. VF610_PAD_PTB20__GPIO_42 or MX7D_PAD_SD2_CD_B__GPIO5_IO9
No need to do it again in gpio_request_enable.
And according to Stefan:
"For all GPIO I checked in upstream device trees we assign a pinctrl
to the same node, so in all cases gpio_request_enable/disable is really
unnecessary."
So it should be safe to simply remove it.
Note that this changes semantics for Vybrid, e.g.
"The two functions have been introduced for Vybrid (through
SHARE_MUX_CONF_REG) and mux pins as GPIOs automatically when a GPIO
gets requested. The automatic mux is optional by the pinmux/gpio
subsystem semantics, and other NXP devices do not use it, instead an
explicit pinctrl node is added in the device tree to mux GPIOs where
required. Hence this change aligns Vybrid to other NXP (i.MX) devices.
Note that all upstream device tree assign proper pinctrl properties
where GPIOs are used so no change is necessary for device trees."
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Tue, 25 Jul 2017 13:41:53 +0000 (21:41 +0800)]
pinctrl: imx: add imx7ulp driver
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports,
IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.
This patch adds the IOMUXC1 support for A7.
It only supports generic pin config.
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Tue, 25 Jul 2017 13:41:52 +0000 (21:41 +0800)]
pinctrl: imx: switch to use the generic pinmux property
The generic pinmux property seems to be more suitable for IMX.
So we change to use 'pinmux' instead of 'pins'.
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dong Aisheng [Tue, 25 Jul 2017 13:41:51 +0000 (21:41 +0800)]
dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports,
IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface.
This patch adds the IOMUXC1 support for A7.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 31 Jul 2017 06:21:11 +0000 (15:21 +0900)]
pinctrl: uniphier: add UniPhier PXs3 pinctrl driver
Add pin configuration and pinmux support for UniPhier PXs3 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 31 Jul 2017 06:21:10 +0000 (15:21 +0900)]
pinctrl: uniphier: add suspend / resume support
Save registers lost in the sleep when suspending, and restore them
when resuming.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 31 Jul 2017 06:21:09 +0000 (15:21 +0900)]
pinctrl: uniphier: omit redundant input enable bit information
For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit
number matches its pin number. So, this is redundant information.
Instead, we just need a flag to know if the iectrl gating exists or not.
With this refactoring, 5 bits in pin data will be saved.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 31 Jul 2017 06:21:08 +0000 (15:21 +0900)]
pinctrl: uniphier: clean up GPIO port muxing
There are a bunch of GPIO muxing data, but most of them are actually
unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges"
DT properties.
Tables that contain a set of GPIO pins are still needed for the named
mapping by "gpio-ranges-group-names". This is a much cleaner way for
UniPhier SoC family where GPIO numbers are not straight mapped to pin
numbers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 31 Jul 2017 06:21:07 +0000 (15:21 +0900)]
pinctrl: uniphier: fix pin_config_get() for input-enable
For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers. So, the register offset must be
taken into account. Otherwise, wrong input-enable status is displayed.
While we here, rename the macro because it is a base address.
Fixes:
aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Masahiro Yamada [Mon, 31 Jul 2017 06:21:06 +0000 (15:21 +0900)]
pinctrl: uniphier: remove unneeded EXPORT_SYMBOL_GPL()
All UniPhier pinctrl drivers are built-in. Exporting the symbol
is meaningless.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 18:34:14 +0000 (13:34 -0500)]
pinctrl: qcom: msm: constify gpio_chip structure
This structure is only used to copy into other structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
13129 2808 192 16129 3f01 drivers/pinctrl/qcom/pinctrl-msm.o
after:
text data bss dec hex filename
12839 2720 192 15751 3d87 drivers/pinctrl/qcom/pinctrl-msm.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 18:39:50 +0000 (13:39 -0500)]
pinctrl: qcom: ssbi-gpio: constify gpio_chip structure
This structure is only used to copy into other structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
17061 6992 0 24053 5df5 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o
after:
text data bss dec hex filename
16777 6904 0 23681 5c81 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 21:35:19 +0000 (16:35 -0500)]
pinctrl: coh901: constify gpio_chip structure
This structure is only used to copy into another structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
12775 3696 64 16535 4097 drivers/pinctrl/pinctrl-coh901.o
after:
bss dec hex filename
12440 3640 64 16144 3f10 drivers/pinctrl/pinctrl-coh901.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Gustavo A. R. Silva [Tue, 11 Jul 2017 21:29:29 +0000 (16:29 -0500)]
pinctrl: nomadik: abx500: constify gpio_chip structure
This structure is only used to copy into another structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
17545 5376 0 22921 5989 drivers/pinctrl/nomadik/pinctrl-abx500.o
after:
bss dec hex filename
17273 5320 0 22593 5841 drivers/pinctrl/nomadik/pinctrl-abx500.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / log