GitHub/moto-9609/android_kernel_motorola_exynos9610.git
8 years agopowerpc/mm: Compile out radix related functions if RADIX_MMU is disabled
Aneesh Kumar K.V [Wed, 13 Jul 2016 09:35:23 +0000 (15:05 +0530)]
powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled

Currently we depend on mmu_has_feature to evalute to zero based on
MMU_FTRS_POSSIBLE mask. In a later patch, we want to update
radix_enabled() to runtime update the conditional operation to a jump
instruction. This implies we cannot depend on MMU_FTRS_POSSIBLE mask.
Instead define radix_enabled to return 0 if RADIX_MMU is not enabled.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/mm: use _raw variant of page table accessors
Aneesh Kumar K.V [Wed, 13 Jul 2016 09:35:22 +0000 (15:05 +0530)]
powerpc/mm: use _raw variant of page table accessors

This switch few of the page table accessor to use the __raw variant
and does the cpu to big endian conversion of constants. This helps in
generating better code.

For ex: a pgd_none(pgd) check with and without fix is listed below

Without fix:
------------
   2240: 20 00 61 eb  ld      r27,32(r1)
/* PGD level */
typedef struct { __be64 pgd; } pgd_t;
static inline unsigned long pgd_val(pgd_t x)
{
return be64_to_cpu(x.pgd);

    2244: 22 00 66 78  rldicl  r6,r3,32,32
    2248: 3e 40 7d 54  rotlwi  r29,r3,8
    224c: 0e c0 7d 50  rlwimi  r29,r3,24,0,7
    2250: 3e 40 c5 54  rotlwi  r5,r6,8
    2254: 2e c4 7d 50  rlwimi  r29,r3,24,16,23
    2258: 0e c0 c5 50  rlwimi  r5,r6,24,0,7
    225c: 2e c4 c5 50  rlwimi  r5,r6,24,16,23
    2260: c6 07 bd 7b  rldicr  r29,r29,32,31
    2264: 78 2b bd 7f  or      r29,r29,r5
if (pgd_none(pgd))
    2268: 00 00 bd 2f  cmpdi   cr7,r29,0
    226c: 54 03 9e 41  beq     cr7,25c0 <__get_user_pages_fast+0x500>

With fix:
---------
    2370: 20 00 61 eb  ld      r27,32(r1)
if (pgd_none(pgd))
    2374: 00 00 bd 2f  cmpdi   cr7,r29,0
    2378: a8 03 9e 41  beq     cr7,2720 <__get_user_pages_fast+0x530>
break;
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/mm/radix: Update LPCR HR bit as per ISA
Aneesh Kumar K.V [Wed, 13 Jul 2016 09:35:21 +0000 (15:05 +0530)]
powerpc/mm/radix: Update LPCR HR bit as per ISA

PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it up appropriately

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/mm: Fix .long's in tlb-radix.c to more meaningful
Balbir Singh [Wed, 13 Jul 2016 09:35:20 +0000 (15:05 +0530)]
powerpc/mm: Fix .long's in tlb-radix.c to more meaningful

The .longs with the shifts are harder to read, use more meaningful names
for the opcodes. PPC_TLBIE_5 is introduced for the 5 opcode variation of
the instruction due to an existing op-code for the 2 opcode variant.

Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pci: Don't try to allocate resources that will be reassigned
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:18 +0000 (16:37 +1000)]
powerpc/pci: Don't try to allocate resources that will be reassigned

When we know we will reassign all resources, trying (and failing)
to allocate them initially is fairly pointless and leads to a lot
of scary messages in the kernel log

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv/pci: Check status of a PHB before using it
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:17 +0000 (16:37 +1000)]
powerpc/powernv/pci: Check status of a PHB before using it

If the firmware encounters an error (internal or HW) during initialization
of a PHB, it might leave the device-node in the tree but mark it disabled
using the "status" property. We should check it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv/pci: Use the device-tree to get available range of M64's
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:16 +0000 (16:37 +1000)]
powerpc/powernv/pci: Use the device-tree to get available range of M64's

M64's are the configurable 64-bit windows that cover the 64-bit MMIO
space. We used to hard code 16 windows. Newer chips might have a
variable number and might need to reserve some as well (for example
on PHB4/POWER9, M32 and M64 are actually unified and we use M64#0
to map the 32-bit space).

So newer OPALs will provide a property we can use to know what range
of windows is available. The property is named so that it can
eventually support multiple ranges but we only use the first one for
now.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv/pci: Fallback to OPAL for TCE invalidations
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:15 +0000 (16:37 +1000)]
powerpc/powernv/pci: Fallback to OPAL for TCE invalidations

If we don't find registers for the PHB or don't know the model
specific invalidation method, use OPAL calls instead.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv/pci: Rework accessing the TCE invalidate register
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:14 +0000 (16:37 +1000)]
powerpc/powernv/pci: Rework accessing the TCE invalidate register

It's architected, always in a known place, so there is no need
to keep a separate pointer to it, we use the existing "regs",
and we complement it with a real mode variant.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
# Conflicts:
# arch/powerpc/platforms/powernv/pci-ioda.c
# arch/powerpc/platforms/powernv/pci.h
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv/pci: Remove SWINV constants and obsolete TCE code
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:13 +0000 (16:37 +1000)]
powerpc/powernv/pci: Remove SWINV constants and obsolete TCE code

We have some obsolete code in pnv_pci_p7ioc_tce_invalidate()
to handle some internal lab tools that have stopped being
useful a long time ago. Remove that along with the definition
and test for the TCE_PCI_SWINV_* flags whose value is basically
always the same.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv/pci: Rename TCE invalidation calls
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:12 +0000 (16:37 +1000)]
powerpc/powernv/pci: Rename TCE invalidation calls

The TCE invalidation functions are fairly implementation specific,
and while the IODA specs more/less describe the register, in practice
various implementation workarounds may be required. So name the
functions after the target PHB.

Note today and for the foreseeable future, there's a 1:1 relationship
between an IODA version and a PHB implementation. There exist another
variant of IODA1 (Torrent) but we never supported in with OPAL and
never will.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/opal: Add real mode call wrappers
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:11 +0000 (16:37 +1000)]
powerpc/opal: Add real mode call wrappers

Replace the old generic opal_call_realmode() with proper per-call
wrappers similar to the normal ones and convert callers.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries/pci: Remove obsolete SW invalidate
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:10 +0000 (16:37 +1000)]
powerpc/pseries/pci: Remove obsolete SW invalidate

That was used by some old IBM internal bringup tools and is
no longer relevant.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Discover IODA3 PHBs
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:09 +0000 (16:37 +1000)]
powerpc/powernv: Discover IODA3 PHBs

We instanciate them as IODA2. We also change the MSI EOI hack
to only kick on PHB3 since it will not be needed on any new
implementation.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/xics: Add ICP OPAL backend
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:08 +0000 (16:37 +1000)]
powerpc/xics: Add ICP OPAL backend

This adds a new XICS backend that uses OPAL calls, which can be
used when we don't have native support for the platform interrupt
controller.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/irq: Add mechanism to force a replay of interrupts
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:07 +0000 (16:37 +1000)]
powerpc/irq: Add mechanism to force a replay of interrupts

Calling this function with interrupts soft-disabled will cause
a replay of the external interrupt vector when they are re-enabled.

This will be used by the OPAL XICS backend (and latter by the native
XIVE code) to handle EOI signaling that there are more interrupts to
fetch from the hardware since the hardware won't issue another HW
interrupt in that case.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/irq: Add support for HV virtualization interrupts
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:06 +0000 (16:37 +1000)]
powerpc/irq: Add support for HV virtualization interrupts

This will be delivering external interrupts from the XIVE to the
Hypervisor. We treat it as a normal external interrupt for the
lazy irq disable code (so it will be replayed as a 0x500) and
route it to do_IRQ.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/book64s: Move a few exception common handlers to make room
Benjamin Herrenschmidt [Sat, 16 Jul 2016 22:58:25 +0000 (17:58 -0500)]
powerpc/book64s: Move a few exception common handlers to make room

This moves the CBE RAS and facility unavailable "common" handlers
down to after the FWNMI page.

This frees up some space in the very demanded spaces before the
relocation-on vectors and before the FWNMI page. They are still
within 64K of __start, so CONFIG_RELOCATABLE should still work.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Add XICS emulation APIs
Benjamin Herrenschmidt [Fri, 8 Jul 2016 06:37:05 +0000 (16:37 +1000)]
powerpc/powernv: Add XICS emulation APIs

OPAL provides an emulated XICS interrupt controller to
use as a fallback on newer processors that don't have a
XICS. It's meant as a way to provide backward compatibility
with future processors. Add the corresponding interfaces.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Use deepest stop state when cpu is offlined
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:53 +0000 (11:50 +0530)]
powerpc/powernv: Use deepest stop state when cpu is offlined

If hardware supports stop state, use the deepest stop state when
the cpu is offlined.

Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocpuidle/powernv: Add support for POWER ISA v3 idle states
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:52 +0000 (11:50 +0530)]
cpuidle/powernv: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary,
 a) new instruction named stop is added.
 b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.

Supported idle states and value to be written to PSSCR register to enter
any idle state is exposed via ibm,cpu-idle-state-names and
ibm,cpu-idle-state-psscr respectively. To enter an idle state,
platform provided power_stop() needs to be invoked with the appropriate
PSSCR value.

This patch adds support for this new mechanism in cpuidle powernv driver.

Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
Cc: linux-pm@vger.kernel.org
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: linuxppc-dev@lists.ozlabs.org
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocpuidle/powernv: cleanup cpuidle-powernv.c
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:51 +0000 (11:50 +0530)]
cpuidle/powernv: cleanup cpuidle-powernv.c

- Use stack instead of kzalloc'ed memory for variables while probing
   device tree for idle states.
 - Set cap for number of idle states that can be added to
   cpuidle_state_table
 - Minor change in way we check of_property_read_u32_array for error
   for sake of consistency
 - Drop unnecessary "&" while assigning function pointer

Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocpuidle/powernv: Use CPUIDLE_STATE_MAX instead of MAX_POWERNV_IDLE_STATES
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:50 +0000 (11:50 +0530)]
cpuidle/powernv: Use CPUIDLE_STATE_MAX instead of MAX_POWERNV_IDLE_STATES

Use cpuidle's CPUIDLE_STATE_MAX macro instead of powernv specific
MAX_POWERNV_IDLE_STATES.

Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-pm@vger.kernel.org
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Add platform support for stop instruction
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:49 +0000 (11:50 +0530)]
powerpc/powernv: Add platform support for stop instruction

POWER ISA v3 defines a new idle processor core mechanism. In summary,
 a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
 b) new per thread SPR named Processor Stop Status and Control Register
(PSSCR) is added which controls the behavior of stop instruction.

PSSCR layout:
----------------------------------------------------------
| PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL |
----------------------------------------------------------
0      4     41   42    43   44     48    54   56    60

PSSCR key fields:
Bits 0:3  - Power-Saving Level Status. This field indicates the lowest
power-saving state the thread entered since stop instruction was last
executed.

Bit 42 - Enable State Loss
0 - No state is lost irrespective of other fields
1 - Allows state loss

Bits 44:47 - Power-Saving Level Limit
This limits the power-saving level that can be entered into.

Bits 60:63 - Requested Level
Used to specify which power-saving level must be entered on executing
stop instruction

This patch adds support for stop instruction and PSSCR handling.

Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: abstraction for saving SPRs before entering deep idle states
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:48 +0000 (11:50 +0530)]
powerpc/powernv: abstraction for saving SPRs before entering deep idle states

Create a function for saving SPRs before entering deep idle states.
This function can be reused for POWER9 deep idle states.

Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Make pnv_powersave_common more generic
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:47 +0000 (11:50 +0530)]
powerpc/powernv: Make pnv_powersave_common more generic

pnv_powersave_common does common steps needed before entering idle
state and eventually changes MSR to MSR_IDLE and does rfid to
pnv_enter_arch207_idle_mode.

Move the updation of HSTATE_HWTHREAD_STATE to pnv_powersave_common
from pnv_enter_arch207_idle_mode and make it more generic by passing the
rfid address as a function parameter.

Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Rename reusable idle functions to hardware agnostic names
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:46 +0000 (11:50 +0530)]
powerpc/powernv: Rename reusable idle functions to hardware agnostic names

Functions like power7_wakeup_loss, power7_wakeup_noloss,
power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can
also be used by POWER9. Hence rename these functions hardware agnostic
names.

Suggested-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Rename idle_power7.S to idle_book3s.S
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:45 +0000 (11:50 +0530)]
powerpc/powernv: Rename idle_power7.S to idle_book3s.S

idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next
patch for POWER9. Rename the file to a non-hardware specific
name.

Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/kvm: make hypervisor state restore a function
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:44 +0000 (11:50 +0530)]
powerpc/kvm: make hypervisor state restore a function

In the current code, when the thread wakes up in reset vector, some
of the state restore code and check for whether a thread needs to
branch to kvm is duplicated. Reorder the code such that this
duplication is avoided.

At a higher level this is what the change looks like-

Before this patch -
power7_wakeup_tb_loss:
restore hypervisor state
if (thread needed by kvm)
goto kvm_start_guest
restore nvgprs, cr, pc
rfid to process context

power7_wakeup_loss:
restore nvgprs, cr, pc
rfid to process context

reset vector:
if (waking from deep idle states)
goto power7_wakeup_tb_loss
else
if (thread needed by kvm)
goto kvm_start_guest
goto power7_wakeup_loss

After this patch -
power7_wakeup_tb_loss:
restore hypervisor state
return

power7_restore_hyp_resource():
if (waking from deep idle states)
goto power7_wakeup_tb_loss
return

power7_wakeup_loss:
restore nvgprs, cr, pc
rfid to process context

reset vector:
power7_restore_hyp_resource()
if (thread needed by kvm)
                goto kvm_start_guest
goto power7_wakeup_loss

Reviewed-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Use PNV_THREAD_WINKLE macro while requesting for winkle
Shreyas B. Prabhu [Fri, 8 Jul 2016 06:20:43 +0000 (11:50 +0530)]
powerpc/powernv: Use PNV_THREAD_WINKLE macro while requesting for winkle

Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/lib: Clarify that adde is an instruction and we mean plural
Stewart Smith [Mon, 23 May 2016 01:27:01 +0000 (11:27 +1000)]
powerpc/lib: Clarify that adde is an instruction and we mean plural

Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: Remove call to memblock_add()
Nathan Fontenot [Wed, 29 Jun 2016 17:20:30 +0000 (12:20 -0500)]
powerpc/pseries: Remove call to memblock_add()

The call to memblock_add is not needed, this is already done by
memory_add(). This patch removes this call which shrinks
dlpar_add_lmb_memory() enough that it can be merged into dlpar_add_lmb().

Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: Auto-online hotplugged memory
Nathan Fontenot [Wed, 29 Jun 2016 17:19:14 +0000 (12:19 -0500)]
powerpc/pseries: Auto-online hotplugged memory

A recent update (commit id 31bc3858ea3) allows for automatically
onlining memory that is added. This patch sets the config option
CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y for pseries and updates the
pseries memory hotplug code so that DLPAR added memory can be
automatically onlined instead of explicitly onlining the memory.

Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: Dynamic add entires to associativity lookup array
Nathan Fontenot [Mon, 20 Jun 2016 14:01:38 +0000 (09:01 -0500)]
powerpc/pseries: Dynamic add entires to associativity lookup array

Dynamically add entries to the associativity lookup array

The ibm,associativity-lookup-arrays property may only contain
associativity arrays for LMBs present at boot time. When hotplug
adding a LMB its associativity array may not be in the associativity
lookup array, this patch adds the ability to add new entries to the
associativity lookup array.

Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: Move property cloning into its own routine
Nathan Fontenot [Mon, 20 Jun 2016 14:00:39 +0000 (09:00 -0500)]
powerpc/pseries: Move property cloning into its own routine

Move property cloning code into its own routine

Split the pieces of dlpar_clone_drconf_property() that create a copy of
the property struct into its own routine. This allows for creating
clones of more than just the ibm,dynamic-memory property used in memory
hotplug.

Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: HVC early debug options should depend on HVC_CONSOLE
Michael Ellerman [Tue, 28 Jun 2016 05:02:46 +0000 (15:02 +1000)]
powerpc/pseries: HVC early debug options should depend on HVC_CONSOLE

The pseries HVC early debug options, CONFIG_PPC_EARLY_DEBUG_LPAR and
CONFIG_PPC_EARLY_DEBUG_LPAR_HVSI both require code that is part of the
hvc driver. If we turn them on but not CONFIG_HVC_CONSOLE then we get:

  arch/powerpc/kernel/built-in.o: In function `.udbg_early_init':
  arch/powerpc/kernel/built-in.o:(.debug_addr+0x9a00): undefined reference to `udbg_init_debug_lpar'

Similarly for HVSI. So make them both depend on CONFIG_HVC_CONSOLE.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/tm: Fix stack pointer corruption in __tm_recheckpoint()
Michael Neuling [Wed, 6 Jul 2016 04:58:06 +0000 (14:58 +1000)]
powerpc/tm: Fix stack pointer corruption in __tm_recheckpoint()

At the start of __tm_recheckpoint() we save the kernel stack pointer
(r1) in SPRG SCRATCH0 (SPRG2) so that we can restore it after the
trecheckpoint.

Unfortunately, the same SPRG is used in the SLB miss handler.  If an
SLB miss is taken between the save and restore of r1 to the SPRG, the
SPRG is changed and hence r1 is also corrupted.  We can end up with
the following crash when we start using r1 again after the restore
from the SPRG:

  Oops: Bad kernel stack pointer, sig: 6 [#1]
  SMP NR_CPUS=2048 NUMA pSeries
  CPU: 658 PID: 143777 Comm: htm_demo Tainted: G            EL   X 4.4.13-0-default #1
  task: c0000b56993a7810 ti: c00000000cfec000 task.ti: c0000b56993bc000
  NIP: c00000000004f188 LR: 00000000100040b8 CTR: 0000000010002570
  REGS: c00000000cfefd40 TRAP: 0300   Tainted: G            EL   X  (4.4.13-0-default)
  MSR: 8000000300001033 <SF,ME,IR,DR,RI,LE>  CR: 02000424  XER: 20000000
  CFAR: c000000000008468 DAR: 00003ffd84e66880 DSISR: 40000000 SOFTE: 0
  PACATMSCRATCH: 00003ffbc865e680
  GPR00: fffffffcfabc4268 00003ffd84e667a0 00000000100d8c38 000000030544bb80
  GPR04: 0000000000000002 00000000100cf200 0000000000000449 00000000100cf100
  GPR08: 000000000000c350 0000000000002569 0000000000002569 00000000100d6c30
  GPR12: 00000000100d6c28 c00000000e6a6b00 00003ffd84660000 0000000000000000
  GPR16: 0000000000000003 0000000000000449 0000000010002570 0000010009684f20
  GPR20: 0000000000800000 00003ffd84e5f110 00003ffd84e5f7a0 00000000100d0f40
  GPR24: 0000000000000000 0000000000000000 0000000000000000 00003ffff0673f50
  GPR28: 00003ffd84e5e960 00000000003d0f00 00003ffd84e667a0 00003ffd84e5e680
  NIP [c00000000004f188] restore_gprs+0x110/0x17c
  LR [00000000100040b8] 0x100040b8
  Call Trace:
  Instruction dump:
  f8a1fff0 e8e700a8 38a00000 7ca10164 e8a1fff8 e821fff0 7c0007dd 7c421378
  7db142a6 7c3242a6 38800002 7c810164 <e9c100e0e9e100e8 ea0100f0 ea2100f8

We hit this on large memory machines (> 2TB) but it can also be hit on
smaller machines when 1TB segments are disabled.

To hit this, you also need to be virtualised to ensure SLBs are
periodically removed by the hypervisor.

This patches moves the saving of r1 to the SPRG to the region where we
are guaranteed not to take any further SLB misses.

Fixes: 98ae22e15b43 ("powerpc: Add helper functions for transactional memory context switching")
Cc: stable@vger.kernel.org # v3.9+
Signed-off-by: Michael Neuling <mikey@neuling.org>
Acked-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agoMerge tag 'powerpc-4.7-5' into next
Michael Ellerman [Fri, 15 Jul 2016 04:57:47 +0000 (14:57 +1000)]
Merge tag 'powerpc-4.7-5' into next

Pull in the fixes we sent during 4.7, we have code we want to merge into
next that depends on some of them.

8 years agopowerpc: Make ppc_md.{halt, restart} __noreturn
Daniel Axtens [Tue, 12 Jul 2016 00:54:52 +0000 (10:54 +1000)]
powerpc: Make ppc_md.{halt, restart} __noreturn

powernv marks it's halt and restart calls as __noreturn. However,
ppc_md does not have this annotation. Add the annotation to ppc_md,
and then to every halt/restart function that is missing it.

Additionally, I have verified that all of these functions do not
return. Occasionally I have added a spin loop to be sure.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/sparse: Pass endianness to sparse
Daniel Axtens [Tue, 12 Jul 2016 00:54:51 +0000 (10:54 +1000)]
powerpc/sparse: Pass endianness to sparse

Explicitly give sparse an endianness in the Makefile, so that it
doesn't get confused.

Normally we have #ifdef one and #else the other, so it doesn't usually
matter, but we have been bitten by it before, and indeed this patch
fixes a number of sparse errors.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/kvm: Clarify __user annotations
Daniel Axtens [Tue, 12 Jul 2016 00:54:48 +0000 (10:54 +1000)]
powerpc/kvm: Clarify __user annotations

kvmppc_h_put_tce_indirect labels a u64 pointer as __user. It also
labelled the u64 where get_user puts the result as __user. This isn't
a pointer and so doesn't need to be labelled __user.

Split the u64 value definition onto a new line to make it clear that
it doesn't get the annotation.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pmac/smp: Add missing FROZEN hotplug notifier transitions
Anna-Maria Gleixner [Mon, 4 Apr 2016 09:30:01 +0000 (11:30 +0200)]
powerpc/pmac/smp: Add missing FROZEN hotplug notifier transitions

The FROZEN transitions are used when a CPU suspends/resumes. In case
of a suspend/resume, only the up prepare (CPU_UP_PREPARE_FROZEN) is
handled. The error handling transition CPU_UP_CANCELED_FROZEN as well
as the CPU_ONLINE_FROZEN transition are not handled.

Masking the switch case action argument with ~CPU_TASKS_FROZEN, to
handle all FROZEN tasks the same way than the corresponding non frozen
tasks.

Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards
Andrew Donnellan [Wed, 13 Jul 2016 21:17:14 +0000 (07:17 +1000)]
cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards

Add a new API, cxl_check_and_switch_mode() to allow for switching of
bi-modal CAPI cards, such as the Mellanox CX-4 network card.

When a driver requests to switch a card to CAPI mode, use PCI hotplug
infrastructure to remove all PCI devices underneath the slot. We then write
an updated mode control register to the CAPI VSEC, hot reset the card, and
reprobe the card.

As the card may present a different set of PCI devices after the mode
switch, use the infrastructure provided by the pnv_php driver and the OPAL
PCI slot management facilities to ensure that:

  * the old devices are removed from both the OPAL and Linux device trees
  * the new devices are probed by OPAL and added to the OPAL device tree
  * the new devices are added to the Linux device tree and probed through
    the regular PCI device probe path

As such, introduce a new option, CONFIG_CXL_BIMODAL, with a dependency on
the pnv_php driver.

Refactor existing code that touches the mode control register in the
regular single mode case into a new function, setup_cxl_protocol_area().

Co-authored-by: Ian Munsie <imunsie@au1.ibm.com>
Cc: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agoPCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state
Andrew Donnellan [Wed, 13 Jul 2016 21:17:13 +0000 (07:17 +1000)]
PCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state

When calling pnv_php_set_slot_power_state() with state ==
OPAL_PCI_SLOT_OFFLINE, remove devices from the device tree as if we're
dealing with OPAL_PCI_SLOT_POWER_OFF.

Cc: Gavin Shan <gwshan@linux.vnet.ibm.com>
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agoPCI/hotplug: pnv_php: export symbols and move struct types needed by cxl
Andrew Donnellan [Wed, 13 Jul 2016 21:17:12 +0000 (07:17 +1000)]
PCI/hotplug: pnv_php: export symbols and move struct types needed by cxl

The cxl driver will use infrastructure from pnv_php to handle device tree
updates when switching bi-modal CAPI cards into CAPI mode.

To enable this, export pnv_php_find_slot() and
pnv_php_set_slot_power_state(), and add corresponding declarations, as well
as the definition of struct pnv_php_slot, to asm/pnv-pci.h.

Cc: Gavin Shan <gwshan@linux.vnet.ibm.com>
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Workaround PE=0 hardware limitation in Mellanox CX4
Ian Munsie [Wed, 13 Jul 2016 21:17:11 +0000 (07:17 +1000)]
cxl: Workaround PE=0 hardware limitation in Mellanox CX4

The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:

[   34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[   34.166580] mlx5_core 0000:01:00.1: Failed allocating uar, aborting

Since the kernel API allocates a default context very early during
device init that will almost certainly get Process Element ID 0 there is
no easy way for us to extend the API to allow the Mellanox to inform us
of this limitation ahead of time.

Instead, work around the issue by extending the XSL structure to include
a minimum PE to allocate. Although the bug is not in the XSL, it is the
easiest place to work around this limitation given that the CX4 is
currently the only card that uses an XSL.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Add support for interrupts on the Mellanox CX4
Ian Munsie [Wed, 13 Jul 2016 21:17:10 +0000 (07:17 +1000)]
cxl: Add support for interrupts on the Mellanox CX4

The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style interrupts (i.e. using IVTE entries and
ranges to map a PE and AFU interrupt number to an MSIX address).

We want to hide the implementation details of cxl interrupts as much as
possible. To this end, we use a special version of the MSI setup &
teardown routines in the PHB while in cxl mode to allocate the cxl
interrupts and configure the IVTE entries in the process element.

This function does not configure the MSIX table - the CX4 card uses a
custom format in that table and it would not be appropriate to fill that
out in generic code. The rest of the functionality is similar to the
"Full MSI-X mode" described in the CAIA, and this could be easily
extended to support other adapters that use that mode in the future.

The interrupts will be associated with the default context. If the
maximum number of interrupts per context has been limited (e.g. by the
mlx5 driver), it will automatically allocate additional kernel contexts
to associate extra interrupts as required. These contexts will be
started using the same WED that was used to start the default context.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Add preliminary workaround for CX4 interrupt limitation
Ian Munsie [Wed, 13 Jul 2016 21:17:09 +0000 (07:17 +1000)]
cxl: Add preliminary workaround for CX4 interrupt limitation

The Mellanox CX4 has a hardware limitation where only 4 bits of the
AFU interrupt number can be passed to the XSL when sending an interrupt,
limiting it to only 15 interrupts per context (AFU interrupt number 0 is
invalid).

In order to overcome this, we will allocate additional contexts linked
to the default context as extra address space for the extra interrupts -
this will be implemented in the next patch.

This patch adds the preliminary support to allow this, by way of adding
a linked list in the context structure that we use to keep track of the
contexts dedicated to interrupts, and an API to simultaneously iterate
over the related context structures, AFU interrupt numbers and hardware
interrupt numbers. The point of using a single API to iterate these is
to hide some of the details of the iteration from external code, and to
reduce the number of APIs that need to be exported via base.c to allow
built in code to call.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Add kernel APIs to get & set the max irqs per context
Ian Munsie [Wed, 13 Jul 2016 21:17:08 +0000 (07:17 +1000)]
cxl: Add kernel APIs to get & set the max irqs per context

These APIs will be used by the Mellanox CX4 support. While they function
standalone to configure existing behaviour, their primary purpose is to
allow the Mellanox driver to inform the cxl driver of a hardware
limitation, which will be used in a future patch.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Add support for using the kernel API with a real PHB
Ian Munsie [Wed, 13 Jul 2016 21:17:07 +0000 (07:17 +1000)]
cxl: Add support for using the kernel API with a real PHB

This hooks up support for using the kernel API with a real PHB. After
the AFU initialisation has completed it calls into the PHB code to pass
it the AFU that will be used by other peer physical functions on the
adapter.

The cxl_pci_to_afu API is extended to work with peer PCI devices,
retrieving the peer AFU from the PHB. This API may also now return an
error if it is called on a PCI device that is not associated with either
a cxl vPHB or a peer PCI device to an AFU, and this error is propagated
down.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Add support for the cxl kernel api on the real phb
Ian Munsie [Wed, 13 Jul 2016 21:17:06 +0000 (07:17 +1000)]
powerpc/powernv: Add support for the cxl kernel api on the real phb

This adds support for the peer model of the cxl kernel api to the
PowerNV PHB, in which physical function 0 represents the cxl function on
the card (an XSL in the case of the CX4), which other physical functions
will use for memory access and interrupt services. It is referred to as
the peer model as these functions are peers of one another, as opposed
to the Virtual PHB model which forms a hierarchy.

This patch exports APIs to enable the peer mode, check if a PCI device
is attached to a PHB in this mode, and to set and get the peer AFU for
this mode.

The cxl driver will enable this mode for supported cards by calling
pnv_cxl_enable_phb_kernel_api(). This will set a flag in the PHB to note
that this mode is enabled, and switch out it's controller_ops for the
cxl version.

The cxl version of the controller_ops struct implements it's own
versions of the enable_device_hook and release_device to handle
refcounting on the peer AFU and to allocate a default context for the
device.

Once enabled, the cxl kernel API may not be disabled on a PHB. Currently
there is no safe way to disable cxl mode short of a reboot, so until
that changes there is no reason to support the disable path.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Do not create vPHB if there are no AFU configuration records
Ian Munsie [Wed, 13 Jul 2016 21:17:05 +0000 (07:17 +1000)]
cxl: Do not create vPHB if there are no AFU configuration records

The vPHB model of the cxl kernel API is a hierarchy where the AFU is
represented by the vPHB, and it's AFU configuration records are exposed
as functions under that vPHB. If there are no AFU configuration records
we will create a vPHB with nothing under it, which is a waste of
resources and will opt us into EEH handling despite not having anything
special to handle.

This also does not make sense for cards using the peer model of the cxl
kernel API, where the other functions of the device are exposed via
additional peer physical functions rather than AFU configuration
records. This model will also not work with the existing EEH handling in
the cxl driver, as that is designed around the vPHB model.

Skip creating the vPHB for AFUs without any AFU configuration records,
and opt out of EEH handling for them.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Allow a default context to be associated with an external pci_dev
Ian Munsie [Wed, 13 Jul 2016 21:17:04 +0000 (07:17 +1000)]
cxl: Allow a default context to be associated with an external pci_dev

The cxl kernel API has a concept of a default context associated with
each PCI device under the virtual PHB. The Mellanox CX4 will also use
the cxl kernel API, but it does not use a virtual PHB - rather, the AFU
appears as a physical function as a peer to the networking functions.

In order to allow the kernel API to work with those networking
functions, we will need to associate a default context with them as
well. To this end, refactor the corresponding code to do this in vphb.c
and export it so that it can be called from the PHB code.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Move cxl_afu_get / cxl_afu_put to base
Ian Munsie [Wed, 13 Jul 2016 21:17:03 +0000 (07:17 +1000)]
cxl: Move cxl_afu_get / cxl_afu_put to base

The Mellanox CX4 uses a model where the AFU is one physical function of
the device, and is used by other peer physical functions of the same
device. This will require those other devices to grab a reference on the
AFU when they are initialised to make sure that it does not go away
during their lifetime.

Move the AFU refcount functions to base.c so they can be called from
the PHB code.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Enable bus mastering for devices using CAPP DMA mode
Ian Munsie [Wed, 13 Jul 2016 21:17:02 +0000 (07:17 +1000)]
cxl: Enable bus mastering for devices using CAPP DMA mode

Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Add cxl_slot_is_supported API
Ian Munsie [Wed, 13 Jul 2016 21:17:01 +0000 (07:17 +1000)]
cxl: Add cxl_slot_is_supported API

This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be switched to cxl mode so that it can leave it in
PCI mode if it is not.

This API takes a parameter to check if CAPP DMA mode is supported, which
it currently only allows on P8NVL systems, since that mode currently has
issues accessing memory < 4GB on P8, and we cannot realistically avoid
that.

This API does not currently check if a CAPP unit is available (i.e. not
already assigned to another PHB) on P8. Doing so would be racy since it
is assigned on a first come first serve basis, and so long as CAPP DMA
mode is not supported on P8 we don't need this, since the only
anticipated user of this API requires CAPP DMA mode.

Cc: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/powernv: Split cxl code out into a separate file
Ian Munsie [Wed, 13 Jul 2016 21:17:00 +0000 (07:17 +1000)]
powerpc/powernv: Split cxl code out into a separate file

The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Use for_each_compatible_node() macro
Wei Yongjun [Tue, 12 Jul 2016 11:30:11 +0000 (11:30 +0000)]
cxl: Use for_each_compatible_node() macro

Use for_each_compatible_node() macro instead of open coding it.

Generated by Coccinelle.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agoselftests/powerpc: Add a test for PROT_SAO
Michael Ellerman [Mon, 11 Jul 2016 05:25:18 +0000 (15:25 +1000)]
selftests/powerpc: Add a test for PROT_SAO

PROT_SAO is a powerpc-specific flag to mmap(), and we rely on arch
specific logic to allow it to be passed to mmap().

Add a small test to ensure mmap() accepts PROT_SAO. We don't have a good
way to test that it actually causes the mapping to be created with the
right flags, so for now we just touch the mapping so it's faulted in. In
future we might be able to do something better.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/xmon: Dump ISA 2.07 SPRs
Michael Ellerman [Thu, 7 Jul 2016 12:54:30 +0000 (22:54 +1000)]
powerpc/xmon: Dump ISA 2.07 SPRs

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/xmon: Dump ISA 2.06 SPRs
Michael Ellerman [Thu, 7 Jul 2016 12:54:29 +0000 (22:54 +1000)]
powerpc/xmon: Dump ISA 2.06 SPRs

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/xmon: Adjust spacing of existing SPRs to make room for more
Michael Ellerman [Thu, 7 Jul 2016 12:54:28 +0000 (22:54 +1000)]
powerpc/xmon: Adjust spacing of existing SPRs to make room for more

Purely to make it pleasing to the eye.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/xmon: Move static regno into its only user
Michael Ellerman [Thu, 7 Jul 2016 12:54:27 +0000 (22:54 +1000)]
powerpc/xmon: Move static regno into its only user

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/xmon: Remove unused externs
Michael Ellerman [Thu, 7 Jul 2016 12:54:26 +0000 (22:54 +1000)]
powerpc/xmon: Remove unused externs

None of these are used, or have been since we merged ppc & ppc64.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/crash: Rearrange loop condition to avoid out of bounds array access
Suraj Jitindar Singh [Mon, 11 Jul 2016 04:17:31 +0000 (14:17 +1000)]
powerpc/crash: Rearrange loop condition to avoid out of bounds array access

The array crash_shutdown_handles[] has size CRASH_HANDLER_MAX, thus when
we loop over the elements of the list we check crash_shutdown_handles[i]
&& i < CRASH_HANDLER_MAX. However this means that when we increment i to
CRASH_HANDLER_MAX we will perform an out of bound array access checking
the first condition before exiting on the second condition.

To avoid the out of bounds access, simply reorder the loop conditions.

Fixes: 1d1451655bad ("powerpc: Add array bounds checking to crash_shutdown_handlers")
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Don't test for machine type in smp_setup_cpu_maps()
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:03:55 +0000 (15:03 +1000)]
powerpc: Don't test for machine type in smp_setup_cpu_maps()

The subsequent test for RTAS along with the LPAR test are sufficient

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/rtas: Don't test for machine type in rtas_initialize()
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:03:54 +0000 (15:03 +1000)]
powerpc/rtas: Don't test for machine type in rtas_initialize()

The test is unnecessary, the FW_FEATURE_LPAR is sufficient as there
exist no other LPAR type that has RTAS.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/85xx/mpc85xx_rdb: Don't use the flat device-tree after boot
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:04:04 +0000 (15:04 +1000)]
powerpc/85xx/mpc85xx_rdb: Don't use the flat device-tree after boot

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/85xx/mpc85xx_ds: Don't use the flat device-tree after boot
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:04:03 +0000 (15:04 +1000)]
powerpc/85xx/mpc85xx_ds: Don't use the flat device-tree after boot

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/85xx/ge_imp3a: Don't use the flat device-tree after boot
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:04:02 +0000 (15:04 +1000)]
powerpc/85xx/ge_imp3a: Don't use the flat device-tree after boot

ge_imp3a_pic_init() is called way beyond the unflattening of
the tree, it shouldn't be using of_flat_dt_*

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/cell: Don't use flat device-tree after boot
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:04:01 +0000 (15:04 +1000)]
powerpc/cell: Don't use flat device-tree after boot

Some bit of SPU code was using the FDT rather than the expanded
device-tree. Fix it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Move epapr_paravirt_early_init() to early_init_devtree()
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:03:44 +0000 (15:03 +1000)]
powerpc: Move epapr_paravirt_early_init() to early_init_devtree()

The function is called by both 32-bit and 64-bit early setup right
after early_init_devtree(). All it does is run yet another early
DT parser which is precisely what early_init_devtree() is about,
so move it in there.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Add comment explaining the purpose of setup_kdump_trampoline()
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:03:46 +0000 (15:03 +1000)]
powerpc: Add comment explaining the purpose of setup_kdump_trampoline()

Anything in early_setup() needs to be justified to be there, in
this case, we need the trampolines before we can take exceptions
and thus before we turn on the MMU.

Also remove a pretty meaningless and misplaced debug message

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[mpe: Fix comment formatting]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Update obsolete comments in setup_32.c about entry conditions
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:03:45 +0000 (15:03 +1000)]
powerpc: Update obsolete comments in setup_32.c about entry conditions

early_init() is called in-place before kernel relocation and using
whatever MMU setup exists at the point the kernel is entered.

machine_init() is called after relocation and after some initial
mapping of PAGE_OFFSET has been established (typically using BATs
on 6xx/7xx/7xxx processors or some form of bolted TLB on others).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Ignore CAPI adapters misplaced in switched slots
Philippe Bergheaud [Fri, 1 Jul 2016 11:32:52 +0000 (13:32 +0200)]
cxl: Ignore CAPI adapters misplaced in switched slots

One should not attempt to switch a PHB into CAPI mode if there is
a switch between the PHB and the adapter. This patch modifies the
cxl driver to ignore CAPI adapters misplaced in switched slots.

Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: make base more explicitly non-modular
Paul Gortmaker [Sun, 3 Jul 2016 20:31:53 +0000 (16:31 -0400)]
cxl: make base more explicitly non-modular

The Kconfig/Makefile currently controlling compilation of this code is:

drivers/misc/cxl/Kconfig:config CXL_BASE
drivers/misc/cxl/Kconfig:       bool

drivers/misc/cxl/Makefile:obj-$(CONFIG_CXL_BASE)          += base.o

...meaning that it currently is not being built as a module by anyone.

Lets convert the one module_init into device_initcall so that
when reading the driver it more clear that it is builtin-only.

Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.

We don't replace module.h with init.h since the file is doing
other modular stuff (module_get/put) even though it is built-in.

Cc: Ian Munsie <imunsie@au1.ibm.com>
Cc: Michael Neuling <mikey@neuling.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Refine slice error debug messages
Philippe Bergheaud [Tue, 5 Jul 2016 11:08:06 +0000 (13:08 +0200)]
cxl: Refine slice error debug messages

The PSL Slice Error Register (PSL_SERR_An) reports implementation
dependent AFU errors, in the form of a bitmap. The PSL_SERR_An
register content is printed in the form of hex dump debug message.

This patch decodes the PSL_ERR_An register contents, and prints a
specific error message for each possible error bit. It also dumps
the secondary registers AFU_ERR_An and PSL_DSISR_An, that may
contain extra debug information.

This patch also removes the large WARN message that used to report
the cxl slice error interrupt, and replaces it by a short informative
message, that draws attention to AFU implementation errors.

Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Fix NULL pointer dereference on kernel contexts with no AFU interrupts
Ian Munsie [Wed, 29 Jun 2016 18:55:17 +0000 (04:55 +1000)]
cxl: Fix NULL pointer dereference on kernel contexts with no AFU interrupts

If a kernel context is initialised and does not have any AFU interrupts
allocated it will cause a NULL pointer dereference when the context is
detached since the irq_names list will not have been initialised.

Move the initialisation of the irq_names list into the cxl_context_init
routine so that it will be valid for the entire lifetime of the context
and will not cause a NULL pointer dereference.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Workaround XSL bug that does not clear the RA bit after a reset
Ian Munsie [Wed, 29 Jun 2016 18:51:26 +0000 (04:51 +1000)]
cxl: Workaround XSL bug that does not clear the RA bit after a reset

An issue was noted in our debug logs where the XSL would leave the RA
bit asserted after an AFU reset operation, which would effectively
prevent further AFU reset operations from working.

Workaround the issue by clearing the RA bit with an MMIO write if it is
still asserted after any AFU control operation.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Fix bug where AFU disable operation had no effect
Ian Munsie [Thu, 30 Jun 2016 16:50:40 +0000 (02:50 +1000)]
cxl: Fix bug where AFU disable operation had no effect

The AFU disable operation has a bug where it will not clear the enable
bit and therefore will have no effect. To date this has likely been
masked by fact that we perform an AFU reset before the disable, which
also has the effect of clearing the enable bit, making the following
disable operation effectively a noop on most hardware. This patch
modifies the afu_control function to take a parameter to clear from the
AFU control register so that the disable operation can clear the
appropriate bit.

This bug was uncovered on the Mellanox CX4, which uses an XSL rather
than a PSL. On the XSL the reset operation will not complete while the
AFU is enabled, meaning the enable bit was still set at the start of the
disable and as a result this bug was hit and the disable also timed out.

Because of this difference in behaviour between the PSL and XSL, this
patch now makes the reset dependent on the card using a PSL to avoid
waiting for a timeout on the XSL. It is entirely possible that we may be
able to drop the reset altogether if it turns out we only ever needed it
due to this bug - however I am not willing to drop it without further
regression testing and have added comments to the code explaining the
background.

This also fixes a small issue where the AFU_Cntl register was read
outside of the lock that protects it.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Fix allocating a minimum of 2 pages for the SPA
Ian Munsie [Wed, 29 Jun 2016 12:16:26 +0000 (22:16 +1000)]
cxl: Fix allocating a minimum of 2 pages for the SPA

The Scheduled Process Area is allocated dynamically with enough pages to
fit at least as many processes as the AFU descriptor indicated. Since
the calculation is non-trivial, it does this by calculating how many
processes could fit in an allocation of a given order, and increasing
that order until it can fit enough processes or hits the maximum
supported size.

Currently, it will start this search using a SPA of 2 pages instead of
1. This can waste a page of memory if the AFU's maximum number of
supported processes was small enough to fit in one page.

Fix the algorithm to start the search at 1 page.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agocxl: Fix allowing bogus AFU descriptors with 0 maximum processes
Ian Munsie [Wed, 29 Jun 2016 12:16:25 +0000 (22:16 +1000)]
cxl: Fix allowing bogus AFU descriptors with 0 maximum processes

If the AFU descriptor of an AFU directed AFU indicates that it supports
0 maximum processes, we will accept that value and attempt to use it.
The SPA will still be allocated (with 2 pages due to another minor bug
and room for 958 processes), and when a context is allocated we will
pass the value of 0 to idr_alloc as the maximum. However, idr_alloc will
treat that as meaning no maximum and will allocate a context number and
we return a valid context.

Conceivably, this could lead to a buffer overflow of the SPA if more
than 958 contexts were allocated, however this is mitigated by the fact
that there are no known AFUs in the wild with a bogus AFU descriptor
like this, and that only the root user is allowed to flash an AFU image
to a card.

Add a check when validating the AFU descriptor to reject any with 0
maximum processes.

We do still allow a dedicated process only AFU to indicate that it
supports 0 contexts even though that is forbidden in the architecture,
as in that case we ignore the value and use 1 instead. This is just on
the off-chance that such a dedicated process AFU may exist (not that I
am aware of any), since their developers are less likely to have cared
about this value at all.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/configs: Remove old symbols from defconfigs
Andrew Donnellan [Tue, 5 Jul 2016 06:12:35 +0000 (16:12 +1000)]
powerpc/configs: Remove old symbols from defconfigs

Update defconfigs to remove old symbols and comments referencing old
symbols.

Dropped:

* AVERAGE
* INET_LRO
* EXT3_DEFAULTS_TO_ORDERED
* EXT3_FS_XATTR
* I2O
* INFINIBAND_AMSO1100
* INFINIBAND_EHCA
* IP1000

Replaced:

* BLK_DEV_XIP -> BLK_DEV_RAM_DAX
* CLK_PPC_CORENET -> CLK_QORIQ
* EXT2_FS_XIP -> FS_DAX
* EXT3_FS* -> EXT4_FS*

Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Fix typo in comment reference to CONFIG_TRACE_IRQFLAGS
Andrew Donnellan [Tue, 5 Jul 2016 06:12:34 +0000 (16:12 +1000)]
powerpc: Fix typo in comment reference to CONFIG_TRACE_IRQFLAGS

Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/ps3: Fix typo in comment reference to CONFIG_PS3_REPOSITORY_WRITE
Andrew Donnellan [Tue, 5 Jul 2016 06:12:33 +0000 (16:12 +1000)]
powerpc/ps3: Fix typo in comment reference to CONFIG_PS3_REPOSITORY_WRITE

Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/eeh: Fix pr_debug()s in eeh_cache.c
Andrew Donnellan [Fri, 24 Jun 2016 05:54:22 +0000 (15:54 +1000)]
powerpc/eeh: Fix pr_debug()s in eeh_cache.c

eeh_cache.c doesn't build cleanly with -DDEBUG when
CONFIG_PHYS_ADDR_T_64BIT is set, as a couple of pr_debug()s use "%lx" for
resource_size_t parameters.

Use "%pap" instead, as it's the correct format specifier for types deriving
from phys_addr_t.

Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/opal: Wake up kopald polling thread before waiting for events
Benjamin Herrenschmidt [Mon, 4 Jul 2016 04:51:44 +0000 (14:51 +1000)]
powerpc/opal: Wake up kopald polling thread before waiting for events

On some environments (prototype machines, some simulators, etc...)
there is no functional interrupt source to signal completion, so
we rely on the fairly slow OPAL heartbeat.

In a number of cases, the calls complete very quickly or even
immediately. We've observed that it helps a lot to wakeup the OPAL
heartbeat thread before waiting for event in those cases, it will
call OPAL immediately to collect completions for anything that
finished fast enough.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-By: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Add MTD_BLOCK to powernv_defconfig
Michael Neuling [Fri, 8 Jul 2016 03:13:15 +0000 (13:13 +1000)]
powerpc: Add MTD_BLOCK to powernv_defconfig

This is so we can use the powernv_flash mtd driver as an block
device.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: start rtasd before PCI probing
Greg Kurz [Wed, 15 Jun 2016 20:26:41 +0000 (22:26 +0200)]
powerpc/pseries: start rtasd before PCI probing

A strange behaviour is observed when comparing PCI hotplug in QEMU, between
x86 and pseries. If you consider the following steps:
- start a VM
- add a PCI device via the QEMU monitor before the rtasd has started (for
  example starting the VM in paused state, or hotplug during FW or boot
  loader)
- resume the VM execution

The x86 kernel detects the PCI device, but the pseries one does not.

This happens because the rtasd kernel worker is currently started under
device_initcall, while PCI probing happens earlier under subsys_initcall.

As a consequence, if we have a pending RTAS event at boot time, a message
is printed and the event is dropped.

This patch moves all the initialization of rtasd to arch_initcall, which is
run before subsys_call: this way, logging_enabled is true when the RTAS
event pops up and it is not lost anymore.

The proc fs bits stay at device_initcall because they cannot be run before
fs_initcall.

Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pci: Assign fixed PHB number based on device-tree properties
Guilherme G. Piccoli [Wed, 29 Jun 2016 18:14:22 +0000 (15:14 -0300)]
powerpc/pci: Assign fixed PHB number based on device-tree properties

The domain/PHB field of PCI addresses has its value obtained from a
global variable, incremented each time a new domain (represented by
struct pci_controller) is added on the system. The domain addition
process happens during boot or due to PHB hotplug add.

As recent kernels are using predictable naming for network interfaces,
the network stack is more tied to PCI naming. This can be a problem in
hotplug scenarios, because PCI addresses will change if devices are
removed and then re-added. This situation seems unusual, but it can
happen if a user wants to replace a NIC without rebooting the machine,
for example.

This patch changes the way PCI domain values are generated: now, we use
device-tree properties to assign fixed PHB numbers to PCI addresses
when available (meaning pSeries and PowerNV cases). We also use a bitmap
to allow dynamic PHB numbering when device-tree properties are not
used. This bitmap keeps track of used PHB numbers and if a PHB is
released (by hotplug operations for example), it allows the reuse of
this PHB number, avoiding PCI address to change in case of device remove
and re-add soon after. No functional changes were introduced.

Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: Ian Munsie <imunsie@au1.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
[mpe: Drop unnecessary machine_is(pseries) test]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/kernel: Drop unused extern for current_set
Michael Ellerman [Wed, 29 Jun 2016 11:25:33 +0000 (21:25 +1000)]
powerpc/kernel: Drop unused extern for current_set

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pci: Fix build with PCI_IOV=y and EEH=n
Michael Ellerman [Tue, 5 Jul 2016 04:07:07 +0000 (14:07 +1000)]
powerpc/pci: Fix build with PCI_IOV=y and EEH=n

Despite attempting to fix this in commit fb36e9073693 ("powerpc/pci: Fix
SRIOV not building without EEH enabled"), the build is still broken when
PCI_IOV=y and EEH=n (eg. g5_defconfig with PCI_IOV=y):

  arch/powerpc/kernel/pci_dn.c: In function ‘remove_dev_pci_data’:
  arch/powerpc/kernel/pci_dn.c:230:18: error: unused variable ‘edev’

Incorporate Ben's idea of using __maybe_unused to avoid so many #ifdefs.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Fix build with CONFIG_MEMORY_HOTPLUG on some configs
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:07:54 +0000 (15:07 +1000)]
powerpc: Fix build with CONFIG_MEMORY_HOTPLUG on some configs

For memory hotplug to work, the MMU code needs to provide the functions
create_section_mapping() and remove_section_mapping() to respectively
map and unmap portions of the linear mapping.

At the moment only hash64 provides these, so we provide weak stubs that
just error out. This fixes the build with configurations such as 64-bit
BookE with CONFIG_MEMORY_HOTPLUG enabled.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/mm: Fix build of Book3E/64 with 64K pages
Benjamin Herrenschmidt [Tue, 5 Jul 2016 05:07:52 +0000 (15:07 +1000)]
powerpc/mm: Fix build of Book3E/64 with 64K pages

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agoselftests/powerpc: Use "Delta" rather than "Error" in normal output
Michael Ellerman [Wed, 6 Jul 2016 05:17:34 +0000 (15:17 +1000)]
selftests/powerpc: Use "Delta" rather than "Error" in normal output

Use "Delta" to refer to the difference between measurements, rather than
"Error", so scripts that look for "Error" aren't confused into thinking
there was a failure.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/boot: Add OPAL console to epapr wrappers
Oliver O'Halloran [Thu, 30 Jun 2016 14:34:37 +0000 (00:34 +1000)]
powerpc/boot: Add OPAL console to epapr wrappers

This patch adds an OPAL console backend to the powerpc boot wrapper so
that decompression failures inside the wrapper can be reported to the
user. This is important since it typically indicates data corruption in
the firmware and other nasty things.

Currently this only works when building a little endian kernel. When
compiling a 64 bit BE kernel the wrapper is always build 32 bit to be
compatible with some 32 bit firmwares. BE support will be added at a
later date. Another limitation of this is that only the "raw" type of
OPAL console is supported, however machines that provide a hvsi console
also provide a raw console so this is not an issue in practice.

Actually-written-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[mpe: Move #ifdef __powerpc64__ to avoid warnings on 32-bit]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/mm: Add a parameter to disable 1TB segs
Oliver O'Halloran [Tue, 5 Jul 2016 01:43:21 +0000 (11:43 +1000)]
powerpc/mm: Add a parameter to disable 1TB segs

This patch adds the kernel command line parameter "no_tb_segs" which
forces the kernel to use 256MB rather than 1TB segments. Forcing the use
of 256MB segments makes it considerably easier to test code that depends
on an SLB miss occurring.

Suggested-by: Michael Neuling <mikey@neuling.org>
Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/timer: Large Decrementer support
Oliver O'Halloran [Fri, 1 Jul 2016 06:20:39 +0000 (16:20 +1000)]
powerpc/timer: Large Decrementer support

Power ISAv3 adds a large decrementer (LD) mode which increases the size
of the decrementer register. The size of the enlarged decrementer
register is between 32 and 64 bits with the exact size being dependent
on the implementation. When in LD mode, reads are sign extended to 64
bits and a decrementer exception is raised when the high bit is set (i.e
the value goes below zero). Writes however are truncated to the physical
register width so some care needs to be taken to ensure that the high
bit is not set when reloading the decrementer. This patch adds support
for using the LD inside the host kernel on processors that support it.

When LD mode is supported firmware will supply the ibm,dec-bits property
for CPU nodes to allow the kernel to determine the maximum decrementer
value. Enabling LD mode is a hypervisor privileged operation so the kernel
can only enable it manually when running in hypervisor mode. Guests that
support LD mode can request it using the "ibm,client-architecture-support"
firmware call (not implemented in this patch) or some other platform
specific method. If this property is not supplied then the traditional
decrementer width of 32 bit is assumed and LD mode will not be enabled.

This patch was based on initial work by Jack Miller.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc: Avoid -maltivec when using clang integrated assembler
Anton Blanchard [Wed, 25 Nov 2015 23:45:49 +0000 (10:45 +1100)]
powerpc: Avoid -maltivec when using clang integrated assembler

Check the assembler supports -maltivec by wrapping it with
call as-option.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
8 years agopowerpc/pseries: Fix error return value in cmm_mem_going_offline()
Rasmus Villemoes [Tue, 8 Mar 2016 21:26:17 +0000 (22:26 +0100)]
powerpc/pseries: Fix error return value in cmm_mem_going_offline()

cmm_mem_going_offline() is (only) called from cmm_memory_cb(), which
sends the return value through notifier_from_errno(). The latter
expects 0 or -errno (notifier_to_errno(notifier_from_errno(x)) is 0
for any x >= 0, so passing a positive value cannot make sense). Hence
negate ENOMEM.

Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>