GitHub/LineageOS/G12/android_kernel_amlogic_linux-4.9.git
9 years agopinctrl: rockchip: add support for the rk3368
Heiko Stübner [Fri, 12 Jun 2015 21:51:01 +0000 (23:51 +0200)]
pinctrl: rockchip: add support for the rk3368

The rk3368 is the first ARM64 soc from Rockchip, but seems to share most
peripherals with the ARM32 soc, including the pinctrl functionality.
The only notable difference is - as with every Rockchip soc - that the
offsets in the General Register Files moved around and a split of the pmu
section of the rk3288 into pmu and pmugrf (pmu general register files)
sections. The pinctrl driver of course only needs the pmugrf registers
for controlling the pin settings.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: rockchip: generalize perpin driver-strength setting
Heiko Stübner [Fri, 12 Jun 2015 21:50:11 +0000 (23:50 +0200)]
pinctrl: rockchip: generalize perpin driver-strength setting

The upcoming support for the RK3368 ARM64 SoC also supports perpin
drive strength settings (at different register positions), so generalize
the register and offset calculation to easily support this one too.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: r8a7794: add SDHI pin groups
Shinobu Uehara [Fri, 5 Jun 2015 22:36:50 +0000 (01:36 +0300)]
pinctrl: sh-pfc: r8a7794: add SDHI pin groups

Add SDHI0/1/2 pin groups to R8A7794 PFC driver.

Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
[Sergei: renamed SD data pins to match the driver, rebased, renamed, added
changelog.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: r8a7794: add MMCIF pin groups
Shinobu Uehara [Fri, 5 Jun 2015 22:35:54 +0000 (01:35 +0300)]
pinctrl: sh-pfc: r8a7794: add MMCIF pin groups

Add MMCIF pin groups to R8A7794 PFC driver.

Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
[Sergei: rebased, renamed, added changelog.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: add R8A7794 PFC support
Hisashi Nakamura [Fri, 5 Jun 2015 22:34:48 +0000 (01:34 +0300)]
pinctrl: sh-pfc: add R8A7794 PFC support

Add PFC support for  the  R8A7794 SoC  including pin groups for some
on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF...

Sergei: squashed together several patches, fixed the MLB_CLK typo,
added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin
group names, removed stray new line and fixed typos in the  comments
in the pinmux_config_regs[] initializer, removed the platform device
ID, took into account limited number of signals in the GPIO1/5/6
controllers, added reasonable and removed unreasonable
copyrights, modified the bindings document, renamed, added changelog.

Changes in version 5:
- resolved rejects, refreshed the patch;
- added Laurent Pinchart's ACK.

Changes in version 4:
- reused the PORT_GP_26() macro to #define PORT_GP_28().

Changes in version 3:
- removed the platform device ID;
- added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the
  CPU_ALL_PORT() macro.

Changes in version 2:
- rebased the patch.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: make pinctrl_register() return proper error code
Masahiro Yamada [Tue, 9 Jun 2015 04:01:16 +0000 (13:01 +0900)]
pinctrl: make pinctrl_register() return proper error code

Currently, pinctrl_register() just returns NULL on error, so the
callers can not know the exact reason of the failure.

Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
-ENOMEM on error of pinctrl_register(), although the error code
might be different from the real cause of the error.

This commit reworks pinctrl_register() to return the appropriate
error code and modifies all of the pinctrl drivers to use IS_ERR()
for the error checking and PTR_ERR() for getting the error code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Ray Jui <rjui@broadcom.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: add support for Armada 395 variant
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:26 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: add support for Armada 395 variant

The Armada 39x SoC family has grown a new variant, the Armada 395,
which sits between the Armada 390 and Armada 398 in terms of
features. This commit adds support for this additional variant to the
Armada 39x pinctrl driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: add missing SATA functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:25 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: add missing SATA functions

The latest version of the Armada 39x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: add missing PCIe functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:24 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: add missing PCIe functions

The latest version of the Armada 39x datasheet documents several new
PCIe related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 39x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-38x: add ptp functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:23 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-38x: add ptp functions

The latest version of the Armada 38x datasheet documents several new
PTP related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-38x: add ua1 functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:22 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-38x: add ua1 functions

The latest version of the Armada 38x datasheet documents several new
UART1 related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-38x: add nand functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:21 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-38x: add nand functions

The latest version of the Armada 38x datasheet documents several new
NAND related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-38x: add sata functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:20 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-38x: add sata functions

The latest version of the Armada 38x datasheet documents several new
SATA related functions on various MPP pins. This commit adds the
description of these new functions to the Armada 38x pinctrl driver as
well as to its DT binding documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: add dram functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:19 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-xp: add dram functions

The latest Armada XP datasheet documents several new DRAM related
functions on various MPPs. This commit adds the description of these
new functions in the Armada XP pinctrl driver and its DT binding
documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: add nand rb function
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:18 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-xp: add nand rb function

The latest version of the Armada XP datasheet documents a new
NAND-related MPP function on MPP48, for which this commit adds
support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: add spi1 function
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:17 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-xp: add spi1 function

The latest Armada XP datasheet documents that some of the MPP pins can
be used to access the second SPI bus, labelled 'spi1'. This commit
adds the corresponding pins in the pinctrl driver and its DT binding
documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: normalize ref clock naming
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:16 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: normalize ref clock naming

This commit normalizes the subnames of the reference clock MPP pins in
the Armada 39x pinctrl driver to match with the name used on other
SoCs.

Since only the subnames are changed, DT backward compatibility is not
affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: rename spi to spi0
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:15 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-xp: rename spi to spi0

After updating to the latest Armada XP datasheet, we discovered that
there is a second SPI bus accessible from the MPP pins, called 'spi1'.

In order to be consistent with other SoCs having two SPI busses, this
commit renames the functions of the first SPI bus to 'spi0' instead of
just 'spi'.

This commit obviously breaks the DT backward compatibility for the
people using the "spi" function name in their Device Tree.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-370: align spi1 clock pin naming
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:14 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-370: align spi1 clock pin naming

Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the
'sck' subname and not 'clk', so this commit adjusts the code and
documentation accordingly.

Since this commit only changes the subname, DT backward compatibility
is not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:13 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet

For consistency with the datasheet, this commit renames the VDD
function of the MPP4 pin.

While this changes the DT compatibility, it is not considered to be a
problem since this pin is unlikely to be used for anything but
debugging purposes.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:12 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-xp: fix binding documentation of ge1 pins

There was an off-by-one in the documentation of the ge1(txd[0-3])
pins, which is fixed by this commit. Since the driver was correct, and
the subnames are anyway not used in the DT binding itself, there is no
need to push this documentation fix for stable.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:11 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pins

This commit normalizes the naming of the Ethernet txclkout pin to be
the same accross Marvell SoCs. It is worth mentioning that the DT
binding documentation of the Armada XP was wrong for MPP12: it said
the function was ge1(txd0), while it is in fact ge1(txclkout). It is
however not really a fix worth sending to stable since it does not
change the behavior, and the driver itself was correct.

Since only the subnames are changed, DT backward compatibility is not
affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{370,375}: normalize audio pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:10 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{370,375}: normalize audio pins

This commit aligns the naming of the audio 'lrclk' pin accross Marvell
SoCs.

Since only the subname is changed, the DT backward compatibility is
not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{370,375}: normalize PCIe pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:09 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{370,375}: normalize PCIe pins

This commit normalizes the naming of PCIe pins to use 'rstout' instead
of 'rstoutn' or 'rst-out'.

Since only the subnames are changed, DT compatibility is not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:08 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pins

This commit normalizes the naming of the TDM pins accross the
different Marvell SoCs. Mainly it consists in:

 * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn'
   becomes 'rst'

 * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x.

 * Change the main name 'tdm-1' to 'tdm' for one of the pins of the
   Armada XP

The last two changes affect DT compatibility, but since the TDM
interface is nowhere near being supported in mainline, it should not
be considered to be a serious problem at this point.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: align NAND pin naming
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:07 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: align NAND pin naming

All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.

It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.

While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:06 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pins

This commit modifies the definition of the Device Bus interface pins
to be consistent accross SoCs. Especially, it removes the 'n'
indicators that we don't encode in the subnames of pins:

   'dev(wen0)' becomes 'dev(we0)'
   'dev(wen1)' becomes 'dev(we1)'
   'dev(oen)' becomes 'dev(oe)'
   etc.

In addition, it fixes the Armada 375 DT binding documentation, which
forgot to document the 'dev' function for MPP46, MPP57 and MPP63.

Since only the subnames are changed, this commit does not affect DT
compatibility.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: normalize SDIO pin naming
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:05 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: normalize SDIO pin naming

In order to be consistent with the datasheet and some other SoCs, this
commit renames the SDIO pins of the Armada 39x from "sd" to "sd0".

While this changes the DT binding, this is not a problem since Armada
39x is a brand new SoC which isn't used in production yet (so now is
the right time to fix such things).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: normalize SATA present functionality naming
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:04 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: normalize SATA present functionality naming

This commit makes the naming of SATA related MPP functions consistent
accross SoCs by adjusting the Armada 39x definition to use "prsnt"
instead of "present".

Since only the subnames are changed, the DT binding is not modified at
all.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:03 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functions

This commit makes the dram functions naming (both the name and
subname) consistent accross SoC, by using:

  dram(vttctrl)
  dram(deccerr)

in all Marvell SoCs.

Due to the change to the name, it changes the DT binding, but these
functions are not used by any in-tree Device Tree file, and are very
unlikely to be used by anyone.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:02 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnames

The subnames are purely informative, but it's nicer when they match
accross SoCs. This commit adjusts the Armada 375, Armada 38x and
Armada 39x MPP definitions so that the subnames of the PTP pins match
the ones used on Armada XP and Kirkwood.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:01 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs

The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and
a second one of 27 GPIOs. However, since there is a total of 60 MPP
pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v4.1+
Fixes: ee086577abe7f ("pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs
Thomas Petazzoni [Tue, 9 Jun 2015 16:47:00 +0000 (18:47 +0200)]
pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs

The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and
a second one of 27 GPIOs. However, since there is a total of 60 MPP
pins that can be muxed as GPIOs, the second bank really has 28 GPIOs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-375: remove incorrect space in pin description
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:59 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-375: remove incorrect space in pin description

There was an incorrect space in the definition of the function of one
pin in the Armada 375 pinctrl driver, which this commit fixes.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: fix functions of MPP48
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:58 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-xp: fix functions of MPP48

There was a mistake in the definition of the functions for MPP48 on
Marvell Armada XP. The second function is dev(clkout), and not tclk.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:57 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions

The latest version of the Armada XP datasheet no longer documents the
VDD cpu_pd functions, which might indicate they are not working and/or
not supported. This commit ensures the pinctrl driver matches the
datasheet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-xp: remove non-existing NAND pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:56 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-xp: remove non-existing NAND pins

After updating to a more recent version of the Armada XP datasheet, we
realized that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-375: remove non-existing NAND re/we pins
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:55 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins

After updating to a more recent version of the Armada 375, we realized
that some of the pins documented as having a NAND-related
functionality in fact did not have such functionality. This commit
updates the pinctrl driver accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-370: fix spi0 pin description
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:54 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-370: fix spi0 pin description

Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly
named "spi0-1" instead of just "spi0". This commit fixes that.

This DT binding change does not affect any of the in-tree users.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.7+
Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mvebu: armada-38x: fix PCIe functions
Thomas Petazzoni [Tue, 9 Jun 2015 16:46:53 +0000 (18:46 +0200)]
pinctrl: mvebu: armada-38x: fix PCIe functions

A new revision of the Marvell Armada 38x hardware datasheet unveiled
that the definition of some of the PCIe functions were not
correct. This commit fixes the pinctrl driver accordingly.

Some PCIe functions simply do not exist, some of the PCIe functions in
fact were corresponding to other functions, and some PCIe functions
have been added.

Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related:
this function is in fact implemented on MPP43, instead of a PCIe
function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.15+
Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: don't print unavailable function groups
Ludovic Desroches [Mon, 8 Jun 2015 15:16:37 +0000 (17:16 +0200)]
pinctrl: don't print unavailable function groups

There is no reason to try to print groups associated to a function if
get_function_groups returns an error. Moreover, it can lead to a NULL
pointer dereference error.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: dt-binding: Add DT binding documentation for MSM8660
Bjorn Andersson [Fri, 5 Jun 2015 22:52:24 +0000 (15:52 -0700)]
pinctrl: dt-binding: Add DT binding documentation for MSM8660

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: qcom: Add MSM8660 pinctrl definitions
Bjorn Andersson [Fri, 5 Jun 2015 22:52:23 +0000 (15:52 -0700)]
pinctrl: qcom: Add MSM8660 pinctrl definitions

Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: berlin: comment the spi functions
Antoine Tenart [Tue, 2 Jun 2015 09:37:48 +0000 (11:37 +0200)]
pinctrl: berlin: comment the spi functions

Add comments for the SPI functions, to distinguish CLK, SDI, SDO and
C{0,1,2,3}n.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: berlin: fix spi1 SS0n function name
Antoine Tenart [Tue, 2 Jun 2015 09:37:47 +0000 (11:37 +0200)]
pinctrl: berlin: fix spi1 SS0n function name

Rename function ss0 to spi1 to be consistent with the other Berlin
function names.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sunxi: Add allwinner A33 PIO controller support
Vishnu Patekar [Tue, 2 Jun 2015 09:08:40 +0000 (11:08 +0200)]
pinctrl: sunxi: Add allwinner A33 PIO controller support

A33 PIO has 7 ports which starts from PB and has two interrupt ports.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: samsung: Fix the pointer in PTR_ERR()
Fabio Estevam [Mon, 1 Jun 2015 12:57:04 +0000 (09:57 -0300)]
pinctrl: samsung: Fix the pointer in PTR_ERR()

PTR_ERR should access the value just tested by IS_ERR

The semantic patch that makes this change is available
in scripts/coccinelle/tests/odd_ptr_err.cocci.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: Remove .owner field
Fabio Estevam [Mon, 1 Jun 2015 12:53:59 +0000 (09:53 -0300)]
pinctrl: Remove .owner field

platform_driver does not need to set the owner field, as it will be
populated by the driver core, so just remove it.

The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: fix confusing debug message in pinctrl_register_map()
Masahiro Yamada [Thu, 28 May 2015 12:52:59 +0000 (21:52 +0900)]
pinctrl: fix confusing debug message in pinctrl_register_map()

There are two types for pinctrl maps: pinmux and pinconfig
This debug message shows the number of maps of both types.
The string "pinmux map" is not precise.  Let's say "pinctrl map"
instead.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[also fixed %d -> %u]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: zynq: add static const to zynq_pctrl_groups
Masahiro Yamada [Thu, 28 May 2015 12:57:53 +0000 (21:57 +0900)]
pinctrl: zynq: add static const to zynq_pctrl_groups

This array is only referenced in this file and never updated.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: zynq: add static to zynq_pins
Masahiro Yamada [Thu, 28 May 2015 12:57:23 +0000 (21:57 +0900)]
pinctrl: zynq: add static to zynq_pins

This array is only referenced in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: Fix pinctrl register irq fail bug.
Hongzhou Yang [Wed, 27 May 2015 09:43:55 +0000 (02:43 -0700)]
pinctrl: mediatek: Fix pinctrl register irq fail bug.

Since mt6397 is no need to support interrupt controller,
I judged "interrupt-controller" property to skip it last patch.
But the if judgement should on the contrary, this is a bug.

And find of_property_read_bool is better for this case.
So using of_property_read_bool instead of of_find_property.

Also fix bug of misuse pointer.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Reviewed-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: Fix bug of ies/smt setting for mt8173.
Hongzhou Yang [Wed, 27 May 2015 09:43:54 +0000 (02:43 -0700)]
pinctrl: mediatek: Fix bug of ies/smt setting for mt8173.

Add ies/smt support for MSDC3.
Also fix ies bug for pin 106 and 107.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: Spelling s/reseved/reserved/
Geert Uytterhoeven [Thu, 21 May 2015 12:05:10 +0000 (14:05 +0200)]
pinctrl: Spelling s/reseved/reserved/

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: use "const struct ..." rather than "struct ... const"
Masahiro Yamada [Fri, 22 May 2015 06:25:50 +0000 (15:25 +0900)]
pinctrl: use "const struct ..." rather than "struct ... const"

Only this member, pins, is defined as "struct ... const *", but the
others in this struct, pinlops, pmxops, confops, etc. are defined as
"const struct ... *".

Swap the "struct pinctrl_pin_desc" and "const" for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: remove useless const qualifier
Masahiro Yamada [Fri, 22 May 2015 06:19:37 +0000 (15:19 +0900)]
pinctrl: remove useless const qualifier

This "const" claims the get_function_groups callback never
changes the given num_groups pointer.  It is always true
in C language, so not worth mentioning.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL
Masahiro Yamada [Wed, 20 May 2015 08:42:31 +0000 (17:42 +0900)]
pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL

The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830,
0xf8000834, respectively.

Each offset address must be prefixed with 0x.

Fixes: add958cee967 "pinctrl: Add driver for Zynq"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro
Masahiro Yamada [Wed, 20 May 2015 08:42:30 +0000 (17:42 +0900)]
pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro

The offset to the mux register is missing.

Fixes: add958cee967 "pinctrl: Add driver for Zynq"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: tegra-xusb: Fix allocation of pins
Jon Hunter [Wed, 27 May 2015 13:11:54 +0000 (14:11 +0100)]
pinctrl: tegra-xusb: Fix allocation of pins

Commit e5b3b2d9ed20 ("pinctrl: allows not to define the get_group_pins
operation") allows pin controllers not to register the get_group_pins()
function. However, a side-effect of not registering this function is
that pins are not allocated and potentially multiple devices could
attempt to configure the same pins [1]. Although this problem exists in
the pinctrl core, because only a few devices are impacted by this, fix
this for tegra-xusb by adding the get_group_pins() function.

Please note that in addition to adding the get_group_pins() functions
the pins/lanes for the tegra-xusb also need to be registered when
calling pinctrl_register(). This also allows the current pinmux state
to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad
controller.

[1] http://www.spinics.net/lists/linux-gpio/msg05810.html

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: tegra-xusb: Remove unused structure
Jon Hunter [Wed, 27 May 2015 13:11:53 +0000 (14:11 +0100)]
pinctrl: tegra-xusb: Remove unused structure

The structure tegra_xusb_padctl_group is defined but never used and so
remove this.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: improve debugfs for strict controllers
Linus Walleij [Thu, 28 May 2015 08:11:19 +0000 (10:11 +0200)]
pinctrl: improve debugfs for strict controllers

If we know we are using a strict pin controller (one that cannot
mix device functions+group use and GPIO) we can be a bit more
specific in debugfs, just print either device-function-group
or GPIO consumer for the pin. Let's do that to be helpful.

Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: add OF dependency to MT6397
Linus Walleij [Wed, 20 May 2015 07:11:23 +0000 (09:11 +0200)]
pinctrl: mediatek: add OF dependency to MT6397

X86_64 allmodconfig screams like so:
warning: (PINCTRL_MT6397) selects PINCTRL_MTK_COMMON
which has unmet direct dependencies
(PINCTRL && (ARCH_MEDIATEK || COMPILE_TEST) && OF)

So add OF to dependencies to shut up this warning.

Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: r8a7791: Add PWM pin groups and functions
Yoshihiro Shimoda [Mon, 18 May 2015 01:41:05 +0000 (10:41 +0900)]
pinctrl: sh-pfc: r8a7791: Add PWM pin groups and functions

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sirf: add sirf atlas7 pinctrl and gpio support
Wei Chen [Mon, 18 May 2015 07:28:32 +0000 (07:28 +0000)]
pinctrl: sirf: add sirf atlas7 pinctrl and gpio support

The Pinctrl module (ioc) controls the Pad's function select
(each pad can have 8 functions), Pad's Drive Strength, Pad's
Pull Select and Pad's Input Disable status.

The ioc has two modules, ioc_top & ioc_rtc. Both of these two
modules have function select/clear, Pull select and Drive
Strength registers. But only ioc_rtc has input-disable
registers. The Pads on ioc_top have to access ioc_rtc to set
their input-disable status and intpu-disable-value.

So have to use one ioc driver instance to drive these two
ioc modules at the same time, and each ioc module will be
treat as one bank on the "IOC Device".

The GPIO Controller controls the GPIO status if the Pad has
been config as GPIO by Pinctrl already. Includes the GPIO
Input/output, Interrupt type, Interrupt Status, and Set/Get
Values.
The GPIO pull up/down are controlled by Pinctrl.

There are 7 GPIO Groups and splited into 3 MACROs in atlas7.
The GPIO Groups in one MACRO share one GPIO controllers, each
GPIO Group are treated as one GPIO bank.

For example:
In VDIFM macro, there is one GPIO Controller, it has 3 banks
to control 3 gpio groups. Its gpio name space is from 0 to 95.

The Device Tree can be written as following:

gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>,
<&pinctrl 64 0 0>;

gpio-ranges-group-names = "gnss_gpio_grp",
"lcd_vip_gpio_grp",
"sdio_i2s_gpio_grp";

bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp".
bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp".
bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp".

Signed-off-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: zynq: add static to platform_driver remove callback
Masahiro Yamada [Fri, 15 May 2015 03:31:38 +0000 (12:31 +0900)]
pinctrl: zynq: add static to platform_driver remove callback

This function is only referenced in this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: r8a7790: Add PWM pin groups and functions
Yoshihiro Shimoda [Thu, 14 May 2015 10:48:54 +0000 (19:48 +0900)]
pinctrl: sh-pfc: r8a7790: Add PWM pin groups and functions

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: add pinctrl/GPIO/EINT driver for mt8127
Yingjoe Chen [Tue, 19 May 2015 03:01:32 +0000 (20:01 -0700)]
pinctrl: mediatek: add pinctrl/GPIO/EINT driver for mt8127

MT8127 pinctrl/eint are similar to mt8135 and mt8173, add
support for mt8127 using mediatek common pinctrl driver.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: Add Pinctrl/GPIO driver for mt6397.
Hongzhou Yang [Tue, 19 May 2015 06:11:17 +0000 (23:11 -0700)]
pinctrl: mediatek: Add Pinctrl/GPIO driver for mt6397.

Add mt6397 support using mediatek common pinctrl driver.

mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip.
Pinctrl/GPIO driver should obtain regmap from PMIC,
so adding this support to common code.

Also, mt6397 is no need to support interrupt controller,
so changing common code to skip it.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: add ies/smt control to common code.
Hongzhou Yang [Tue, 19 May 2015 06:11:16 +0000 (23:11 -0700)]
pinctrl: mediatek: add ies/smt control to common code.

Input enable and smt setting have different register,
modify code to fix it.

Several mediatek soc use similar input enable/smt setting
procedure as mt8173, some soc use generic input enable/smt
setting, some soc has no input enable/smt setting. Adding
common code to handle all those cases, so future soc driver
can use it.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg common code
Yingjoe Chen [Tue, 19 May 2015 06:11:15 +0000 (23:11 -0700)]
pinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg common code

Several mediatek soc use similar pull setting procedure as mt8173,
the pupd enable and resistance setting are in the same register.
Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set
in mt8173 to handle this case, so future soc driver can use it.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: data struct optimize and remove unused member
Yingjoe Chen [Tue, 19 May 2015 06:11:14 +0000 (23:11 -0700)]
pinctrl: mediatek: data struct optimize and remove unused member

struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset
and mtk_pinctrl_devdata.chip_type are never used in code.
Remove them.

Some per-pin data are using int for pin number and offsets.
Change to short and rearrange to reduce const data size.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mt6397: Add pinfunc header file for mt6397.
Hongzhou Yang [Tue, 19 May 2015 03:01:27 +0000 (20:01 -0700)]
pinctrl: mt6397: Add pinfunc header file for mt6397.

Add pinfunc header file, mt8135/mt8173 relate dts will include it.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: mediatek: Modify pinctrl bindings for mt6397.
Hongzhou Yang [Tue, 19 May 2015 06:11:12 +0000 (23:11 -0700)]
pinctrl: mediatek: Modify pinctrl bindings for mt6397.

Since 6397 is no need to support interrupt controller,
moving interrupt controller relate property to optional list.
Also adding mt8173 and mt8127 to bindings.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: lpc18xx: add the missing group function map
Joachim Eastwood [Thu, 14 May 2015 12:45:58 +0000 (14:45 +0200)]
pinctrl: lpc18xx: add the missing group function map

Add the required group function map and fill it at probe using
the pin capabilities information already present in the driver.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: cygnus: fixed typo in the gpio driver
Ray Jui [Thu, 14 May 2015 00:06:22 +0000 (17:06 -0700)]
pinctrl: cygnus: fixed typo in the gpio driver

Fixed a small typo in the Cygnus GPIO driver

Signed-off-by: Jason Uy <jasonuy@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: Add Pistachio SoC pin control driver
Andrew Bresticker [Wed, 6 May 2015 19:59:03 +0000 (12:59 -0700)]
pinctrl: Add Pistachio SoC pin control driver

Add a driver for the pin controller present on the IMG Pistachio SoC.
This driver provides pinmux and pinconfig operations as well as GPIO
and IRQ chips for the GPIO banks.

Changes from v4:
 - Switched to using gpiochip_add_pin_range().
 - Fixed up Kconfig entry.
Changes from v3:
 - Addressed review comments from Ezequiel.
Changes from v2:
 - Removed module stuff which would be compiled out.
Changes from v1:
 - Addressed review comments from Linus.
 - Changed compatible string to "img,pistachio-system-pinctrl".
 - Look for GPIO sub-nodes by name.
 - A couple of bug fixes.

Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: lpc18xx: create pin cap lookup helper
Joachim Eastwood [Wed, 6 May 2015 17:11:21 +0000 (19:11 +0200)]
pinctrl: lpc18xx: create pin cap lookup helper

Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based
on the pin number. Create a common helper function that both
functions can use that also handles the case where no pin number is
found in the pins array.

This also fixes a small bug in pconf_get_pin where pconf_get_i2c0
would use the pins array index rather than the pin number.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: r8a73a4: Remove obsolete multi-platform check
Geert Uytterhoeven [Tue, 28 Apr 2015 10:15:06 +0000 (12:15 +0200)]
pinctrl: sh-pfc: r8a73a4: Remove obsolete multi-platform check

As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic ARM
multi-platform builds.  Hence CONFIG_ARCH_MULTIPLATFORM is always set,
and the check can be removed.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation
Ulrich Hecht [Tue, 12 May 2015 09:13:21 +0000 (11:13 +0200)]
pinctrl: sh-pfc: Add renesas,pfc-r8a7793 to binding documentation

Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: Enable building of r8a7793 PFC support
Ulrich Hecht [Tue, 12 May 2015 09:13:20 +0000 (11:13 +0200)]
pinctrl: sh-pfc: Enable building of r8a7793 PFC support

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: Add r8a7793 support
Ulrich Hecht [Tue, 12 May 2015 09:13:19 +0000 (11:13 +0200)]
pinctrl: sh-pfc: Add r8a7793 support

Regarding pin control, r8a7791 and r8a7793 are identical, so it is
sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: r8a7740: Fix typo SCIFAB in comment
Geert Uytterhoeven [Mon, 4 May 2015 14:40:46 +0000 (16:40 +0200)]
pinctrl: sh-pfc: r8a7740: Fix typo SCIFAB in comment

The last serial port is called "SCIFB", not "SCIFAB".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support
Mika Westerberg [Thu, 7 May 2015 09:54:59 +0000 (12:54 +0300)]
pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support

Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller
Hub). It has slightly different pin configuration compared to the LP
version. This patch adds support for Sunrisepoint-H to the existing
pinctrl-sunrisepoint.c driver.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: Grammar s/used in as/used as/
Geert Uytterhoeven [Mon, 4 May 2015 17:46:57 +0000 (19:46 +0200)]
pinctrl: Grammar s/used in as/used as/

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: sh-pfc: Remove r8a73a4 platform_device_id entry
Geert Uytterhoeven [Tue, 28 Apr 2015 10:15:07 +0000 (12:15 +0200)]
pinctrl: sh-pfc: Remove r8a73a4 platform_device_id entry

As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic DT-only ARM
multi-platform builds.  The driver doesn't need to match platform
devices by name anymore, hence remove the corresponding
platform_device_id entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: use ERR_CAST instead of ERR_PTR/PTR_ERR
Fabian Frederick [Mon, 27 Apr 2015 16:04:05 +0000 (18:04 +0200)]
pinctrl: use ERR_CAST instead of ERR_PTR/PTR_ERR

Inspired by scripts/coccinelle/api/err_cast.cocci

Signed-off-by: Fabian Frederick <fabf@skynet.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agogpio: Constify irq_domain_ops
Krzysztof Kozlowski [Mon, 27 Apr 2015 12:54:07 +0000 (21:54 +0900)]
gpio: Constify irq_domain_ops

The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: single: Constify irq_domain_ops
Krzysztof Kozlowski [Mon, 27 Apr 2015 12:54:06 +0000 (21:54 +0900)]
pinctrl: single: Constify irq_domain_ops

The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: imx: Allow parsing DT without function nodes
Markus Pargmann [Fri, 10 Apr 2015 14:22:38 +0000 (16:22 +0200)]
pinctrl: imx: Allow parsing DT without function nodes

The old format to define pinctrl settings for imx in DT has two
hierarchy levels. The first level are function device nodes. The second
level are pingroups which contain a property fsl,pins. The original
intention was to define all pin functions in a single dtsi file and just
reference the correct ones in the board files.
This idea was rejected some time ago leading to the current design to
have all the pinfunctions defined in the board files. So we don't need
the function device nodes anymore.

This patch changes the pinctrl driver to accept devicetrees which do not
have the first hierarchy level, function device nodes. For example
karo-tx25 already has such a devicetree. Old devicetrees are still
parsed and supported.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: zynq: configure SPI SSx pins separately
Helmut Buchsbaum [Sun, 26 Apr 2015 09:32:47 +0000 (11:32 +0200)]
pinctrl: zynq: configure SPI SSx pins separately

Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.

This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:

pinctrl_spi0_default: spi0-default {
mux_spi {
function = "spi0";
groups = "spi0_0_grp";
};

mux_ss {
function = "spi0_ss";
groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
}

conf-output {
pins = "MIO16", "MIO21";
slew-rate = <0>;
bias-disable;
low-power-disable;
io-standard = <1>;
};

conf-input {
pins = "MIO17";
slew-rate = <0>;
bias-high-impedance;
low-power-disable;
io-standard = <1>;
};

conf-select {
pins = "MIO18", "MIO19";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};

pinctrl_gpio0_default {
mux {
function = "gpio0";
groups = "gpio0_20_grp"
};

conf {
pins = "MIO20";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};

Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: nomadik: assign chips dynamically
Linus Walleij [Wed, 6 May 2015 12:46:40 +0000 (14:46 +0200)]
pinctrl: nomadik: assign chips dynamically

Assign GPIO chip and irqchip to the GPIO container dynamically,
so we can set a unique name for each GPIO irqchip and see what
chip the hwirq offset actually relates to.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: nomadik: activate strict mux mode
Linus Walleij [Wed, 6 May 2015 12:43:45 +0000 (14:43 +0200)]
pinctrl: nomadik: activate strict mux mode

This activates strict mode muxing for the Nomadik pin controllers,
as these do not allow GPIO and functions to use the same pin
simultaneously.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: move strict option to pinmux_ops
Linus Walleij [Wed, 6 May 2015 12:19:13 +0000 (14:19 +0200)]
pinctrl: move strict option to pinmux_ops

While the pinmux_ops are ideally just a vtable for pin mux
calls, the "strict" setting belongs so intuitively with the
pin multiplexing that we should move it here anyway. Putting
it in the top pinctrl_desc makes no sense.

Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: allow exlusive GPIO/mux pin allocation
Sonic Zhang [Thu, 9 Apr 2015 03:13:07 +0000 (11:13 +0800)]
pinctrl: allow exlusive GPIO/mux pin allocation

Disallow simultaneous use of the the GPIO and peripheral mux
functions by setting a flag "strict" in struct pinctrl_desc.

The blackfin pinmux and gpio controller doesn't allow user to
set up a pin for both GPIO and peripheral function. So, add flag
strict in struct pinctrl_desc to check both gpio_owner and
mux_owner before approving the pin request.

v2-changes:
- if strict flag is set, check gpio_owner and mux_onwer in if and
  else clause

v3-changes:
- add kerneldoc for this struct
- augment Documentation/pinctrl.txt

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: add imx7d support
Frank Li [Wed, 29 Apr 2015 14:20:05 +0000 (22:20 +0800)]
pinctrl: add imx7d support

Add i.MX7D pinctrl driver support

Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: Add Pistachio SoC pin control binding document
Andrew Bresticker [Wed, 29 Apr 2015 01:13:01 +0000 (18:13 -0700)]
pinctrl: Add Pistachio SoC pin control binding document

Add a device-tree binding document for the pin controller present
on the IMG Pistachio SoC.

Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: add DT bindings for lpc1850-scu pinctrl driver
Joachim Eastwood [Mon, 27 Apr 2015 22:14:09 +0000 (00:14 +0200)]
pinctrl: add DT bindings for lpc1850-scu pinctrl driver

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: add lpc18xx pinctrl driver
Joachim Eastwood [Mon, 27 Apr 2015 22:14:08 +0000 (00:14 +0200)]
pinctrl: add lpc18xx pinctrl driver

Pinctrl driver for the System Control Unit (SCU) found on NXP
LPC18xx/43xx devices.

Driver uses the generic pinctrl DT bindings for multiplexing
and property settings.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agopinctrl: at91: Add set_multiple GPIO chip feature
Alexander Stein [Thu, 2 Apr 2015 09:55:49 +0000 (11:55 +0200)]
pinctrl: at91: Add set_multiple GPIO chip feature

This adds the callback for set_multiple.

As this controller has a separate set and clear register, we
can't write directly to PIO_ODSR as this would required a cached
variable and would race with at91_gpio_set.

So build masks for the PIO_SODR and PIO_CODR registers and
write them together.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agoLinux 4.1-rc2
Linus Torvalds [Mon, 4 May 2015 02:22:23 +0000 (19:22 -0700)]
Linux 4.1-rc2