Arnd Bergmann [Thu, 7 Jul 2016 13:11:44 +0000 (15:11 +0200)]
Merge tag 'amlogic-dt64-2' of git://git./linux/kernel/git/khilman/linux-amlogic into next/dt64
Merge "Amlogic 64-bit DT updates" from Kevin Hilman:
- add RNG and new clock driver support
* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: DTS: meson-gxbb: switch ethernet to real clock
arm64: dts: gxbb clock controller
ARM64: dts: meson-gxbb: Add Hardware Random Generator node
dt-bindings: hwrng: Add Amlogic Meson Hardware Random Generator bindings
Arnd Bergmann [Thu, 7 Jul 2016 12:18:17 +0000 (14:18 +0200)]
Merge tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu into next/dt64
Merge "mvebu dt64 for 4.8 (part 1)" from Gregory CLEMENT:
- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
- update dt with the clocks found in the Armada 3700 SoCs
* tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add peripherals clocks for Armada 37xx
arm64: dts: marvell: add tbg clocks for Armada 37xx
arm64: dts: marvell: Add xtal clock support for Armada 3700
arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
Arnd Bergmann [Thu, 7 Jul 2016 11:58:44 +0000 (13:58 +0200)]
Merge tag 'v4.7-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt64
Merge "ARM: mediatek: dts 64 bit updates for v4.8" from Matthias Brugger:
- Add nodes for the DISP function ports
- Add dt-bindings for mt6755
- Add basic support for mt6755 SoC
* tag 'v4.7-next-dts' of https://github.com/mbgg/linux-mediatek:
arm64: dts: mediatek: add mt6755 support
Document: DT: Add bindings for mediatek MT6755 SoC Platform
arm64: dts: mt8173: Add display subsystem related nodes
Olof Johansson [Thu, 7 Jul 2016 05:23:27 +0000 (22:23 -0700)]
Merge tag 'v4.8-rockchip-dts64-1' of git://git./linux/kernel/git/mmind/linux-rockchip into next/dt64
The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.
* tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
arm64: dts: rockchip: add i2c nodes for rk3399
arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
arm64: dts: rockchip: add rk3399 io-domain core nodes
arm64: dts: rockchip: add rk3368-r88 iodomains
arm64: dts: rockchip: add rk3368 io-domain core nodes
arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
arm64: dts: rockchip: enable eMMC for rk3399 EVB
arm64: dts: rockchip: add sdhci/emmc for rk3399
arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
arm64: dts: rockchip: assign default rates for core rk3399 clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 6 Jul 2016 04:47:46 +0000 (21:47 -0700)]
Merge tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8
- name the GPIO lines
* tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hikey: name the GPIO lines
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 6 Jul 2016 04:10:09 +0000 (21:10 -0700)]
Merge tag 'imx-dt64-4.8' of git://git./linux/kernel/git/shawnguo/linux into next/dt64
The Freescale arm64 device tree updates for 4.8:
- Update address-cells and reg properties of cpu nodes, considering
MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
and ls2080a
- Adds the cache nodes and next-level-cache property for ls1043a and
ls2080a to get cacheinfo work on these platforms
- Add dma-coherent for ls1043a PCI nodes to utilize the hardware
capability on data coherency
- Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
detection in P3 PHY mode
* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add cache nodes for cacheinfo support
arm64: dts: ls1043a: Add cache nodes for cacheinfo support
arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
bindings: PCI: layerscape: Add 'dma-coherent' property
arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: fsl: Update address-cells and reg properties of cpu nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 5 Jul 2016 05:24:30 +0000 (22:24 -0700)]
Merge tag 'qcom-arm64-for-4.8' of git://git./linux/kernel/git/agross/linux into next/dt64
Qualcomm ARM64 Updates for v4.8
* Enable assorted peripherals on APQ8016 SBC
* Update reserved memory on MSM8916
* Add MSM8996 peripheral support
* Add SCM firmware node on MSM8916
* Add PMU node on MSM8916
* Add PSCI cpuidle support on MSM8916
* tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (22 commits)
arm64: dts: msm8996: add sdc2 support
arm64: dts: msm8996: add sdc2 pinctrl
arm64: dts: msm8996: add support to blsp2_spi5
arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
arm64: dts: msm8996: add support to blsp1_spi0
arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
arm64: dts: msm8996: add support to blsp2_i2c0
arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
arm64: dts: msm8996: add support to blsp2_i2c1
arm64: dts: msm8996: add blsp2_i2c1 pinctrl
arm64: dts: msm8996: add support to blsp1_i2c2 device
arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
arm64: dts: msm8996: add support blsp2_uart2
arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
arm64: dts: msm8996: add blsp2_uart1 pinctrl
arm64: dts: msm8996: add msmgpio label
ARM: dts: msm8916: Update reserved-memory
arm64: dts: msm8916: Add SCM firmware node
arm64: dts: qcom: Add msm8916 PMU node
ARM64: dts: Add PSCI cpuidle support for MSM8916
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 5 Jul 2016 04:33:31 +0000 (21:33 -0700)]
Merge tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64
First part of X-Gene DTS changes queued for v4.8
The changes include:
+ 2 clean-up and style-fix patches from Bjorn
+ Correct timer interrupt polarity for X-Gene 2
+ Remove unused qmlclk node on X-Gene 1
* tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next:
arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
arm64: dts: apm: Remove leading '0x' from unit addresses
arm64: dts: apm: Use lowercase consistently for hex constants
Signed-off-by: Olof Johansson <olof@lixom.net>
Gregory CLEMENT [Wed, 25 May 2016 11:42:43 +0000 (13:42 +0200)]
arm64: dts: marvell: add peripherals clocks for Armada 37xx
Add two new blocks of clocks. The peripheral clocks are the source clocks
of the peripheral of the Armada 3700 SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Gregory CLEMENT [Tue, 17 May 2016 09:28:04 +0000 (11:28 +0200)]
arm64: dts: marvell: add tbg clocks for Armada 37xx
Add a new block of clocks. The Time Base Generators clocks can be the
parent of the peripheral clocks.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Gregory CLEMENT [Wed, 25 May 2016 11:25:52 +0000 (13:25 +0200)]
arm64: dts: marvell: Add xtal clock support for Armada 3700
The configuration of the clock depend of the gpio latch. This information
is stored in the gpio block registers. That's why the block is shared
using a syscon node.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Mars Cheng [Wed, 29 Jun 2016 02:09:33 +0000 (10:09 +0800)]
arm64: dts: mediatek: add mt6755 support
This adds basic chip support for MT6755 SoC.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Mars Cheng [Wed, 29 Jun 2016 02:09:32 +0000 (10:09 +0800)]
Document: DT: Add bindings for mediatek MT6755 SoC Platform
This adds DT binding documentation for Mediatek MT6755.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Thomas Petazzoni [Thu, 16 Jun 2016 12:28:36 +0000 (14:28 +0200)]
arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thomas Petazzoni [Thu, 16 Jun 2016 12:28:35 +0000 (14:28 +0200)]
arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
As suggested by Rob Herring, we should:
1/ Use a SoC-specific compatible string in addition to the more generic
one.
2/ The generic compatible string has been changed from
"marvell,mv-xor-v2" to "marvell,xor-v2".
We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Linus Walleij [Thu, 23 Jun 2016 23:06:04 +0000 (01:06 +0200)]
arm64: dts: hikey: name the GPIO lines
This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".
This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.
Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.
Cc: devicetree@vger.kernel.org
Cc: John Stultz <john.stultz@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Douglas Anderson [Tue, 14 Jun 2016 20:21:11 +0000 (13:21 -0700)]
arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.
These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.
Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Srinivas Kandagatla [Tue, 21 Jun 2016 17:39:53 +0000 (18:39 +0100)]
arm64: dts: msm8996: add sdc2 support
This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:12 +0000 (16:14 +0100)]
arm64: dts: msm8996: add sdc2 pinctrl
This patch adds pinctrl required for sdhci for external sd card
controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:11 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp2_spi5
This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:10 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
This patch adds pinctrl required for blsp2_spi5 device.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:09 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp1_spi0
This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:08 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
This patch adds pinctrl nodes required for blsp1_spi0.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:07 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp2_i2c0
This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:06 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
This patch adds support to blsp2_i2c0 pinctrl.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:05 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp2_i2c1
This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:04 +0000 (16:14 +0100)]
arm64: dts: msm8996: add blsp2_i2c1 pinctrl
This patch adds support to blsp2_i2c1 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:03 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support to blsp1_i2c2 device
This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:02 +0000 (16:14 +0100)]
arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
This patch adds pinctrl nodes required for blsp1_i2c2.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:01 +0000 (16:14 +0100)]
arm64: dts: msm8996: add support blsp2_uart2
This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:14:00 +0000 (16:14 +0100)]
arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
This patch adds blsp2_uart2 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:13:59 +0000 (16:13 +0100)]
arm64: dts: msm8996: add blsp2_uart1 pinctrl
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Fri, 17 Jun 2016 15:13:58 +0000 (16:13 +0100)]
arm64: dts: msm8996: add msmgpio label
This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Kevin Hilman [Tue, 14 Jun 2016 19:03:39 +0000 (12:03 -0700)]
ARM64: DTS: meson-gxbb: switch ethernet to real clock
With the clock driver upstream, switch to the real clock.
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Michael Turquette [Thu, 23 Jun 2016 02:12:23 +0000 (19:12 -0700)]
arm64: dts: gxbb clock controller
Add the clock controller node for the AmLogic GXBB machine.
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Douglas Anderson [Mon, 20 Jun 2016 17:56:54 +0000 (10:56 -0700)]
arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Douglas Anderson [Mon, 20 Jun 2016 17:56:48 +0000 (10:56 -0700)]
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Li Yang [Thu, 16 Jun 2016 23:35:04 +0000 (18:35 -0500)]
arm64: dts: ls2080a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Li Yang [Thu, 16 Jun 2016 23:35:03 +0000 (18:35 -0500)]
arm64: dts: ls1043a: Add cache nodes for cacheinfo support
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Duc Dang [Tue, 21 Jun 2016 01:41:49 +0000 (18:41 -0700)]
arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
Node qmlclk has no consumer, so remove it.
Signed-off-by: Duc Dang <dhdang@apm.com>
Duc Dang [Tue, 21 Jun 2016 01:26:35 +0000 (18:26 -0700)]
arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
Correct X-Gene 2 timer interrupt polarity as low-level triggered.
Signed-off-by: Duc Dang <dhdang@apm.com>
Bjorn Helgaas [Tue, 14 Jun 2016 13:00:30 +0000 (08:00 -0500)]
arm64: dts: apm: Remove leading '0x' from unit addresses
Unit addresses should not have a leading '0x'. Remove them.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
Bjorn Helgaas [Tue, 14 Jun 2016 13:00:20 +0000 (08:00 -0500)]
arm64: dts: apm: Use lowercase consistently for hex constants
The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.
Use lowercase consistently for the hex constants. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
Olof Johansson [Mon, 20 Jun 2016 05:48:17 +0000 (22:48 -0700)]
Merge tag 'arm-soc/for-4.8/devicetree-arm64' of github.com/Broadcom/stblinux into next/dt64
This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs
- Dhanajay enables pinctrl for the Northstar2 SoCs
- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
finally adds the CCI-400 and PMU nodes
* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: Add CCI-400 PMU support
arm64: dts: NS2: Add all of the UARTs
arm64: dts: Enable GPIO for Broadcom NS2 SoC
arm64: dts: enable pinctrl for Broadcom NS2 SoC
arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
dt-bindings: ata: add compatible string for iProc AHCI controller
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Mon, 20 Jun 2016 05:30:16 +0000 (22:30 -0700)]
Merge tag 'amlogic-dt64' of git://git./linux/kernel/git/khilman/linux-amlogic into next/dt64
Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
- add reset driver
* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
ARM64: dts: amlogic: gxbb: add ethernet
ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
ARM64: dts: amlogic: add pins for EMMC, SD
ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
documentation: Add compatibles for Amlogic Meson GXBB pin controllers
ARM64: dts: amlogic: Add hiu and periphs buses
Signed-off-by: Olof Johansson <olof@lixom.net>
Caesar Wang [Wed, 18 May 2016 14:41:50 +0000 (22:41 +0800)]
arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
The 2nd additional region is the GIC virtual cpu interface register
base and size.
As the gic400 of rk3368 says, the cpu interface register map as below
:
-0x0000 GICC_CTRL
.
.
.
-0x00fc GICC_IIDR
-0x1000 GICC_IDR
Obviously, the region size should be greater than 0x1000.
So we should make sure to include the GICC_IDR since the kernel will access
it in some cases.
Fixes:
b790c2cab5ca ("arm64: dts: add Rockchip rk3368 core dtsi and board dts for the r88 board")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Cc: stable@vger.kernel.org
[added Fixes and stable-cc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
David Wu [Mon, 16 May 2016 20:09:31 +0000 (13:09 -0700)]
arm64: dts: rockchip: add i2c nodes for rk3399
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals. Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.
Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates. 200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
their i2c bus was slow anyway. Since we gate the functional clock
when the i2c bus is not active, power savings would only be while i2c
transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
clock to make divisions work out perfectly, accounting for the rise /
fall time measured on an actual board.
Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Liu Gang [Tue, 7 Jun 2016 06:55:46 +0000 (14:55 +0800)]
arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Liu Gang [Tue, 7 Jun 2016 06:55:45 +0000 (14:55 +0800)]
bindings: PCI: layerscape: Add 'dma-coherent' property
Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.
The PCI IP block of ls1043a has this capability, so adding
this feature to improve the PCI performance.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Neil Armstrong [Wed, 15 Jun 2016 10:01:46 +0000 (12:01 +0200)]
ARM64: dts: meson-gxbb: Add Hardware Random Generator node
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Wed, 15 Jun 2016 10:01:45 +0000 (12:01 +0200)]
dt-bindings: hwrng: Add Amlogic Meson Hardware Random Generator bindings
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Masahiro Yamada [Tue, 14 Jun 2016 03:01:43 +0000 (12:01 +0900)]
arm64: dts: uniphier: add /memreserve/ for spin-table release address
As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Masahiro Yamada [Tue, 14 Jun 2016 03:01:42 +0000 (12:01 +0900)]
arm64: dts: uniphier: change cpu-release-address
At first, 256 byte of the head of DRAM space was reserved for some
reasons. However, as the progress of development, it turned out
unnecessary, and it was never used in the end. Move the CPU release
address to leave no space.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Masahiro Yamada [Tue, 14 Jun 2016 03:01:41 +0000 (12:01 +0900)]
arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Mon, 13 Jun 2016 22:29:12 +0000 (15:29 -0700)]
Merge tag 'renesas-arm64-dt-for-v4.8' of git://git./linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC DT Updates for v4.8
* Fix W=1 dtc warnings and other cleanups
* Enable watchdog timer
* Enable DMA for I2C
* Increase the size of GIC-400 mapped registers: be nicer to hypervisors
* Support RTS/CTS hardware flow control
* tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: Drop 0x from unit address of gic
arm64: dts: salvator-x: Fix W=1 dtc warnings
arm64: dts: r8a7795: Fix W=1 dtc warnings
arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
arm64: dts: salvator-x: Enable watchdog timer
arm64: dts: r8a7795: Add RWDT node
arm64: dts: r8a7795: enable DMA for I2C
arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control
Signed-off-by: Olof Johansson <olof@lixom.net>
Bjorn Andersson [Tue, 7 Jun 2016 00:57:24 +0000 (17:57 -0700)]
ARM: dts: msm8916: Update reserved-memory
Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Andy Gross [Fri, 3 Jun 2016 23:25:28 +0000 (18:25 -0500)]
arm64: dts: msm8916: Add SCM firmware node
This adds the devicetree node for the SCM firmware.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Tue, 10 May 2016 22:01:49 +0000 (15:01 -0700)]
arm64: dts: qcom: Add msm8916 PMU node
Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Lina Iyer [Tue, 1 Mar 2016 21:15:30 +0000 (14:15 -0700)]
ARM64: dts: Add PSCI cpuidle support for MSM8916
Add device bindings for CPUs to suspend using PSCI as the enable-method.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Tested-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Srinivas Kandagatla [Tue, 23 Feb 2016 16:50:45 +0000 (16:50 +0000)]
arm64: dts: qcom: apq8016-sbc: enable bam dma node.
This patch enables bam dma node, dma is used for both tx and rx on spi
and on high speed serial.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Georgi Djakov [Thu, 4 Feb 2016 12:53:22 +0000 (14:53 +0200)]
arm64: dts: apq8016-sbc: Add DT node for the uSD SDHC interface
Add the necessary properties to enable the SD-card on db410c boards.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Rajesh Bhagat [Fri, 10 Jun 2016 06:23:46 +0000 (11:53 +0530)]
arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rajesh Bhagat [Fri, 10 Jun 2016 06:23:45 +0000 (11:53 +0530)]
arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alison Wang [Mon, 9 May 2016 09:06:15 +0000 (17:06 +0800)]
arm64: dts: fsl: Update address-cells and reg properties of cpu nodes
MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Caesar Wang [Wed, 25 May 2016 07:39:35 +0000 (15:39 +0800)]
arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Chanho Min [Wed, 1 Jun 2016 01:39:58 +0000 (10:39 +0900)]
arm64: dts: Add dts files for LG Electronics's lg1313 SoC
Add dtsi file to support lg1313 SoC which based on Cortex-A53.
Also add dts file to support lg1312 reference board which based
on lg1313 SoC.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
CK Hu [Fri, 3 Jun 2016 14:59:29 +0000 (16:59 +0200)]
arm64: dts: mt8173: Add display subsystem related nodes
This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Cawa Cheng <cawa.cheng@mediatek.com>
Signed-off-by: Jie Qiu <jie.qiu@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Neil Armstrong [Mon, 30 May 2016 13:27:17 +0000 (15:27 +0200)]
ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
Update DTSI file to add the reset controller node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Kevin Hilman [Wed, 27 Apr 2016 23:58:25 +0000 (16:58 -0700)]
ARM64: dts: amlogic: gxbb: add ethernet
Add node for ethernet interface and pinctrl pins.
Enable on odroid-C2 and P20x boards.
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Kevin Hilman [Wed, 27 Apr 2016 23:12:28 +0000 (16:12 -0700)]
ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins
for all EE domain UARTs.
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Kevin Hilman [Tue, 26 Apr 2016 21:05:19 +0000 (14:05 -0700)]
ARM64: dts: amlogic: add pins for EMMC, SD
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Carlo Caione [Mon, 2 May 2016 08:02:18 +0000 (10:02 +0200)]
ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
Update DTS and DTSI files to enable the pin controller. We also now
support the blinking blue LED on the Odroid-C2.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Carlo Caione [Mon, 2 May 2016 08:02:16 +0000 (10:02 +0200)]
documentation: Add compatibles for Amlogic Meson GXBB pin controllers
Add the two new compatibles for the Amlogic Meson GXBB pin controllers.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Carlo Caione [Sun, 3 Apr 2016 17:14:41 +0000 (19:14 +0200)]
ARM64: dts: amlogic: Add hiu and periphs buses
Add two new buses in the DTS: hiu and periphs buses.
In the Amlogic S905/GXBB SoC several devices (clock / eth / pin
controllers, etc...) are mapped under these two buses. Add them in the
DT before starting to add new devices.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Jon Mason [Wed, 11 May 2016 22:56:09 +0000 (18:56 -0400)]
arm64: dts: NS2: Add CCI-400 PMU support
Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Jon Mason [Wed, 11 May 2016 22:56:08 +0000 (18:56 -0400)]
arm64: dts: NS2: Add all of the UARTs
Add all of the UARTs present on NS2 and enable them in the SVK device
tree file. Also, do some magic to make sure that uart3 is discovered as
ttyS0 (as that is the console UART).
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Yendapally Reddy Dhananjaya Reddy [Fri, 4 Mar 2016 10:23:30 +0000 (05:23 -0500)]
arm64: dts: Enable GPIO for Broadcom NS2 SoC
This enables the GPIO support for Broadcom NS2 SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Yendapally Reddy Dhananjaya Reddy [Fri, 29 Apr 2016 12:51:39 +0000 (08:51 -0400)]
arm64: dts: enable pinctrl for Broadcom NS2 SoC
This enables the pinctrl support for Broadcom NS2 SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Anup Patel [Mon, 28 Mar 2016 04:48:30 +0000 (10:18 +0530)]
arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
We have one dual-port SATA3 AHCI controller present in
NS2 SoC.
This patch enables SATA3 AHCI controller and SATA3 PHY
for NS2 SoC in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Anup Patel [Mon, 28 Mar 2016 04:48:29 +0000 (10:18 +0530)]
dt-bindings: ata: add compatible string for iProc AHCI controller
The Broadcom iProc SoCs have AHCI compliant SATA controller. This
patch adds common compatible string for AHCI SATA controller on
iProc SoCs.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Heiko Stuebner [Sat, 21 May 2016 17:55:28 +0000 (19:55 +0200)]
arm64: dts: rockchip: add rk3399 io-domain core nodes
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Wed, 29 Jul 2015 14:13:35 +0000 (16:13 +0200)]
arm64: dts: rockchip: add rk3368-r88 iodomains
Add the supply-links according to the R88 schematics.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Sat, 21 May 2016 10:43:27 +0000 (12:43 +0200)]
arm64: dts: rockchip: add rk3368 io-domain core nodes
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Mon, 1 Feb 2016 21:09:03 +0000 (22:09 +0100)]
arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
The general register files do contain a lot of separate functions and
while some really are only registers with a lot of different 1-bit
settings, there are also a lot of them containing some bigger function
blocks. To be able to define these as sub-devices, make them simple-mfds.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: David Wu <david.wu@rock-chips.com>
Brian Norris [Fri, 13 May 2016 22:12:04 +0000 (15:12 -0700)]
arm64: dts: rockchip: enable eMMC for rk3399 EVB
Rockchip's rk3399 evaluation board has eMMC. Let's enable the
newly-added nodes.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Brian Norris [Fri, 13 May 2016 22:12:03 +0000 (15:12 -0700)]
arm64: dts: rockchip: add sdhci/emmc for rk3399
Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to
200 MHz, to support all supported timing modes.
Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably
have a compliant Arasan controller, but let's have a rockchip property
as the canonical backup/precautionary measure. Per Heiko's previous
suggestion, let's not clutter the arasan doc with it.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Brian Norris [Fri, 13 May 2016 22:12:02 +0000 (15:12 -0700)]
arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
Per the examples in
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the
grf node to be a simple-mfd in order to properly enumerate child devices
like our eMMC PHY.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
[directly mimic for the pmugrf, which will need the same change later
and there is no need to pollute commit history with another patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Xing Zheng [Fri, 13 May 2016 20:50:18 +0000 (13:50 -0700)]
arm64: dts: rockchip: assign default rates for core rk3399 clocks
These clocks are all core clocks used by many blocks/peripherals, many
of whose drivers don't set their clock rates at all. Let's assign
reasonable default clock rates for these core clocks, so that these
peripherals get something reasonable by default, and also so that if
child devices want to select a clock rate themselves, their muxes have
some reasonable parent clock rates to branch off of (rather than just
the boot-time defaults).
This helps the eMMC PHY, for one, to get a reasonable ACLK rate.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Simon Horman [Wed, 25 May 2016 01:11:40 +0000 (10:11 +0900)]
arm64: dts: r8a7795: Drop 0x from unit address of gic
Drop 0x from unit address of gic as this is the desired form for
a unit address.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Fri, 20 May 2016 07:10:14 +0000 (09:10 +0200)]
arm64: dts: salvator-x: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /regulator@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /regulator@4 has a unit name, but no reg property
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Fri, 20 May 2016 07:10:13 +0000 (09:10 +0200)]
arm64: dts: r8a7795: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,dvc/dvc@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,dvc/dvc@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,src/src@9 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@7 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@8 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/sound@
ec500000/rcar_sound,ssi/ssi@9 has a unit name, but no reg property
Move the cache-controller nodes under the cpus node, and make their unit
names and reg properties match the MPIDR values.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Fri, 20 May 2016 07:43:02 +0000 (09:43 +0200)]
arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
Hook up the RWDT device node to the SYSC "always-on" PM Domain, for a
more consistent device-power-area description in DT.
Cfr. commit
38dbb45ee4bc ("arm64: dts: r8a7795: Use SYSC "always-on" PM
Domain")
Fixes:
f43838a7ae014cba ("arm64: dts: r8a7795: Add RWDT node")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Wolfram Sang [Fri, 1 Apr 2016 11:56:25 +0000 (13:56 +0200)]
arm64: dts: salvator-x: Enable watchdog timer
This patch enables watchdog timer for Salvator-X board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Wolfram Sang [Fri, 1 Apr 2016 11:56:24 +0000 (13:56 +0200)]
arm64: dts: r8a7795: Add RWDT node
This patch adds the RWDT device node for r8a7795.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Niklas Söderlund [Tue, 17 May 2016 10:28:01 +0000 (12:28 +0200)]
arm64: dts: r8a7795: enable DMA for I2C
Add DMA properties to the I2C nodes.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Pooya Keshavarzi [Tue, 19 Apr 2016 06:29:55 +0000 (08:29 +0200)]
arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
There are some requirements about the GIC-400 memory layout and its
mapping if using 64k aligned base addresses like on r8a7795.
See e.g.
http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=
21550029f709072aacf3b9
Map the whole memory range instead of only 0x2000. This will fix
the issue that some hypervisors, e.g. Xen, fail to handle the
interrupts correctly.
Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 4 May 2016 08:57:58 +0000 (10:57 +0200)]
arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control
On the Salvator-X development board, the RTS and CTS pins of debug
serial-1 port SCIF1 are wired to the CP2102 Serial-USB bridge. Reflect
this in the DTS by adding the "uart-has-rtscts" property to the scif1
device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Linus Torvalds [Sun, 29 May 2016 16:29:24 +0000 (09:29 -0700)]
Linux 4.7-rc1
George Spelvin [Sun, 29 May 2016 12:05:56 +0000 (08:05 -0400)]
hash_string: Fix zero-length case for !DCACHE_WORD_ACCESS
The self-test was updated to cover zero-length strings; the function
needs to be updated, too.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: George Spelvin <linux@sciencehorizons.net>
Fixes:
fcfd2fbf22d2 ("fs/namei.c: Add hashlen_string() function")
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
George Spelvin [Sun, 29 May 2016 05:26:41 +0000 (01:26 -0400)]
Rename other copy of hash_string to hashlen_string
The original name was simply hash_string(), but that conflicted with a
function with that name in drivers/base/power/trace.c, and I decided
that calling it "hashlen_" was better anyway.
But you have to do it in two places.
[ This caused build errors for architectures that don't define
CONFIG_DCACHE_WORD_ACCESS - Linus ]
Signed-off-by: George Spelvin <linux@sciencehorizons.net>
Reported-by: Guenter Roeck <linux@roeck-us.net>
Fixes:
fcfd2fbf22d2 ("fs/namei.c: Add hashlen_string() function")
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / log