Arnd Bergmann [Thu, 27 Apr 2017 19:43:42 +0000 (21:43 +0200)]
Merge tag 'juno-fixes-4.12' of git://git./linux/kernel/git/sudeep.holla/linux into next/dt64
Pull "ARMv8 Juno DT fixes for v4.12" from Sudeep Holla:
1. Couple of fixes to remove device tree warnings introduced with
recently added checks in DTC
2. Add information about L1 and L2 caches to Juno device trees as
CCSIDR-based cacheinfo probing is now removed
* tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: dts: juno: fix PCI bus dtc warnings
Olof Johansson [Wed, 19 Apr 2017 13:33:26 +0000 (06:33 -0700)]
Merge tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.12 (part 2)
- crypto engine description for the Armada 7k/8k SoCs and the boards
using it
- SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
using it
* tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu:
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:33:20 +0000 (06:33 -0700)]
Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon SoC DT updates for 4.12
- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins
* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
arm64: dts: hi6220: Reset the mmc hosts
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:33:14 +0000 (06:33 -0700)]
Merge tag 'zte-dt64-4.12' of git://git./linux/kernel/git/shawnguo/linux into next/dt64
ZTE arm64 device tree updates for 4.12:
- Add mmc devices for ZX296718 SoC and enable those available on
zx296718-evb board.
- Add VOU controller device, output devices HDMI and TVENC, and enable
display support for zx296718-evb board.
- Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
rate clock.
* tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zte: add tvenc device for zx296718
arm64: dts: zte: add vou and hdmi devices for zx296718
arm64: dts: zte: add mmc devices for zx296718
arm64: dts: zte: remove zx296718 pll_vga clock
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:33:08 +0000 (06:33 -0700)]
Merge tag 'imx-dt64-4.12' of git://git./linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.12:
- Add support of LS2088A SoC, which is a derivative of existing
LS2080A SoC, and the major difference is on ARM cores.
- Add support of LS1088A SoC which includes eight Cortex-A53 cores
with 32 KB L1 D-cache and I-cache respectively.
- Add crypto and thermal device support for LS1012A platform.
- Add ECC register region for SATA device on LS1012A, LS1043A and
LS1046A platforms.
* tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
dt-bindings: clockgen: Add compatible string for LS1088A
arm64: dts: Add support for FSL's LS1088A SoC
arm64: dts: ls1012a: add crypto node
arm64: dts: ls1012a: add thermal monitor node
arm64: dts: updated sata node on ls1012a platform
arm64: dts: added ecc register address to sata node on ls1046a
arm64: dts: added ecc register address to sata node on ls1043a
arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC
arm64: dts: freescale: ls2080a: Split devicetree for code resuability
dt-bindings: Add compatible for LS2088A QDS and RDB board
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:33:03 +0000 (06:33 -0700)]
Merge tag 'v4.12-rockchip-dts64-2' of git://git./linux/kernel/git/mmind/linux-rockchip into next/dt64
Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
default memory definition on the px5 eval board. While the bootloader
should already override it with the actual amount, it's better to not
carry around wrong values.
* tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: rockchip: add RK3328 eavluation board devicetree
dt-bindings: document rockchip rk3328-evb board
arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
dt-bindings: add binding for rk3328-grf
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:32:57 +0000 (06:32 -0700)]
Merge tag 'samsung-dt64-4.12' of git://git./linux/kernel/git/krzk/linux into next/dt64
Samsung DeviceTree ARM64 update for v4.12:
1. Add IR, touchscreen and panel to TM2/TM2E boards.
2. Add proper clock frequency properties to DSI nodes.
* tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node
arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board
arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2E
arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boards
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:32:49 +0000 (06:32 -0700)]
Merge tag 'renesas-arm64-dt2-for-v4.12' of https://git./linux/kernel/git/horms/renesas into next/dt64
Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
Corrections:
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
Cleanup:
* Drop _clk suffix from X12 clock node name for r8a7795 SoC
Enhancements:
* Add reset control properties for r8a779[56]
* tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
arm64: dts: r8a7796: Add reset control properties
arm64: dts: r8a7795: Add reset control properties
arm64: dts: r8a7795: Correct SATA device size to 2MiB
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:32:42 +0000 (06:32 -0700)]
Merge tag 'qcom-arm64-for-4.12' of git://git./linux/kernel/git/agross/linux into next/dt64
Qualcomm ARM64 Updates for v4.12
* Fixup MSM8996 SMP2P and add ADSP PIL / SLPI SMP2P node
* Replace PMU compatible w/ A53 specific one
* Add APQ8016 ramoops
* Update MSM8916 hexagon node
* Add PM8994 RTC
* tag 'qcom-arm64-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: msm8996: Add ADSP PIL node
arm64: dts: qcom: pm8994: Add rtc node
arm64: dts: apq8016-sbc: Add ramoops
arm64: dts: qcom: msm8916: Update hexagon node
arm64: dts: msm8996: Add SLPI SMP2P dt node.
arm64: dts: qcom: Replace PMU compatible with a53 specific one
arm64: dts: qcom: msm8996: Fixup smp2p node
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 13:32:35 +0000 (06:32 -0700)]
Merge tag 'tegra-for-4.12-arm64-dt' of git://git./linux/kernel/git/tegra/linux into next/dt64
arm64: tegra: Device tree changes for v4.12-rc1
This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
SDHCI and GPIO. It also enables various features on the P2771 devkit.
A small fix is made to the compatible string list for the flow
controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
* tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Update the Tegra132 flowctrl compatible string
arm64: tegra: Add GPU node for Tegra186
arm64: tegra: Enable IOMMU for host1x on Tegra210
arm64: tegra: Enable VIC on Tegra210
arm64: tegra: Add GPIO expanders on P2771
arm64: tegra: Add power monitors on P2771
arm64: tegra: Add GPIO keys on P2771
arm64: tegra: Enable current monitors on P3310
arm64: tegra: Enable SD/MMC slot on P2771
arm64: tegra: Enable SDHCI controllers on P3110
arm64: tegra: Add initial power tree for P3310
arm64: tegra: Enable ethernet on P3310
arm64: tegra: Enable I2C controllers on P3310
arm64: tegra: Invert the PMC interrupt on P3310
arm64: tegra: Add ethernet support for Tegra186
arm64: tegra: Add PMC controller on Tegra186
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 12:39:41 +0000 (05:39 -0700)]
Merge tag 'sunxi-dt-h5-for-4.12' of https://git./linux/kernel/git/sunxi/linux into next/dt64
Allwinner H5 DT changes for 4.12
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We then have patches to support the H5 boards on top.
* tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
arm64: allwinner: h5: add support for the Orange Pi PC 2 board
arm64: allwinner: h5: add Allwinner H5 .dtsi
ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
arm: sun8i: h3: split Allwinner H3 .dtsi
arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 12:37:37 +0000 (05:37 -0700)]
Merge tag 'sunxi-dt64-for-4.12' of https://git./linux/kernel/git/sunxi/linux into next/dt64
Allwinner arm64 DT changes for 4.12
Some patches to enable the PRCM block in the A64
* tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: add R_PIO pinctrl node
arm64: allwinner: a64: add r_ccu node
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 19 Apr 2017 12:29:37 +0000 (05:29 -0700)]
Merge tag 'amlogic-dt64-redo' of git://git./linux/kernel/git/khilman/linux-amlogic into next/dt64
Amlogic 64-bit DT updates for v4.12
- pinctrl: new pins for audio
- clocks: more clocks exposed for GFX, audio
- new board: Khadas Vim (S905X)
- new board: HwaCom AmazeTV (S905X)
- ethernet phy: add GPIO resets
* tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (41 commits)
ARM64: dts: meson-gx: Add support for HDMI output
ARM64: dts: meson-gx: Add shared CMA dma memory pool
ARM64: dts: meson-gxbb-odroidc2: Enable SARADC node
dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
clk: meson-gxbb: Expose GP0 dt-bindings clock id
clk: meson-gxbb: Add MALI clock IDS
dt-bindings: clk: gxbb: expose i2s output clock gates
ARM64: dts: meson-gxl: add spdif output pins
ARM64: dts: meson-gxl: add i2s output pins
ARM64: dts: meson-gxbb: add spdif output pins
ARM64: dts: meson-gxbb: add i2s output pins
ARM64: dts: meson-gxbb: Add USB Hub GPIO hog
ARM: dts: meson8b: Add gpio-ranges properties
ARM: dts: meson8: Add gpio-ranges properties
ARM64: dts: meson-gxl: Add gpio-ranges properties
ARM64: dts: meson-gxbb: Add gpio-ranges properties
ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL
ARM64: dts: meson-gxl: Add missing pinctrl pins groups
ARM64: dts: meson-gx: Prepend GX generic compatible like other nodes
ARM64: dts: meson-gx: empty line cleanup
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Sudeep Holla [Thu, 13 Apr 2017 09:05:38 +0000 (10:05 +0100)]
arm64: dts: juno: add information about L1 and L2 caches
Commit
a8d4636f96ad ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.
Commit
9a802431c527 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.
This patch adds the information about L1 and L2 caches on all variants
of Juno platform.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Sudeep Holla [Wed, 12 Apr 2017 17:26:21 +0000 (18:26 +0100)]
arm64: dts: juno: fix few unit address format warnings
This patch fixes the following set of warnings on juno.
smb@
08000000 unit name should not have leading 0s
sysctl@020000 simple-bus unit address format error, expected "20000"
apbregs@010000 simple-bus unit address format error, expected "10000"
mmci@050000 simple-bus unit address format error, expected "50000"
kmi@060000 simple-bus unit address format error, expected "60000"
kmi@070000 simple-bus unit address format error, expected "70000"
wdt@0f0000 simple-bus unit address format error, expected "f0000"
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Antoine Tenart [Wed, 29 Mar 2017 12:44:31 +0000 (14:44 +0200)]
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
Enable the cryptographic engine available in the CP110 master on the
Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we
do not support multiple cryptographic engines yet.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Antoine Tenart [Wed, 29 Mar 2017 12:44:30 +0000 (14:44 +0200)]
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
Enable the cryptographic engine available in the CP110 master on the
Armada 7040 DB.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Antoine Tenart [Wed, 29 Mar 2017 12:44:29 +0000 (14:44 +0200)]
arm64: marvell: dts: add crypto engine description for 7k/8k
Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Gregory CLEMENT [Thu, 30 Mar 2017 15:23:04 +0000 (17:23 +0200)]
arm64: dts: marvell: add sdhci support for Armada 7K/8K
Also enable it on the Armada 7040 DB and Armada 8040 DB boards.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Gregory CLEMENT [Thu, 30 Mar 2017 15:23:03 +0000 (17:23 +0200)]
arm64: dts: marvell: add eMMC support for Armada 37xx
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Wang Xiaoyin [Thu, 30 Mar 2017 06:48:03 +0000 (14:48 +0800)]
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
Add pinctrl dtsi file for HiKey960 development board, enable
5 pinmux devices and 1 pinconf device, also include some nodes
of configurations for pins.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Wang Xiaoyin [Thu, 30 Mar 2017 06:48:02 +0000 (14:48 +0800)]
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
Extend drive strength levels of the pins for Hi3660 Soc.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Wei Xu [Tue, 28 Mar 2017 16:03:08 +0000 (00:03 +0800)]
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
Enable the NIC and SAS nodes for the hip07-d05 board
to support related functions.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Wei Xu [Tue, 28 Mar 2017 15:40:40 +0000 (23:40 +0800)]
arm64: dts: hisi: add SAS nodes for the hip07 SoC
Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Wei Xu [Tue, 28 Mar 2017 15:33:25 +0000 (23:33 +0800)]
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
Add the infiniband node to support the RoCE function
on the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Wei Xu [Tue, 28 Mar 2017 15:21:09 +0000 (23:21 +0800)]
arm64: dts: hisi: add network related nodes for the hip07 SoC
Add MDIO, SerDes, Port and realted HNS nodes to support the
network on the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Wei Xu [Tue, 28 Mar 2017 15:10:13 +0000 (23:10 +0800)]
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
Add mbigen nodes for the hip07 SoC those will be used
for the SAS, XGE and PCIe host controllers.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Andy Yan [Fri, 7 Apr 2017 08:19:29 +0000 (16:19 +0800)]
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
Commit
122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change
it to the correct value here.
Fixes:
122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jiancheng Xue [Wed, 29 Mar 2017 06:30:09 +0000 (14:30 +0800)]
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
Add basic dts files for hi3798cv200-poplar board. Poplar is the
first development board compliant with the 96Boards Enterprise
Edition TV Platform specification. The board features the
Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53
processor and high performance Mali T720 GPU.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Jiancheng Xue [Wed, 29 Mar 2017 06:30:08 +0000 (14:30 +0800)]
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
Add bindings for HiSilicon hi3798cv200 SoC and Poplar Board.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Daniel Lezcano [Thu, 16 Mar 2017 14:03:24 +0000 (15:03 +0100)]
arm64: dts: hi6220: Reset the mmc hosts
The MMC hosts could be left in an unconsistent or uninitialized state from
the firmware. Instead of assuming, the firmware did the right things, let's
reset the host controllers.
This change fixes a bug when the mmc2/sdio is initialized leading to a hung
task:
[ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds.
[ 242.711129] Not tainted
4.9.0-rc8-00017-gcf0251f #3
[ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 242.724435] kworker/7:1 D 0 675 2 0x00000000
[ 242.729973] Workqueue: events_freezable mmc_rescan
[ 242.734796] Call trace:
[ 242.737269] [<
ffff00000808611c>] __switch_to+0xa8/0xb4
[ 242.742437] [<
ffff000008d07c04>] __schedule+0x1c0/0x67c
[ 242.747689] [<
ffff000008d08254>] schedule+0x40/0xa0
[ 242.752594] [<
ffff000008d0b284>] schedule_timeout+0x1c4/0x35c
[ 242.758366] [<
ffff000008d08e38>] wait_for_common+0xd0/0x15c
[ 242.763964] [<
ffff000008d09008>] wait_for_completion+0x28/0x34
[ 242.769825] [<
ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124
[ 242.775949] [<
ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8
[ 242.781549] [<
ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84
[ 242.787149] [<
ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114
[ 242.793270] [<
ffff000008a26aa0>] sdio_reset+0x34/0x7c
[ 242.798347] [<
ffff000008a1d46c>] mmc_rescan+0x2fc/0x360
[ ... ]
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Geert Uytterhoeven [Mon, 3 Apr 2017 10:08:09 +0000 (12:08 +0200)]
arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Kevin Hilman [Tue, 4 Apr 2017 23:16:52 +0000 (16:16 -0700)]
Merge tag 'amlogic-clk-headers' into v4.12/dt64
Amlogic clock headers and DT binding updates for v4.12
- add clocks for I2S and Mali
# gpg: Signature made Tue Apr 4 16:07:50 2017 PDT using RSA key ID
D3FBC665
# gpg: Good signature from "Kevin Hilman <khilman@kernel.org>" [ultimate]
# gpg: aka "Kevin Hilman <khilman@deeprootsystems.com>" [ultimate]
# gpg: aka "Kevin Hilman <khilman@gmail.com>" [ultimate]
# gpg: aka "Kevin Hilman <khilman@baylibre.com>" [ultimate]
* tag 'amlogic-clk-headers':
dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
clk: meson-gxbb: Expose GP0 dt-bindings clock id
clk: meson-gxbb: Add MALI clock IDS
dt-bindings: clk: gxbb: expose i2s output clock gates
Neil Armstrong [Tue, 21 Mar 2017 15:25:46 +0000 (16:25 +0100)]
ARM64: dts: meson-gx: Add support for HDMI output
Add HDMI output and connector nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Tue, 21 Mar 2017 15:25:45 +0000 (16:25 +0100)]
ARM64: dts: meson-gx: Add shared CMA dma memory pool
The HDMI modes needs more CMA memory to be reserved at boot-time.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Heiner Kallweit [Tue, 14 Feb 2017 21:18:44 +0000 (22:18 +0100)]
ARM64: dts: meson-gxbb-odroidc2: Enable SARADC node
Now that
3adbf3427330 "iio: adc: add a driver for the SAR ADC found in
Amlogic Meson SoCs" has added support for the ADC, let's enable it
on Odroid C2.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Wed, 22 Mar 2017 10:32:27 +0000 (11:32 +0100)]
dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-6-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:32:26 +0000 (11:32 +0100)]
clk: meson-gxbb: Expose GP0 dt-bindings clock id
This patch exposes the GP0 PLL clock id in the dt bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-5-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:18:53 +0000 (11:18 +0100)]
clk: meson-gxbb: Add MALI clock IDS
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490177935-9646-2-git-send-email-narmstrong@baylibre.com
Jerome Brunet [Thu, 9 Mar 2017 10:41:54 +0000 (11:41 +0100)]
dt-bindings: clk: gxbb: expose i2s output clock gates
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
20170309104154.28295-10-jbrunet@baylibre.com
Liang Chen [Mon, 27 Mar 2017 09:40:49 +0000 (17:40 +0800)]
arm64: dts: rockchip: add RK3328 eavluation board devicetree
This patch add rk3328-evb.dts for RK3328 evaluation board.
Tested on RK3328 evb.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Liang Chen [Mon, 27 Mar 2017 09:46:23 +0000 (17:46 +0800)]
dt-bindings: document rockchip rk3328-evb board
Use "rockchip,rk3328-evb" compatible string for Rockchip RK3328
evaluation board.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Liang Chen [Mon, 27 Mar 2017 09:40:48 +0000 (17:40 +0800)]
arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
This patch adds core dtsi file for Rockchip RK3328 SoCs.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Icenowy Zheng [Tue, 4 Apr 2017 09:50:59 +0000 (17:50 +0800)]
ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two
H3 boards and one H5 board.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Tue, 4 Apr 2017 09:51:00 +0000 (17:51 +0800)]
arm64: allwinner: a64: add R_PIO pinctrl node
Allwinner A64 have a dedicated pin controller to manage the PL pin bank.
As the driver and the required clock support are added, add the device
node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Tue, 4 Apr 2017 09:50:58 +0000 (17:50 +0800)]
arm64: allwinner: a64: add r_ccu node
A64 SoC have a CCU (r_ccu) in PRCM block.
Add the device node for it.
The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
to the user manual, and has only 30% accuracy based on our experience
on older SoCs. The real mesaured value of it on two Pine64 boards is
around 11MHz, which is around 70% of 16MHz.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Liang Chen [Mon, 27 Mar 2017 09:40:47 +0000 (17:40 +0800)]
dt-bindings: add binding for rk3328-grf
This adds the compatible for the General Register Files on the new rk3328.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jon Hunter [Tue, 28 Mar 2017 12:42:57 +0000 (13:42 +0100)]
arm64: tegra: Update the Tegra132 flowctrl compatible string
Update the Tegra132 flowctrl compatible string to include
"nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding
documentation.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Alexandre Courbot [Thu, 30 Mar 2017 09:28:28 +0000 (18:28 +0900)]
arm64: tegra: Add GPU node for Tegra186
Add the DT node for the GP10B GPU on Tegra186.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Harninder Rai [Thu, 9 Feb 2017 11:04:11 +0000 (16:34 +0530)]
dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Harninder Rai [Thu, 9 Feb 2017 11:03:49 +0000 (16:33 +0530)]
dt-bindings: clockgen: Add compatible string for LS1088A
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rob Herring [Wed, 22 Mar 2017 02:03:11 +0000 (21:03 -0500)]
arm64: dts: juno: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Arnd Bergmann [Fri, 31 Mar 2017 09:54:40 +0000 (11:54 +0200)]
Merge tag 'v4.12-rockchip-dts64-symlinks-1' of git://git./linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 updates (using arm/arm64 symlinks) for 4.12 part1" from Heiko Stübner
Rockchip dts changes based on the newly created arm/arm64 symlinks.
The core addition is the support for the rk3399-based Gru family of
ChromeOS devices, like the Kevin board which is the recently released
Samsung Chromebook Plus. Additionally the usb3 controllers are added
to rk3399 as they're used on Gru devices and even without full type-c
support they can at least drive usb2 devices already.
* tag 'v4.12-rockchip-dts64-symlinks-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: add regulator info for Kevin digitizer
arm64: dts: rockchip: describe Gru/Kevin OPPs + CPU regulators
arm64: dts: rockchip: add Gru/Kevin DTS
dt-bindings: Document rk3399 Gru/Kevin
arm64: dts: rockchip: support dwc3 USB for rk3399
Arnd Bergmann [Fri, 31 Mar 2017 09:53:40 +0000 (11:53 +0200)]
Merge tag 'v4.12-rockchip-dts64-1' of git://git./linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 updates for 4.12 part1" from Heiko Stübner:
Contains various changes for the rk3368 (dma, i2s, disable mailbox per
default, mmc-resets) and also removes the wrongly added idle states, that
do not match the hardware's capabilities, as well as some general rk3399
pcie fixes as well as also the mmc resets.
* tag 'v4.12-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix PCIe domain number for rk3399
arm64: dts: rockchip: add rk3399 dw-mmc resets
arm64: dts: rockchip: add rk3368 dw-mmc resets
arm64: dts: rockchip: disable mailbox of RK3368 SoCs per default
arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs
arm64: dts: rockchip: add dmac nodes for rk3368 SoCs
arm64: dts: rockchip: remove wrongly added idle states on rk3368
arm64: dts: rockchip: sort rk3399-pcie by unit address
Arnd Bergmann [Fri, 31 Mar 2017 09:52:16 +0000 (11:52 +0200)]
Merge tag 'arm-soc/for-4.12/devicetree-arm64' of github.com/Broadcom/stblinux into next/dt64
Pull "Broadcom devicetree-arm64 changes for 4.12" from Florian Fainelli:
This pull request contains Broadcom ARM64-based SoCs Device Tree updates for
4.12, please pull the following:
- Rob enables the cryptographic block on Northstar 2 (SPU) by adding the proper
Device Tree nodes
- Jon replaces all occurences of: status = "ok" with status = "okay" to better
conform to the Device Tree specification
* tag 'arm-soc/for-4.12/devicetree-arm64' of http://github.com/Broadcom/stblinux:
arm64: dts: NS2: convert "ok" to "okay"
arm64: dts: NS2: Add Broadcom SPU driver DT entry
Arnd Bergmann [Fri, 31 Mar 2017 09:51:03 +0000 (11:51 +0200)]
Merge tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64
Pull "mvebu dt64 for 4.12 (part 1)" from Gregory CLEMENT:
- Add RTC support on Armada 7k/8k
- Improve i2c support on Armada 37xx
- Add gpio expander and RTC on Armada 3720 board
- Improve USB3 support on Armada 37xx
- Add network support on Armada 7k/8k
* tag 'mvebu-dt64-4.12-1' of git://git.infradead.org/linux-mvebu:
arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
ARM64: dts: marvell: armada-3720 add RTC support
ARM64: dts: marvell: armada-3720-db: Add phy for USB3
ARM64: dts: marvell: armada-37xx: Add clock resource for USB3
ARM64: dts: marvell: armada-37xx: Fix interrupt mapping for USB3
ARM64: dts: marvell: armada-3720-db: add gpio expander
ARM64: dts: marvell: armada37xx: add address and size property for i2c cells
arm64: dts: marvell: add RTC description for Armada 7K/8K
Arnd Bergmann [Fri, 31 Mar 2017 09:45:14 +0000 (11:45 +0200)]
Merge tag 'uniphier-dt64-v4.12' of git://git./linux/kernel/git/masahiroy/linux-uniphier into next/dt64
Pull "UniPhier ARM64 SoC DT updates for v4.12" from Masahiro Yamada:
- Fix W=* build warnings
- Add pinctrl properties to eMMC nodes
- Fix resets properties of USB nodes
* tag 'uniphier-dt64-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
arm64: dts: uniphier: re-order reset deassertion of USB of LD11
arm64: dts: uniphier: add pinctrl property to eMMC node for LD11/LD20
arm64: dts: uniphier: move memory node below aliases node
arm64: dts: uniphier: fix no unit name warnings
Jayachandran C [Tue, 14 Mar 2017 12:47:14 +0000 (12:47 +0000)]
arm64: dts: move from ARCH_VULCAN to ARCH_THUNDER2
Move and update device tree files as part of transition from Broadcom
Vulcan to Cavium ThunderX2.
The changes are to:
* rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi,
update cpu cores to be "cavium,thunder2", and update SoC to be
"cavium,thunderx2-cn9900"
* move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi
and update board name string
* Update dts/broadcom/Makefile not to build vulcan dtbs
* Update dts/cavium/Makefile to build thunder2 dtbs
No changes to the dts contents except the updated "compatible" and
"model" properties.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Jayachandran C [Wed, 15 Mar 2017 20:11:00 +0000 (20:11 +0000)]
dt-bindings: Add arm64 ARCH_THUNDER2 platform documentation
Add documentation for Cavium's ThunderX2 CN99XX ARM64 processor. This
SoC will use "cavium,thunderx2-cn9900" as the compatible property.
Also add a documentation entry for the "cavium,thunder2" cpu core
present in these SoCs.
Signed-off-by: Jayachandran C <jnair@caviumnetworks.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
spjoshi@codeaurora.org [Thu, 19 Jan 2017 03:31:53 +0000 (19:31 -0800)]
arm64: dts: msm8996: Add ADSP PIL node
Add ADSP node required for Qualcomm ADSP Peripheral Image Loader.
Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Bjorn Andersson [Fri, 17 Feb 2017 08:53:23 +0000 (00:53 -0800)]
arm64: dts: qcom: pm8994: Add rtc node
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Bjorn Andersson [Wed, 1 Feb 2017 10:24:24 +0000 (02:24 -0800)]
arm64: dts: apq8016-sbc: Add ramoops
Declare a ramoops memory segment to aid debugging for those without UART
access. Verified to carry console log when holding volume down for 15
seconds.
No memory region for ramoops-like support was found downstream, so the
arbitrarily picked region is the last MB of System RAM.
Cc: John Stultz <john.stultz@linaro.org>
Cc: Mart Raudsepp <leio@gentoo.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Harninder Rai [Tue, 28 Mar 2017 16:33:08 +0000 (22:03 +0530)]
arm64: dts: Add support for FSL's LS1088A SoC
LS1088A contains eight ARM v8 CortexA53 processor cores
with 32 KB L1-D cache and 32 KB L1-I cache
Features summary
Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Arranged as two clusters of four cores sharing a 1 MB L2 cache
- Speed Up to 1.5 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 700 MHz
One 64-bit DDR4 SDRAM memory controller with ECC
Data path acceleration architecture 2.0 (DPAA2)
Three PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Three high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1088A
SoC family:
- fsl-ls1088a.dtsi:
DTS-Include file for NXP LS1088A SoC.
- fsl-ls1088a-qds.dts:
DTS file for NXP LS1088A QDS board.
- fsl-ls1088a-rdb.dts:
DTS file for NXP LS1088A RDB board
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>`
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Horia Geantă [Tue, 28 Mar 2017 11:46:19 +0000 (14:46 +0300)]
arm64: dts: ls1012a: add crypto node
LS1012A has a SEC v5.4 security engine.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Bjorn Andersson [Mon, 30 Jan 2017 16:44:59 +0000 (08:44 -0800)]
arm64: dts: qcom: msm8916: Update hexagon node
It's necessary to reference the xo clock and cx supply, so specify these
in the node. Also move the Hexagon smd-edge into the hexagon node, to
enable SSR.
As cxo is not yet available we reference the fixed version of cxo for
now, which will work until proper power management is implemented.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
avaneesh dwivedi [Mon, 30 Jan 2017 15:03:09 +0000 (20:33 +0530)]
arm64: dts: msm8996: Add SLPI SMP2P dt node.
Add smp2p support to communicate with slpi processor.
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Stephen Boyd [Tue, 17 Jan 2017 19:47:55 +0000 (11:47 -0800)]
arm64: dts: qcom: Replace PMU compatible with a53 specific one
The PMU on msm8916 is for the cortex-a53 type CPU. Update the
compatible to the more specific one so we can get the a53
specific events out of the PMU.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Bjorn Andersson [Fri, 18 Nov 2016 20:06:49 +0000 (12:06 -0800)]
arm64: dts: qcom: msm8996: Fixup smp2p node
The SMEM state property name changes between the integration branch and
mainline, update to use the correct one.
Fixes:
2f45d9fcd531 ("arm64: dts: msm8996: Add SMP2P and APCS nodes")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
jbrunet [Sun, 26 Mar 2017 17:19:23 +0000 (19:19 +0200)]
ARM64: dts: meson-gxl: add spdif output pins
Add EE and AO domains pins for the spdif output to the gxl device tree.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
jbrunet [Sun, 26 Mar 2017 17:19:22 +0000 (19:19 +0200)]
ARM64: dts: meson-gxl: add i2s output pins
Add EE and AO domains pins for the i2s output clocks and data the gxl
device tree
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
jbrunet [Sun, 26 Mar 2017 17:19:21 +0000 (19:19 +0200)]
ARM64: dts: meson-gxbb: add spdif output pins
Add EE and AO domains pins for the spdif output to the gxbb device tree.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
jbrunet [Sun, 26 Mar 2017 17:19:20 +0000 (19:19 +0200)]
ARM64: dts: meson-gxbb: add i2s output pins
Add EE and AO domains pins for the i2s output clocks and data to the gxbb
device tree.
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Thu, 23 Mar 2017 16:27:29 +0000 (17:27 +0100)]
ARM64: dts: meson-gxbb: Add USB Hub GPIO hog
The ODroid-C2 on-board USB Hub needs to to have it's reset signal set to
high level in order to be enumerated by the USB Host Controller.
But this management must be part of the currently in-development Generic
Power Sequence patch that will allow a USB Controller driver to start and stop
a power sequence associated to the USB Bus.
In the meantime, a simple USB Hog will work to enable the USB Hub.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Thu, 23 Mar 2017 16:27:27 +0000 (17:27 +0100)]
ARM: dts: meson8b: Add gpio-ranges properties
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Thu, 23 Mar 2017 16:27:26 +0000 (17:27 +0100)]
ARM: dts: meson8: Add gpio-ranges properties
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Thu, 23 Mar 2017 16:27:25 +0000 (17:27 +0100)]
ARM64: dts: meson-gxl: Add gpio-ranges properties
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Thu, 23 Mar 2017 16:27:24 +0000 (17:27 +0100)]
ARM64: dts: meson-gxbb: Add gpio-ranges properties
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Wed, 22 Mar 2017 10:18:55 +0000 (11:18 +0100)]
ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL
The same Mali-450 MP3 GPU is present in the GXBB and GXL SoCs.
The node is simply added in the meson-gxbb.dtsi file.
For GXL, since a lot is shared with the GXM that has a Mali-T820 IP, this
patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific
dtsi files.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[khilman: s/MALI/Mali in changelog]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Icenowy Zheng [Sat, 25 Mar 2017 14:50:15 +0000 (22:50 +0800)]
arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
Orange Pi PC 2 board features a OTG port like the one on older H3 Orange
Pi's, with PG12 pin being the id det pin and PL2 being the vbus driver
pin.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Mon, 6 Mar 2017 17:17:50 +0000 (01:17 +0800)]
arm64: allwinner: h5: add support for the Orange Pi PC 2 board
The Orange Pi PC 2 is a typical single board computer using the
Allwinner H5 SoC. Apart from the usual suspects it features three
separately driven USB ports and a Gigabit Ethernet port.
Also it has a SPI NOR flash soldered, from which the board can boot
from. This enables the SBC to behave like a "real computer" with
built-in firmware.
Add the board specific .dts file, which includes the H5 .dtsi and
enables the peripherals that we support so far.
Reviewed-by: Rask Ingemann Lambertsen <rask@formelder.dk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: dropped all GPIO pinctrl nodes, change red LED gpio,
change MMC cd to active-low, rename some node names to prevent
underscores]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Mon, 6 Mar 2017 17:17:49 +0000 (01:17 +0800)]
arm64: allwinner: h5: add Allwinner H5 .dtsi
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses
Cortex-A53 cores instead.
Based on the now shared base .dtsi describing the common peripherals
describe the H5 specific nodes on top of that.
That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi
refactor, commit message changed to meet new arm64 naming scheme,
drop H3 pinctrl compatible because of interrupt bank change, drop
H3 ccu compatible because of clock change, drop ccu node as it come
into h3-h5 dtsi]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Sat, 25 Mar 2017 14:50:12 +0000 (22:50 +0800)]
ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.
Add device nodes for these controllers.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Mon, 6 Mar 2017 17:17:48 +0000 (01:17 +0800)]
arm: sun8i: h3: split Allwinner H3 .dtsi
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
updated. So we should really share almost the whole .dtsi.
In preparation for that move the peripheral parts of the existing
sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi.
The actual sun8i-h3.dtsi then includes that and defines the H3 specific
parts on top of it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: also split out mmc and gic, as well as pio and ccu's
compatible, and make drop of skeleton into a seperated patch]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Mon, 6 Mar 2017 17:17:47 +0000 (01:17 +0800)]
arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
According to the datasheets provided by Allwinner, both Allwinner H3 and
H5 use GIC-400 as their interrupt controller.
For better device tree reusing, correct the GIC compatible in H3 DTSI to
"arm,gic-400", thus this node can be reused in H5.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Mon, 6 Mar 2017 17:17:46 +0000 (01:17 +0800)]
arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
After converting to generic pinconf binding, pinctrl-a10.h is now not
used at all.
Drop its inclusion for H3 DTSI.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Mon, 6 Mar 2017 17:17:45 +0000 (01:17 +0800)]
arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
The skeleton.dtsi file is now deprecated, and do not exist in ARM64
environment.
Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64
chip, drop skeleton.dtsi inclusion now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Neil Armstrong [Thu, 23 Mar 2017 10:41:11 +0000 (11:41 +0100)]
ARM64: dts: meson-gxl: Add missing pinctrl pins groups
Add pinctrl pins nodes following the additions of missing pins in the pinctrl
driver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Shawn Guo [Thu, 19 Jan 2017 14:45:23 +0000 (22:45 +0800)]
arm64: dts: zte: add tvenc device for zx296718
It adds VOU tvenc device in zx296718.dtsi, so that boards with TV
connector can enable the support by changing 'status' in board DTS file.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Shawn Guo [Thu, 22 Sep 2016 11:48:39 +0000 (19:48 +0800)]
arm64: dts: zte: add vou and hdmi devices for zx296718
It adds VOU DPC device and enables HDMI support, which includes both
display and audio through SPDIF interface.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Jun Nie [Tue, 21 Mar 2017 08:52:59 +0000 (16:52 +0800)]
arm64: dts: zte: add mmc devices for zx296718
Add three mmc devices for zx296718 SoC, and enable the SD and eMMMC on
zx296718-evb board.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Shawn Guo [Tue, 21 Mar 2017 08:42:45 +0000 (16:42 +0800)]
arm64: dts: zte: remove zx296718 pll_vga clock
Rather than a fixed rate clock, pll_vga is a PLL can be programmed into
different freqencies. Let's drop it from device tree and get it
registered from clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Neil Armstrong [Mon, 13 Mar 2017 09:10:52 +0000 (10:10 +0100)]
ARM64: dts: meson-gx: Prepend GX generic compatible like other nodes
Prepend the compatible strings with a GX generic name in nodes compatible with
the GXBB HW and keep the same scheme as other nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Mon, 13 Mar 2017 09:10:51 +0000 (10:10 +0100)]
ARM64: dts: meson-gx: empty line cleanup
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Neil Armstrong [Mon, 13 Mar 2017 09:10:50 +0000 (10:10 +0100)]
ARM64: dts: meson-gx: Finally move common nodes to GX dtsi
Since we know the GXBB and GXL/GXM share more hardware, we can safely move
the remaining peripheral nodes present in the GXBB dtsi to the common GX dtsi.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sat, 18 Mar 2017 12:36:57 +0000 (13:36 +0100)]
ARM64: dts: meson-gxl: add support for the Khadas VIM board
The Khadas VIM series consists of two boards which are almost
identical:
They are both using the same GXL S905X SoC, 100Mbit/s ethernet
(through the SoC-internal PHY), 2GB DDR3 memory, a micro-SD card slot,
onboard eMMC, Broadcom based SDIO WIFI, 2x USB A and 1x USB Type-C (the
latter with OTG support). The red LED is driven by PWM_AO_B (which
allows dimming), while the blue LED is managed by the firmware.
The differences are:
- the VIM Pro has a 16GB eMMC module, while the VIM only has 8GB
- the VIM Pro uses an AP6255 a/b/g/n/ac WIFI module, while the VIM comes
with an AP6212 b/g/n SDIO WIFI module
(the Vim uses an 8GB eMMC module, while
The boards are based on Amlogic's GXL S905X P212 reference design, which
is why most of the functionality (all MMC controllers and power
sequences, IR remote input, the main UART, ADC and ethernet) is simply
inherited from meson-gxl-s905x-p212.dtsi.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sat, 18 Mar 2017 12:36:56 +0000 (13:36 +0100)]
dt-bindings: amlogic: add the Khadas VIM
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sat, 18 Mar 2017 12:36:55 +0000 (13:36 +0100)]
devicetree: add vendor prefix for Khadas
Khadas is a new sub-brand of "Shenzhen Wesion Technology Co., Ltd.".
They are developing Amlogic and Rockchip based "DIY boxes" (single board
computers): http://khadas.com/
They are best know for their latest product: the Khadas VIM (an Amlogic
GXL S905X based SBC).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Martin Blumenstingl [Sat, 18 Mar 2017 12:27:36 +0000 (13:27 +0100)]
ARM64: dts: amlogic: meson-gxl: add the missing PWM pins
This adds the new DT nodes for the missing PWM pins in the EE and AO
domain.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Thomas Petazzoni [Thu, 16 Mar 2017 15:16:27 +0000 (16:16 +0100)]
arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K
This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Gregory CLEMENT [Wed, 8 Mar 2017 17:35:19 +0000 (18:35 +0100)]
ARM64: dts: marvell: armada-3720 add RTC support
The Armada 3720 DB board has an RTC on the I2C bus. It's a PT7C4337A from
Pericom but which claims to be fully compatible with the ds1337.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / log