GitHub/exynos8895/android_kernel_samsung_universal8895.git
12 years agodrm/nve0/gr: initial implementation
Ben Skeggs [Tue, 13 Mar 2012 03:05:13 +0000 (13:05 +1000)]
drm/nve0/gr: initial implementation

This may, perhaps, get re-merged with nvc0_graph.c at some point.  It's
still unclear as to how great an idea that'd be.  Stay tuned...

Completely dependent on firmware blobs from NVIDIA binary driver currently.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nve0/fifo: initial implementation
Ben Skeggs [Thu, 8 Mar 2012 00:41:45 +0000 (10:41 +1000)]
drm/nve0/fifo: initial implementation

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nouveau: give a slightly larger pci(e)gart aperture on all chipsets
Ben Skeggs [Tue, 27 Mar 2012 05:15:18 +0000 (15:15 +1000)]
drm/nouveau: give a slightly larger pci(e)gart aperture on all chipsets

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nouveau/pm: some more delays for ddr3 reclocking
Ben Skeggs [Mon, 6 Feb 2012 06:20:30 +0000 (16:20 +1000)]
drm/nouveau/pm: some more delays for ddr3 reclocking

These numbers from the binary driver's daemon scripts, and fix the transition
to perflvl 3 on my T510.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nvc0/pm: very initial mclk freq change
Ben Skeggs [Mon, 6 Feb 2012 03:51:30 +0000 (13:51 +1000)]
drm/nvc0/pm: very initial mclk freq change

Loads of magic missing, this will probably blow up if you try it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nvd9/pm: oops, fix timing calc
Ben Skeggs [Mon, 6 Feb 2012 01:42:29 +0000 (11:42 +1000)]
drm/nvd9/pm: oops, fix timing calc

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nvc0/pm: enable mpll src pll, and calc mpll coefficients
Ben Skeggs [Mon, 6 Feb 2012 01:34:20 +0000 (11:34 +1000)]
drm/nvc0/pm: enable mpll src pll, and calc mpll coefficients

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nvc0/pm: start filling in memory reclocking stubs
Ben Skeggs [Tue, 31 Jan 2012 23:00:57 +0000 (09:00 +1000)]
drm/nvc0/pm: start filling in memory reclocking stubs

12 years agodrm/nva3/pm: another few magic regs, and slightly better 0x004018 handling
Ben Skeggs [Sun, 5 Feb 2012 23:58:09 +0000 (09:58 +1000)]
drm/nva3/pm: another few magic regs, and slightly better 0x004018 handling

Not entirely convinced 0x004018 transitions are correct yet, but, it's
an improvement.

The 750MHz value comes from fiddling with the binary driver + coolbits on
two different DDR3 NVA8 chipsets (T510 NVS3100M, and NVS300), not a clue
where this number comes from.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: initial attempt at handling 111100/111104
Ben Skeggs [Fri, 3 Feb 2012 00:34:33 +0000 (10:34 +1000)]
drm/nva3/pm: initial attempt at handling 111100/111104

Probably not quite right, but this is enough now to make NVS300 reclock
between all 3 of its perflvls correctly.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: make pll->pll mode work
Ben Skeggs [Fri, 3 Feb 2012 00:02:03 +0000 (10:02 +1000)]
drm/nva3/pm: make pll->pll mode work

This probably wants a cleanup, but I'm holding off until I know for sure
how the rest of the things that need doing fit together.

Tested on NVS300 by hacking up perflvl 1 to require PLL mode, and switching
between perflvl 3 and 1.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: attempt to bash a few 0x100200 bits correctly
Ben Skeggs [Thu, 2 Feb 2012 05:07:13 +0000 (15:07 +1000)]
drm/nva3/pm: attempt to bash a few 0x100200 bits correctly

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: begin to restructure memory clock changes + another magic
Ben Skeggs [Thu, 2 Feb 2012 01:43:31 +0000 (11:43 +1000)]
drm/nva3/pm: begin to restructure memory clock changes + another magic

The binary driver appears to do various bits and pieces of the memory
clock frequency change at different times, depending on the particular
transition that's occuring.  I've attempted to replicate this here
for div->pll, pll->div and div->div transitions.

With some additional (patches upcoming) magic regs being bashed, this
allows me to correctly transition between all 3 perflvls on NVS300.

pll->pll transitions will *not* work correctly at the moment, pending
me tricking the binary driver into doing one and seeing how to correctly
handle it.

This patch also handles (hopefully) 0x1110e0, which appears to need
changing depending on whether in PLL or divider mode.. Maybe.  We'll
see.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: more random unknown PFB regs
Ben Skeggs [Fri, 27 Jan 2012 03:26:52 +0000 (13:26 +1000)]
drm/nva3/pm: more random unknown PFB regs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: initial attempt at more magic PFB regs
Ben Skeggs [Fri, 27 Jan 2012 00:53:17 +0000 (10:53 +1000)]
drm/nva3/pm: initial attempt at more magic PFB regs

The reg calculation may get moved elsewhere at some point, but lets
figure out what exactly we need to do first.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: hook up to ram reclocking helper
Ben Skeggs [Wed, 25 Jan 2012 06:02:58 +0000 (16:02 +1000)]
drm/nva3/pm: hook up to ram reclocking helper

This gets us a start on memory timings.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nva3/pm: introduce more paranoia
Ben Skeggs [Sat, 17 Dec 2011 04:02:51 +0000 (14:02 +1000)]
drm/nva3/pm: introduce more paranoia

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 years agodrm/nouveau/radeon: add static const to the dma-buf ops.
Dave Airlie [Wed, 23 May 2012 13:10:27 +0000 (14:10 +0100)]
drm/nouveau/radeon: add static const to the dma-buf ops.

Reported-by: wfg@linux.intel.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/i915: make some dmabuf things static
Dave Airlie [Wed, 23 May 2012 13:09:32 +0000 (14:09 +0100)]
drm/i915: make some dmabuf things static

these functions and the table can all be static/static const.

Reported-by: wfg@linux.intel.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: update ast/cirrus/mgag200 for change in TTM api
Dave Airlie [Wed, 23 May 2012 13:08:41 +0000 (14:08 +0100)]
drm: update ast/cirrus/mgag200 for change in TTM api

New drivers merged after changes were done in prime TTM code.

Fix build.

Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoMerge branch 'prime-merge' of ssh://people.freedesktop.org/~airlied/linux into drm...
Dave Airlie [Wed, 23 May 2012 09:46:24 +0000 (10:46 +0100)]
Merge branch 'prime-merge' of ssh://people.freedesktop.org/~airlied/linux into drm-core-next

* 'prime-merge' of ssh://people.freedesktop.org/~airlied/linux:
  drm/radeon: add PRIME support (v2)
  i915: add dmabuf/prime buffer sharing support.
  nouveau: add PRIME support
  ttm: add prime sharing support to TTM (v2)
  udl: add prime fd->handle support.
  drm/prime: add exported buffers to current fprivs imported buffer list (v2)
  drm/prime: introduce sg->pages/addr arrays helper

12 years agodrm/radeon: add PRIME support (v2)
Alex Deucher [Thu, 10 May 2012 22:33:13 +0000 (18:33 -0400)]
drm/radeon: add PRIME support (v2)

This adds prime->fd and fd->prime support to radeon.
It passes the sg object to ttm and then populates
the gart entries using it.

Compile tested only.

v2: stub kmap + use new helpers + add reimporting

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoi915: add dmabuf/prime buffer sharing support.
Daniel Vetter [Thu, 10 May 2012 13:25:09 +0000 (15:25 +0200)]
i915: add dmabuf/prime buffer sharing support.

This adds handle->fd and fd->handle support to i915, this is to allow
for offloading of rendering in one direction and outputs in the other.

v2 from Daniel Vetter:
- fixup conflicts with the prepare/finish gtt prep work.
- implement ppgtt binding support.

Note that we have squat i-g-t testcoverage for any of the lifetime and
access rules dma_buf/prime support brings along. And there are quite a
few intricate situations here.

Also note that the integration with the existing code is a bit
hackish, especially around get_gtt_pages and put_gtt_pages. It imo
would be easier with the prep code from Chris Wilson's unbound series,
but that is for 3.6.

Also note that I didn't bother to put the new prepare/finish gtt hooks
to good use by moving the dma_buf_map/unmap_attachment calls in there
(like we've originally planned for).

Last but not least this patch is only compile-tested, but I've changed
very little compared to Dave Airlie's version. So there's a decent
chance v2 on drm-next works as well as v1 on 3.4-rc.

v3: Right when I've hit sent I've noticed that I've screwed up one
obj->sg_list (for dmar support) and obj->sg_table (for prime support)
disdinction. We should be able to merge these 2 paths, but that's
material for another patch.

v4: fix the error reporting bugs pointed out by ickle.

v5: fix another error, and stop non-gtt mmaps on shared objects
stop pread/pwrite on imported objects, add fake kmap

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agonouveau: add PRIME support
Dave Airlie [Mon, 2 Apr 2012 10:53:06 +0000 (11:53 +0100)]
nouveau: add PRIME support

This adds prime->fd and fd->prime support to nouveau,
it passes the SG object to TTM, and then populates the
GART entries using it.

v2: add stubbed kmap + use new function to fill out pages array
for faulting + add reimport test.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agottm: add prime sharing support to TTM (v2)
Dave Airlie [Mon, 2 Apr 2012 10:46:06 +0000 (11:46 +0100)]
ttm: add prime sharing support to TTM (v2)

This adds the ability for ttm common code to take an SG table
and use it as the backing for a slave TTM object.

The drivers can then populate their GTT tables using the SG object.

v2: make sure to setup VM for sg bos as well.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoudl: add prime fd->handle support.
Dave Airlie [Wed, 21 Dec 2011 11:23:44 +0000 (11:23 +0000)]
udl: add prime fd->handle support.

udl can only be used as an output offload so doesn't need to support
handle->fd direction.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/prime: add exported buffers to current fprivs imported buffer list (v2)
Dave Airlie [Sun, 20 May 2012 16:31:16 +0000 (17:31 +0100)]
drm/prime: add exported buffers to current fprivs imported buffer list (v2)

If userspace attempts to import a buffer it exported on the same device,
we need to return the same GEM handle for it, not a new handle pointing
at the same GEM object.

v2: move removals into a single fn, no need to set to NULL. (Chris Wilson)

Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/prime: introduce sg->pages/addr arrays helper
Dave Airlie [Fri, 18 May 2012 14:40:33 +0000 (15:40 +0100)]
drm/prime: introduce sg->pages/addr arrays helper

the ttm drivers need this currently, in order to get fault handling
working and efficient.

It also allows addrs to be NULL for devices like udl.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: add plane properties
Rob Clark [Thu, 17 May 2012 08:23:27 +0000 (02:23 -0600)]
drm: add plane properties

The omapdrm driver uses this for setting per-overlay rotation.  It
is likely also useful for setting YUV->RGB colorspace conversion
matrix, etc.

Signed-off-by: Rob Clark <rob@ti.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: add bitmask property type
Rob Clark [Thu, 17 May 2012 08:23:26 +0000 (02:23 -0600)]
drm: add bitmask property type

A bitmask property is similar to an enum.  The enum value is a bit
position (0-63), and valid property values consist of a mask of
zero or more of (1 << enum_val[n]).

[airlied: 1LL -> 1ULL]

Signed-off-by: Rob Clark <rob@ti.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoMerge branch 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung...
Dave Airlie [Tue, 22 May 2012 09:39:57 +0000 (10:39 +0100)]
Merge branch 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung into drm-core-next

* 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung:
  drm/exynos: add G2D driver
  drm/exynos: added vp scaling feature for hdmi
  drm/exynos: added source size to overlay structure
  drm/exynos: add additional display mode for hdmi
  drm/exynos: enable dvi mode for dvi monitor
  drm/exynos: fixed wrong pageflip finish event for interlace mode
  drm/exynos: add PM functions for hdmi and mixer
  drm/exynos: add dpms for hdmi
  drm/exynos: use threaded irq for hdmi hotplug
  drm/exynos: use platform_get_irq_byname for hdmi
  drm/exynos: cleanup for hdmi platform data
  drm/exynos: added a feature to get gem buffer information.
  drm/exynos: added drm prime feature.
  drm/exynos: added cache attribute support for gem.
  vgaarb: Provide dummy default device functions

12 years agodrm: Make the CRTC gamma_set operation optional
Laurent Pinchart [Thu, 17 May 2012 11:27:24 +0000 (13:27 +0200)]
drm: Make the CRTC gamma_set operation optional

Drivers for hardware without gamma support should not be forced to
implement a no-op gamma set operation.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Rob Clark <rob.clark@linaro.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: Constify drm_mode_config_funcs pointer
Laurent Pinchart [Thu, 17 May 2012 11:27:23 +0000 (13:27 +0200)]
drm: Constify drm_mode_config_funcs pointer

The DRM mode config functions structure declared by drivers and pointed
to by the drm_mode_config funcs field is never modified. Make it a const
pointer.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Inki Dae <inki.dae@samsung.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Cc: Rob Clark <rob.clark@linaro.org>
Reviwed-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: Constify gem_vm_ops pointer
Laurent Pinchart [Thu, 17 May 2012 11:27:22 +0000 (13:27 +0200)]
drm: Constify gem_vm_ops pointer

The GEM vm operations structure is passed to the VM core that stores it
in a const field. There vm operations structures can thus be const in
DRM as well.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Inki Dae <inki.dae@samsung.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Rob Clark <rob.clark@linaro.org>
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: Miscellaneous typo fixes and documentation updates
Laurent Pinchart [Thu, 17 May 2012 11:27:20 +0000 (13:27 +0200)]
drm: Miscellaneous typo fixes and documentation updates

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: Don't initialize local ret variable when not needed
Laurent Pinchart [Thu, 17 May 2012 11:27:21 +0000 (13:27 +0200)]
drm: Don't initialize local ret variable when not needed

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm: Delete the vblank timer synchronously at cleanup time
Laurent Pinchart [Thu, 17 May 2012 11:27:19 +0000 (13:27 +0200)]
drm: Delete the vblank timer synchronously at cleanup time

A race condition exists in drm_vblank_cleanup() if the vblank disable
timer callback runs after freeing the memory that its callback function
tries to access. Fix this by deleting the timer synchronously.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/backlight: initialize struct backlight_properties properly
Corentin Chary [Tue, 22 May 2012 09:29:46 +0000 (10:29 +0100)]
drm/backlight: initialize struct backlight_properties properly

The power field was never correctly initialized.

[airlied: just took the two drm specific bits]

Signed-off-by: Corentin Chary <corentin.chary@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/nouveau/dp: Probe branch/sink OUIs (v2)
Adam Jackson [Mon, 14 May 2012 20:05:49 +0000 (16:05 -0400)]
drm/nouveau/dp: Probe branch/sink OUIs (v2)

(airlied: v2: fix missing struct - fixes compile)

Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon/dp: Probe branch/sink OUIs
Adam Jackson [Mon, 14 May 2012 20:05:48 +0000 (16:05 -0400)]
drm/radeon/dp: Probe branch/sink OUIs

Signed-off-by: Adam Jackson <ajax@redhat.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/i915/dp: Probe branch/sink OUIs
Adam Jackson [Mon, 14 May 2012 20:05:47 +0000 (16:05 -0400)]
drm/i915/dp: Probe branch/sink OUIs

Signed-off-by: Adam Jackson <ajax@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/dp: Add DPCD defines for register 0x007
Adam Jackson [Mon, 14 May 2012 20:05:46 +0000 (16:05 -0400)]
drm/dp: Add DPCD defines for register 0x007

Low four bits are downstream port count.  High bit indicates peer OUI
support.  OUI matching will allow us to do additional per-sink handling
for things like DP->VGA bandwidth limits or (hopefully) the iMac-as-
display hack.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/dp: Add DPCD OUI register defines
Adam Jackson [Mon, 14 May 2012 20:05:45 +0000 (16:05 -0400)]
drm/dp: Add DPCD OUI register defines

DisplayPort has an escape hatch by which sources and sinks can identify
each other.  We would prefer not to notice this, but I suspect we're
going to need to.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agogma500: Fix Poulsbo suspend/resume crash on devices with SDVO ports
Alan Cox [Mon, 21 May 2012 14:27:44 +0000 (15:27 +0100)]
gma500: Fix Poulsbo suspend/resume crash on devices with SDVO ports

Reported-by: Guillaume Clément <guillaume@baobob.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agogma500: handle poulsbo cursor restriction
Patrik Jakobsson [Mon, 21 May 2012 14:27:30 +0000 (15:27 +0100)]
gma500: handle poulsbo cursor restriction

Poulsbo needs a physical address in the cursor base register. We allocate a
stolen memory buffer and copy the cursor image provided by userspace into it.
When/If we get our own userspace driver we can map this stolen memory directly.
The patch also adds a mark in chip ops so we can identify devices that has this
requirement.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agogma500: Prevent endless loop in panel power up sequence
Alan Cox [Mon, 21 May 2012 14:27:10 +0000 (15:27 +0100)]
gma500: Prevent endless loop in panel power up sequence

Some devices don't have a panel connected to LVDS and thus will never power up.
This patch checks the power sequence progress bits in PP_STATUS to prevent an
endless loop on such devices.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon/hdmi: compile audio status in 1 function
Rafał Miłecki [Mon, 14 May 2012 19:25:57 +0000 (21:25 +0200)]
drm/radeon/hdmi: compile audio status in 1 function

This optmizes calls, registers reads and assignments.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agonouveau: nouveau_set_bo_placement takes TTM flags
Dave Airlie [Fri, 18 May 2012 14:31:12 +0000 (15:31 +0100)]
nouveau: nouveau_set_bo_placement takes TTM flags

This seems to be wrong to me, spotted while thinking about dma-buf.

Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agoMerge tag 'drm-intel-next-2012-05-20' of git://people.freedesktop.org/~danvet/drm...
Dave Airlie [Mon, 21 May 2012 07:09:06 +0000 (08:09 +0100)]
Merge tag 'drm-intel-next-2012-05-20' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next

Daniel wrote:

The last pull I'd like to squeeze into 3.5, safe for the hsw stuff mostly
bugfixes:
- last few patches for basic hsw enabling (Eugeni, infoframe support by
 Paulo)
- Fix up infoframe support, we've hopefully squashed all the cargo-culting
 in there (Paulo). Among all the issues, this finally fixes some of the
 infoframe regressions seen on g4x and snb systems.
- Fixup sdvo infoframe support, this fixes a regression from 2.6.37.
- Correctly enable semaphores on snb, we've enabled it already for 3.5,
 but the dmar check was slightly wrong.
- gen6 irq fixlets from Chris.
- disable gmbus on i830, the hw seems to be simply broken.
- fix up the pch pll fallout (Chris & me).
- for_each_ring macro from Chris - I've figured I'll merge this now to
 avoid backport pain.
- complain when the rps state isn't what we expect (Chris). Note that this
 is shockingly easy to hit and hence pretty much will cause a regression
 report. But it only tells us that the gpu turbo state got out of whack,
 a problem we know off since a long time (it cause the gpu to get stuck a
 a fixed frequency, usually the lowest one). Chris is working on a fix,
 but we haven't yet found a magic formula that works perfectly (only
 patches that massively reduce the frequency of this happening).
- MAINTAINERS patch, I'm now officially the guy to beat up."

* tag 'drm-intel-next-2012-05-20' of git://people.freedesktop.org/~danvet/drm-intel: (57 commits)
  drm/i915: IBX has a fixed pch pll to pch pipe mapping
  drm/i915: implement hsw_write_infoframe
  drm/i915: small hdmi coding style cleanups
  drm/i915: fixup infoframe support for sdvo
  drm/i915: Enable the PCH PLL for all generations after link training
  drm/i915: Convert BUG_ON(!pll->active) and friends to a WARN
  drm/i915: don't clobber the pipe param in sanitize_modesetting
  drm/i915: disable gmbus on i830
  drm/i915: Replace the feature tests for BLT/BSD with ring init checks
  drm/i915: Check whether the ring is initialised prior to dispatch
  drm/i915: Introduce for_each_ring() macro
  drm/i915: Assert that the transcoder is indeed off before modifying it
  drm/i915: hook Haswell devices in place
  drm/i915: prepare HDMI link for Haswell
  drm/i915: move HDMI structs to shared location
  drm/i915: add WR PLL programming table
  drm/i915: add support for DDI-controlled digital outputs
  drm/i915: detect digital outputs on Haswell
  drm/i915: program iCLKIP on Lynx Point
  drm/i915: program WM_LINETIME on Haswell
  ...

12 years agodrm/i915: IBX has a fixed pch pll to pch pipe mapping
Daniel Vetter [Sun, 20 May 2012 18:00:25 +0000 (20:00 +0200)]
drm/i915: IBX has a fixed pch pll to pch pipe mapping

This should fix breakage introduced in

commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Fri Apr 20 17:11:53 2012 +0100

    drm/i915: manage PCH PLLs separately from pipes

v2: Add a DRM_DEBUG_KMS message to explain why a given pll was
selected, suggested by Chris Wilson.

v3: Actually run git add.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49712
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: implement hsw_write_infoframe
Paulo Zanoni [Mon, 14 May 2012 20:12:51 +0000 (17:12 -0300)]
drm/i915: implement hsw_write_infoframe

Both the control and data registers are completely different now.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: small hdmi coding style cleanups
Paulo Zanoni [Mon, 14 May 2012 20:12:50 +0000 (17:12 -0300)]
drm/i915: small hdmi coding style cleanups

- Changed the coding style of auxiliary infoframe functions to make
  them smaller
- Fixed the column alignment of some function definitions
- Remove definition of "struct drm_crtc" in some places as they're
  used only to retrieve "struct intel_crtc"

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: fixup infoframe support for sdvo
Daniel Vetter [Sat, 12 May 2012 18:22:00 +0000 (20:22 +0200)]
drm/i915: fixup infoframe support for sdvo

At least the worst offenders:
- SDVO specifies that the encoder should compute the ecc. Testing also
  shows that we must not send the ecc field, so copy the dip_infoframe
  struct to a temporay place and avoid the ecc field. This way the avi
  infoframe is exactly 17 bytes long, which agrees with what the spec
  mandates as a minimal storage capacity (with the ecc field it would
  be 18 bytes).
- Only 17 when sending the avi infoframe. The SDVO spec explicitly
  says that sending more data than what the device announces results
  in undefined behaviour.
- Add __attribute__((packed)) to the avi and spd infoframes, for
  otherwise they're wrongly aligned. Noticed because the avi infoframe
  ended up being 18 bytes large instead of 17. We haven't noticed this
  yet because we don't use the uint16_t fields yet (which are the only
  ones that would be wrongly aligned).

This regression has been introduce by

3c17fe4b8f40a112a85758a9ab2aebf772bdd647 is the first bad commit
commit 3c17fe4b8f40a112a85758a9ab2aebf772bdd647
Author: David Härdeman <david@hardeman.nu>
Date:   Fri Sep 24 21:44:32 2010 +0200

    i915: enable AVI infoframe for intel_hdmi.c [v4]

Patch tested on my g33 with a sdvo hdmi adaptor.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=25732
Tested-by: Peter Ross <pross@xvid.org> (G35 SDVO-HDMI)
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/kms: fix Kconfig for new drivers.
Dave Airlie [Sun, 20 May 2012 09:09:25 +0000 (10:09 +0100)]
drm/kms: fix Kconfig for new drivers.

Reported-by: Jiri Slaby <jslaby@suse.cz>
Reported-by: Jonathan Nieder <jrnieder@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/i915: Enable the PCH PLL for all generations after link training
Chris Wilson [Sun, 13 May 2012 08:54:09 +0000 (09:54 +0100)]
drm/i915: Enable the PCH PLL for all generations after link training

Hidden away within one chipset specific path was the necessary logic to
turn on the PLL. This needs to be done everywhere in order for us to
drive any display! As such as soon as we tested on a non-CougarPoint
chipset, we failed to bring up any DisplayPorts and generated a nice set
of assertion failures in the process. At least one part of our logic is
working, the part that assumes that we have no idea what we are doing.

Reported-by: guang.a.yang@intel.com
References: https://bugs.freedesktop.org/show_bug.cgi?id=49712
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Convert BUG_ON(!pll->active) and friends to a WARN
Chris Wilson [Sun, 13 May 2012 19:16:12 +0000 (20:16 +0100)]
drm/i915: Convert BUG_ON(!pll->active) and friends to a WARN

Turn a fatal lockup into a merely blank display with lots of shouty
messages.

v2: Whilst in the area, convert the other BUG_ON into less fatal errors.
In particular, note that we may be called on a PCH platform not using
PLLs, such as Haswell, and so we do not always want to BUG_ON(!pll)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: don't clobber the pipe param in sanitize_modesetting
Daniel Vetter [Sun, 13 May 2012 20:29:25 +0000 (22:29 +0200)]
drm/i915: don't clobber the pipe param in sanitize_modesetting

... we need it later on in the function to clean up pipe <-> plane
associations. This regression has been introduced in

commit f47166d2b0001fcb752b40c5a2d4db986dfbea68
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Mar 22 15:00:50 2012 +0000

    drm/i915: Sanitize BIOS debugging bits from PIPECONF

Spotted by staring at debug output of an (as it turns out) totally
unrelated bug.

v2: I've totally failed to do the s/pipe/i/ correctly, spotted by
Chris Wilson.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Cc: stable@kernel.org (the regression was Cc: stable, too)
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: disable gmbus on i830
Daniel Vetter [Sun, 13 May 2012 12:44:20 +0000 (14:44 +0200)]
drm/i915: disable gmbus on i830

The hw just returns garbage.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838
Reported-and-tested-by: Vladyslav <DFEW.Entwickler@googlemail.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Replace the feature tests for BLT/BSD with ring init checks
Chris Wilson [Fri, 11 May 2012 13:29:32 +0000 (14:29 +0100)]
drm/i915: Replace the feature tests for BLT/BSD with ring init checks

When userspace asks whether the driver supports the BLT or BSD rings for
this chip, simply report whether those particular rings are initialised

v2: Use intel_ring_initialized()

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Check whether the ring is initialised prior to dispatch
Chris Wilson [Fri, 11 May 2012 13:29:31 +0000 (14:29 +0100)]
drm/i915: Check whether the ring is initialised prior to dispatch

Rather than use the magic feature tests HAS_BLT/HAS_BSD just check
whether the ring we are about to dispatch the execbuffer on is
initialised.

v2: Use intel_ring_initialized()

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Introduce for_each_ring() macro
Chris Wilson [Fri, 11 May 2012 13:29:30 +0000 (14:29 +0100)]
drm/i915: Introduce for_each_ring() macro

In many places we wish to iterate over the rings associated with the
GPU, so refactor them to use a common macro.

Along the way, there are a few code removals that should be side-effect
free and some rearrangement which should only have a cosmetic impact,
such as error-state.

Note that this slightly changes the semantics in the hangcheck code:
We now always cycle through all enabled rings instead of
short-circuiting the logic.

v2: Pull in a couple of suggestions from Ben and Daniel for
intel_ring_initialized() and not removing the warning (just moving them
to a new home, closer to the error).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Added note to commit message about the small behaviour
change, suggested by Ben Widawsky.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: Assert that the transcoder is indeed off before modifying it
Chris Wilson [Fri, 11 May 2012 08:21:25 +0000 (09:21 +0100)]
drm/i915: Assert that the transcoder is indeed off before modifying it

Inspired by a recent regression that seems to confuse pch transcoder
state, let's be a bit more paranoid.

References: https://bugs.freedesktop.org/show_bug.cgi?id=49712
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Pimped commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: hook Haswell devices in place
Eugeni Dodonov [Wed, 9 May 2012 18:37:32 +0000 (15:37 -0300)]
drm/i915: hook Haswell devices in place

This patch enables i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: prepare HDMI link for Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:31 +0000 (15:37 -0300)]
drm/i915: prepare HDMI link for Haswell

On Haswell, we need to properly train the DDI buffers prior to enabling
HDMI, and enable the required clocks with correct dividers for the desired
frequency.

Also, we cannot simple reuse HDMI routines from previous generations of
GPU, as most of HDMI-specific stuff is being done via the DDI port
programming instead of HDMI-specific registers.

This commit take advantage of the WR PLL clock table which is in a
separate (previous) commit to select the right divisors for each mode.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: move HDMI structs to shared location
Eugeni Dodonov [Wed, 9 May 2012 18:37:30 +0000 (15:37 -0300)]
drm/i915: move HDMI structs to shared location

Move intel_hdmi data structure and support functions to a shared location,
to allow their usage from intel_ddi module.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add WR PLL programming table
Eugeni Dodonov [Wed, 9 May 2012 18:37:29 +0000 (15:37 -0300)]
drm/i915: add WR PLL programming table

This table is used for programming WR PLL clocks, used by HDMI and DVI outputs.
I split it into a separate patch to simplify the HDMI enabling patch which was
getting huge.

Note that this table is a temporary solution for WR PLL programming. It
will be reworked into a more exact algorithm at a later stage. But for
now, it provides the most accurate clock setting solution, so we use it
here.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add support for DDI-controlled digital outputs
Eugeni Dodonov [Wed, 9 May 2012 18:37:28 +0000 (15:37 -0300)]
drm/i915: add support for DDI-controlled digital outputs

Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: detect digital outputs on Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:27 +0000 (15:37 -0300)]
drm/i915: detect digital outputs on Haswell

Digital port detection on Haswell is indicated by the presence of a bit in
DDI_BUF_CTL for port A, and by a different register for ports B, C and D.
So we check for those bits during the initialization time and let the hdmi
function know about those.

Note that this bit does not indicates whether the output is DP or HDMI.
However, the DDI buffers can be programmed in a way that is shared between
DP/HDMI and FDI/HDMI except for PORT E.

So for now, we detect those digital outputs as being HDMI, but proper DP
support is still pending.

Note that DDI A can only drive eDP, so we do not handle it here for hdmi
initialization.

v2: simplify Haswell handling logic

v3: use generic function for handling digital outputs.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: program iCLKIP on Lynx Point
Eugeni Dodonov [Wed, 9 May 2012 18:37:26 +0000 (15:37 -0300)]
drm/i915: program iCLKIP on Lynx Point

The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
to do so, it must be programmed to properly do the clock ticks according
to the divisor, phase direction, phase increments and a special auxiliary
divisor for 20MHz clock.

v2: calculate divisor values directly instead of relying on a table.

v3: merged a fix from Ben to properly check for invalid divider values.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: program WM_LINETIME on Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:24 +0000 (15:37 -0300)]
drm/i915: program WM_LINETIME on Haswell

The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.

v2: improve comment as per Chris Wilson suggestion

v3: incorporate latest changes in specs.

v4: move into wm update routine, also mention that the same routine can
program IPS watermarks. We do not have their enablement code yet, nor
handle the required clock settings at the moment, so this patch won't
program those values for now.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: define Haswell watermarks and clock gating
Eugeni Dodonov [Wed, 9 May 2012 18:37:23 +0000 (15:37 -0300)]
drm/i915: define Haswell watermarks and clock gating

For now, we simple reuse the Ivy Bridge routines here.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: use ironlake eld write routine for Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:22 +0000 (15:37 -0300)]
drm/i915: use ironlake eld write routine for Haswell

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: support DDI training in FDI mode
Eugeni Dodonov [Wed, 9 May 2012 18:37:21 +0000 (15:37 -0300)]
drm/i915: support DDI training in FDI mode

Starting with Haswell, DDI ports can work in FDI mode to support
connectivity with the outputs located on the PCH.

This commit adds support for such connections in the intel_ddi module, and
provides Haswell-specific functionality to make it work.

v2: simplify the commit as per Daniel Vetter suggestion.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: initialize DDI buffer translations
Eugeni Dodonov [Wed, 9 May 2012 18:37:20 +0000 (15:37 -0300)]
drm/i915: initialize DDI buffer translations

DDI is introduced starting with Haswell GPU generation. So to simplify its
management in the future, we also add intel_ddi.c to hold all the
DDI-related items.

Buffer translations for DDI links must be initialized prior to enablement.
For FDI and DP, first 9 pairs of values are used to select the connection
parameters. HDMI uses the last pair of values and ignores the first 9
pairs. So we program HDMI values in both cases, which allows HDMI to work
over both FDI and DP-friendly buffers.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: account for only one PCH receiver on Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:19 +0000 (15:37 -0300)]
drm/i915: account for only one PCH receiver on Haswell

On Haswell, only one pipe can work in FDI mode, so this patch prevents
messing with wrong registers when FDI is being used by non-first pipe. And
to prevent this, we also specify that the VGA can only be used on pipe 0
for now in the crtc_mask value.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: handle DDI-related assertions
Eugeni Dodonov [Wed, 9 May 2012 18:37:18 +0000 (15:37 -0300)]
drm/i915: handle DDI-related assertions

Prevent bogus asserts on DDI-related paths.

Longer explanation from Eugeni by mail:

"For the asserts there are 3 paths where we hit them:
- in assert_fdi_tx (we don't have the FDI_TX_CTL anymore, backup plan
  DDI_FUNC_CTL is used instead)
- in assert_fdi_tx_pll_enabled (we have the combination of iCLKIP and
  DDI_FUNC_CTL, plus PORT_CLK_SEL and PIPE_CLK_SEL now to make things
  work). We could use an assert here indeed - if we configure port to
  use one clock, and pipe to use another, everything hangs. Right now,
  we configure all of them in one place only; but yes, when DP code
  lands it will get more funky.
- and in ironlake_fdi_pll_enable. I reuse part of this function (to
  configure the TU sizes), but as in the 1st case, FDI_TX_CTL is gone
  so I just ignore it here."

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
[danvet: Pasted Eugeni's explanation into the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add LPT PCH checks
Eugeni Dodonov [Wed, 9 May 2012 18:37:17 +0000 (15:37 -0300)]
drm/i915: add LPT PCH checks

Avoid bogus asserts and PCH PLL accesses on Lynx Point.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: enable power wells on Haswell init
Eugeni Dodonov [Wed, 9 May 2012 18:37:16 +0000 (15:37 -0300)]
drm/i915: enable power wells on Haswell init

This attempts to enable all the available power wells during the
initialization.

Those power wells can be enabled in parallel or on-demand, and disabled
when no longer needed, but this is out of scope of this initial
enablement. Proper tracking of who uses which power well will require
a considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.

v2: use more generic and future-proof code

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: detect PCH encoders on Haswell
Eugeni Dodonov [Wed, 9 May 2012 23:30:31 +0000 (20:30 -0300)]
drm/i915: detect PCH encoders on Haswell

On Haswell, the recommended PCH-connected output is the one driven by DDI
E in FDI mode, used for VGA connection. All the others are handled by the
CPU.

Note that this does not accounts for Haswell/PPT combination yet, so if we
encounter such combination an error message is thrown to indicate that
things could go wrong.

v2: improve non-LPT detection warning per Daniel Vetter's suggestion.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: do not use fdi_normal_train on Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:14 +0000 (15:37 -0300)]
drm/i915: do not use fdi_normal_train on Haswell

This should be already configured when FDI auto-negotiation is done.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: show unknown sdvox registers on hdmi init
Eugeni Dodonov [Wed, 9 May 2012 18:37:13 +0000 (15:37 -0300)]
drm/i915: show unknown sdvox registers on hdmi init

This will throw a BUG() message when an unknown sdvox register is
given to intel_hdmi_init. When this happens, things could going to be pretty
much broken afterwards, so we better detect this as soon as possible.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: properly check for pipe count
Eugeni Dodonov [Wed, 9 May 2012 18:37:12 +0000 (15:37 -0300)]
drm/i915: properly check for pipe count

As suggested by Chris Wilson and Daniel Vetter, this chunk of code can be
simplified with a more simple check.

Also, as noticed by Jesse Barnes, it is worth mentioning that plane is an
enum and num_pipe is an int, so we could be more paranoid here about those
validation checks eventually.

CC: Daniel Vetter <daniel.vetter@ffwll.ch>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: calculate watermarks for devices that have 3 pipes
Eugeni Dodonov [Wed, 9 May 2012 18:37:11 +0000 (15:37 -0300)]
drm/i915: calculate watermarks for devices that have 3 pipes

This adds proper support for calculating those watermarks, checking for
number of available pipes instead of specific GPU variants when deciding
if watermarks for 3rd pipe are necessary.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add support for SBI ops
Eugeni Dodonov [Wed, 9 May 2012 18:37:10 +0000 (15:37 -0300)]
drm/i915: add support for SBI ops

With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.

v2: de-inline the function and address changes in bits names

v3: protect operations with dpio_lock, increase timeout to 100 for
paranoia sake.

v4: decrease paranoia a bit, as noticed by Chris Wilson

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: reuse Ivy Bridge interrupts code for Haswell
Eugeni Dodonov [Wed, 9 May 2012 18:37:09 +0000 (15:37 -0300)]
drm/i915: reuse Ivy Bridge interrupts code for Haswell

Haswell interrupts are mostly similar with Ivy Bridge, so we share same
routines with it.

This patch also simplifies the vblank counter handling for all the Gen5+
architectures.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: add new Haswell DIP controls registers
Eugeni Dodonov [Thu, 10 May 2012 13:18:02 +0000 (10:18 -0300)]
drm/i915: add new Haswell DIP controls registers

Haswell has different DIP control registers and offsets which we need to
use for infoframes, which this patch adds.

Note that this does not adds full DIP frames support, but only the basic
functionality necessary for HDMI to work in early enablement.

v2: replace infoframe handling with a debug message, proper support will
be added via a patch from Paulo Zanoni later.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/i915: gen6_enable_rps() wants to be called after ring initialisation
Chris Wilson [Wed, 9 May 2012 10:56:28 +0000 (11:56 +0100)]
drm/i915: gen6_enable_rps() wants to be called after ring initialisation

Currently we call gen6_enable_rps() (which writes into the per-ring
register mmio space) from intel_modeset_init_hw() which is called before
we initialise the rings. If we defer intel_modeset_init_hw() until
afterwards (in the intel_modeset_gem_init() phase) all is well.

v2: Rectify ordering of gem vs display HW init upon resume. (Daniel)

v3: Fix up locking. (Paulo)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Smash Paulo's locking fix onto Chris' patch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
12 years agodrm/cirrus/ast/mgag200: fix build without CONFIG_VGA_CONSOLE
Dave Airlie [Sat, 19 May 2012 15:33:21 +0000 (16:33 +0100)]
drm/cirrus/ast/mgag200: fix build without CONFIG_VGA_CONSOLE

Reported-by: Randy Dunlap
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/prime: expose capability flags for userspace.
Dave Airlie [Mon, 2 Apr 2012 13:11:50 +0000 (14:11 +0100)]
drm/prime: expose capability flags for userspace.

This lets the kernel tell userspace if the device supports prime
import/export.

This is useful for -modesetting at least, but would be nice for other
drivers.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon/hdmi: use new AFMT structs
Rafał Miłecki [Mon, 14 May 2012 14:52:30 +0000 (16:52 +0200)]
drm/radeon/hdmi: use new AFMT structs

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon/hdmi: store info about all AFMT blocks
Alex Deucher [Mon, 14 May 2012 14:52:29 +0000 (16:52 +0200)]
drm/radeon/hdmi: store info about all AFMT blocks

Introduce special struct radeon_afmt for this purpose.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/exynos: add G2D driver
Joonyoung Shim [Thu, 17 May 2012 11:06:32 +0000 (20:06 +0900)]
drm/exynos: add G2D driver

Changelog v3:
- use __u64 instead of pointer in ioctl struct.

The G2D is a 2D graphic accelerator that supports Bit Block Transfer.
This G2D driver is exynos drm specific and supports only G2D(version
4.1) of later Exynos series from Exynos4X12 because supporting DMA.

The G2D is performed by two tasks simply.
1. Configures the rendering parameters, such as foreground color and
   coordinates data by setting the drawing context registers.
2. Start the rendering process by setting thre relevant command
   registers accordingly.

The G2D version 4.1 supports DMA mode as host interface. User can make
command list to reduce HOST(ARM) loads. The contents of The command list
is setted to relevant registers of G2D by DMA.

The command list is composed Header and command sets and Tail.
- Header: The number of command set(4Bytes)
- Command set: Register offset(4Bytes) + Register data(4Bytes)
- Tail: Pointer of base address of the other command list(4Bytes)

By Tail field, the G2D can process many command lists without halt at
one go.

The G2D has following the rendering pipeline.
--> Primitive Drawing --> Rotation --> Clipping --> Bilinear Sampling
--> Color Key --> ROP --> Mask Operation --> Alpha Blending -->
Dithering --> FrameBuffer

And supports various operations from the rendering pipeline.
- copy
- fast solid color fill
- window clipping
- rotation
- flip
- 4 operand raster operation(ROP4)
- masking operation
- alpha blending
- color key
- dithering
- etc

User should make the command list to data and registers needed by
operation to use. The Exynos G2D driver only manages the command lists
received from user. Some registers needs memory base address(physical
address) of image. User doesn't know its physical address, so fills the
gem handle of that memory than address to command sets, then G2D driver
converts it to memory base address.

We adds three ioctls and one event for Exynos G2D.

- ioctls
DRM_EXYNOS_G2D_GET_VER: get the G2D hardware version
DRM_EXYNOS_G2D_SET_CMDLIST: set the command list from user to driver
DRM_EXYNOS_G2D_EXEC: execute the command lists setted to driver

- event
DRM_EXYNOS_G2D_EVENT: event to give notification completion of the
      command list to user

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
12 years agodrm/exynos: added vp scaling feature for hdmi
Seung-Woo Kim [Tue, 24 Apr 2012 09:52:22 +0000 (18:52 +0900)]
drm/exynos: added vp scaling feature for hdmi

This patch adds vp scaling feature for exynos hdmi. Scaling ratio
between source and destination is used for width and height.
Also meaningless variables to set registers are cleaned.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
12 years agodrm/exynos: added source size to overlay structure
Seung-Woo Kim [Tue, 24 Apr 2012 09:43:10 +0000 (18:43 +0900)]
drm/exynos: added source size to overlay structure

Set plane has source size but exynos overlay structure did
not consider it. This patch adds source size to overlay
structure. For set crtc, source size is set from crtc size.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
12 years agodrm/exynos: add additional display mode for hdmi
Seung-Woo Kim [Tue, 24 Apr 2012 08:55:06 +0000 (17:55 +0900)]
drm/exynos: add additional display mode for hdmi

1080p@30Hz mode is added to hdmi display mode.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
12 years agodrm/exynos: enable dvi mode for dvi monitor
Seung-Woo Kim [Tue, 24 Apr 2012 08:39:15 +0000 (17:39 +0900)]
drm/exynos: enable dvi mode for dvi monitor

Hdmi monitor and dvi monitor can be distinguished with edid.
This patch enables dvi mode if dvi monitor is connected and does
not enable audio feature for dvi mode because dvi has no audio
feature.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
12 years agodrm/exynos: fixed wrong pageflip finish event for interlace mode
Seung-Woo Kim [Mon, 23 Apr 2012 11:30:13 +0000 (20:30 +0900)]
drm/exynos: fixed wrong pageflip finish event for interlace mode

Pageflip finish event for interlace mode has bug on checking top
field vsync because of comparing between dma address converted
by start coordinates and non-converted dma address.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
12 years agodrm/radeon: make use of radeon_gem_init() consistent
Alex Deucher [Thu, 10 May 2012 17:00:06 +0000 (13:00 -0400)]
drm/radeon: make use of radeon_gem_init() consistent

All radeon_gem_init() does is initialize the gem objects
list.  radeon_device.c does this explicitly.  r600+ calls
radeon_gem_init() so the list gets initialized twice.  Older
asics don't call it at all and rely on the the init in
radeon_device.c.  Just call radeon_gem_init() in radeon_device.c
and remove the explicit calls from all the newer asics.

All asics call radeon_gem_fini() in their fini pathes.  That
could possibly be cleaned up too.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon: eliminate redundant connector_names table
Ilija Hadzic [Fri, 4 May 2012 15:25:12 +0000 (11:25 -0400)]
drm/radeon: eliminate redundant connector_names table

connector_names table is just a repeat of information that
already exists in drm_connector_enum_list and the same string
can be retrieved using drm_get_connector_name function.

Nuke the redundant table and use the proper function to retrieve
the connector name.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
12 years agodrm/radeon: Also reset BCI on SI GPU reset.
Michel Dänzer [Tue, 15 May 2012 15:31:02 +0000 (17:31 +0200)]
drm/radeon: Also reset BCI on SI GPU reset.

Without this, e.g. egltri_screen looks scrambled after a GPU reset.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>