GitHub/moto-9609/android_kernel_motorola_exynos9610.git
10 years agodrm/i915: Track which port is using which pipe's power sequencer
Ville Syrjälä [Thu, 4 Sep 2014 11:54:20 +0000 (14:54 +0300)]
drm/i915: Track which port is using which pipe's power sequencer

VLV/CHV have a per-pipe panel power sequencer which locks onto the
port once used. We need to keep track wich power sequencers are
locked to which ports.

v2: remove spurious whitespace change, rebase due to backlight changes (Imre)

Reviewed-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Break some really long lines to appease checkpatch a bit.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix edp vdd locking
Ville Syrjälä [Thu, 4 Sep 2014 11:53:14 +0000 (14:53 +0300)]
drm/i915: Fix edp vdd locking

Introduce a new mutex (pps_mutex) to protect the power sequencer
state. For now this state includes want_panel_vdd as well as the
power sequencer registers.

We need a single mutex (as opposed to per port) because later on we
will need to deal with VLV/CHV which have multiple power sequencer
which can be reassigned to different ports.

v2: Add the locking to intel_dp_encoder_suspend too (Imre)
v3: Take care intel_edp_backlight_power() and
    _intel_edp_backlight_on/off(), deal with reboot notifier
    vlv_power_sequencer_pipe() call (Imre)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Reset the HEAD pointer for the ring after writing START
Chris Wilson [Thu, 7 Aug 2014 14:39:54 +0000 (15:39 +0100)]
drm/i915: Reset the HEAD pointer for the ring after writing START

Ville found an old w/a documented for g4x that suggested that we need to
reset the HEAD after writing START. This is a useful fixup for some of
the g4x ring initialisation woes, but as usual, not all.

v2: Do the rewrite unconditionally anyway

References: https://bugs.freedesktop.org/show_bug.cgi?id=76554
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix unsafe vma iteration in i915_drop_caches
Chris Wilson [Wed, 3 Sep 2014 18:23:37 +0000 (19:23 +0100)]
drm/i915: Fix unsafe vma iteration in i915_drop_caches

When unbinding, there is a possibility that we drop the active reference
on the object, thereby freeing it. If that happens, we may destroy the
vm link as well as the object and vma. So iterate carefully.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: init sprites with univeral plane init function
Derek Foreman [Wed, 3 Sep 2014 13:38:20 +0000 (10:38 -0300)]
drm/i915: init sprites with univeral plane init function

Really just for completeness - old init function ends up making the plane
exactly the same way due to the way the enums are set up.

Signed-off-by: Derek Foreman <derek.foreman@collabora.co.uk>
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs
Ville Syrjälä [Wed, 3 Sep 2014 11:09:53 +0000 (14:09 +0300)]
drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs

Check for !HAS_PCH_SPLIT() instead of 'gen < 5' in the PCH transcoder
enable functions.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code
Ville Syrjälä [Wed, 3 Sep 2014 11:09:52 +0000 (14:09 +0300)]
drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code

A few open coded HAS_GMCH_DISPLAY() remain in the underrun reporting
code. Convert them over.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code
Ville Syrjälä [Wed, 3 Sep 2014 11:09:51 +0000 (14:09 +0300)]
drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code

IS_GEN8() is a bad check in the forcewake code due to bdw vs. chv
differences. Use IS_BROADWELL() instead.

The only actual bug here is that we currently call
__gen7_gt_force_wake_mt_reset() on chv. On the other places we
have checked for chv before using IS_GEN8(), but change them
to use IS_BROADWELL() anyway to reduce the chance of accidents in the
future.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't call gen8_fbc_sw_flush() on chv
Ville Syrjälä [Wed, 3 Sep 2014 11:09:50 +0000 (14:09 +0300)]
drm/i915: Don't call gen8_fbc_sw_flush() on chv

CHV doesn't have FBC, so don't go calling gen8_fbc_sw_flush() on it.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add a FIXME comment while at it that we should rework this a
lot more.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Remove shadowed local variable 'i' from i915_interrupt_info
Chris Wilson [Wed, 3 Sep 2014 10:59:36 +0000 (11:59 +0100)]
drm/i915: Remove shadowed local variable 'i' from i915_interrupt_info

Just a stray local variable, begone.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Rename global latency_ns variable
Chris Wilson [Wed, 3 Sep 2014 10:56:07 +0000 (11:56 +0100)]
drm/i915: Rename global latency_ns variable

We use the variable name latency_ns in both the local lowlevel wm
calculation routines and at the global level. Rename the global value to
reduce shadow warnings and future confusion.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't restrict i915_wa_registers to BDW
Damien Lespiau [Sat, 30 Aug 2014 15:51:03 +0000 (16:51 +0100)]
drm/i915: Don't restrict i915_wa_registers to BDW

We have CHV code that already makes the test obsolete. Besides, when
num_wa_regs is 0 (platforms not gathering that W/A data), we expose
something sensible already.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Remove unneeded brackets
Damien Lespiau [Sat, 30 Aug 2014 15:51:02 +0000 (16:51 +0100)]
drm/i915: Remove unneeded brackets

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't silently discard workarounds
Damien Lespiau [Sat, 30 Aug 2014 15:51:01 +0000 (16:51 +0100)]
drm/i915: Don't silently discard workarounds

If we happen to emit more than I915_MAX_WA_REGS workarounds, we will
currently discard them, not even emit the LRI. Not really what we want,
so warn loudly.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't overrun the intel_wa_regs array
Damien Lespiau [Sat, 30 Aug 2014 15:51:00 +0000 (16:51 +0100)]
drm/i915: Don't overrun the intel_wa_regs array

When entering intel_ring_emit_wa() with num_wa_regs equal to
I915_MAX_WA_REGS, we end up indexing the intel_wa_regs array beyond its
allocation.

Fix the check then.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Rename intel_wa_registers with a i915_ prefix
Damien Lespiau [Sat, 30 Aug 2014 15:50:59 +0000 (16:50 +0100)]
drm/i915: Rename intel_wa_registers with a i915_ prefix

Those debugfs files are prefixed by i915, the name of the kernel module,
presumably to make the difference with files exposed by core DRM.

Also, add a ',' at the end of the last entry. This is to ease the
conflict resolution when rebasing internal patches that add a member at
the end of the array. Without it, wiggle can't do its job as we need to
modify an existing line (appending the ',').

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: change CHV write_eld/global_resources function pointers
Paulo Zanoni [Tue, 2 Sep 2014 19:53:57 +0000 (16:53 -0300)]
drm/i915: change CHV write_eld/global_resources function pointers

Currently, CHV is using the same functions as HSW/BDW instead of the
same functions as VLV. This looks wrong, especially since, for
example, valleyview_modeset_global_resouces even has an IS_CHERRYVIEW
check.

This patch has the potential to fix display audio and the CHV CDCLK.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/hdmi: Cache EDID for a detection cycle
Chris Wilson [Tue, 2 Sep 2014 19:04:01 +0000 (20:04 +0100)]
drm/i915/hdmi: Cache EDID for a detection cycle

As we may query the edid multiple times following a detect, record the
EDID found during output discovery and reuse it. This is a separate
issue from caching the output EDID across detection cycles.

v2: Also hookup the force() callback for audio detection when the user
forces the connection status.
v3: Ville spots a typo, s/==/!=/

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: Cache EDID for a detection cycle
Chris Wilson [Tue, 2 Sep 2014 19:04:00 +0000 (20:04 +0100)]
drm/i915/dp: Cache EDID for a detection cycle

As we may query the edid multiple times following a detect, record the
EDID found during output discovery and reuse it. This is a separate
issue from caching the output EDID across detection cycles.

v2: Implement connector->force() callback so that edid is associated
with the connector for user overrides as well (Ville)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: Refactor common eDP lid detection
Chris Wilson [Tue, 2 Sep 2014 19:03:59 +0000 (20:03 +0100)]
drm/i915/dp: Refactor common eDP lid detection

Both gmch and pch detection routines used the exact same routine for
eDP, so de-duplicate.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: : Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Remove old defines for vswing and pre-emph values
Sonika Jindal [Fri, 8 Aug 2014 10:53:46 +0000 (16:23 +0530)]
drm: Remove old defines for vswing and pre-emph values

This is the last patch in the series, so remove old defines

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Renaming DP training vswing pre emph defines
Sonika Jindal [Fri, 8 Aug 2014 10:53:41 +0000 (16:23 +0530)]
drm/i915: Renaming DP training vswing pre emph defines

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/tegra: Renaming DP training vswing pre emph defines
Sonika Jindal [Fri, 8 Aug 2014 10:53:45 +0000 (16:23 +0530)]
drm/tegra: Renaming DP training vswing pre emph defines

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/radeon: Renaming DP training vswing pre emph defines
Sonika Jindal [Fri, 8 Aug 2014 10:53:44 +0000 (16:23 +0530)]
drm/radeon: Renaming DP training vswing pre emph defines

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_1200     (3 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Acked-by: Alex Deucher <alexdeucher@gmail.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/gma500: Renaming DP training vswing pre emph defines
Sonika Jindal [Fri, 8 Aug 2014 10:53:43 +0000 (16:23 +0530)]
drm/gma500: Renaming DP training vswing pre emph defines

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/exynos: Renaming DP training vswing pre emph defines
Sonika Jindal [Fri, 8 Aug 2014 10:53:42 +0000 (16:23 +0530)]
drm/exynos: Renaming DP training vswing pre emph defines

Rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Renaming DP training vswing pre emph defines
Sonika Jindal [Fri, 8 Aug 2014 10:53:40 +0000 (16:23 +0530)]
drm: Renaming DP training vswing pre emph defines

Adding new defines, older one will be removed in the last patch in the series.
This is to rename the defines to have levels instead of values for vswing and
pre-emph levels as the values may differ in other scenarios like low vswing of
eDP1.4 where the values are different.

Done using following cocci patch for each define:
@@
@@

 # define DP_TRAIN_VOLTAGE_SWING_400     (0 << 0)
+ # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0     (0 << 0)

...
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: debug sink dpms aux errors also on enable
Jani Nikula [Tue, 2 Sep 2014 13:33:52 +0000 (16:33 +0300)]
drm/i915: debug sink dpms aux errors also on enable

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't call intel_plane_restore() when the prop value didn't change
Ville Syrjälä [Mon, 1 Sep 2014 15:08:25 +0000 (18:08 +0300)]
drm/i915: Don't call intel_plane_restore() when the prop value didn't change

No point in calling intel_plane_restore() in .set_property() if the
value didn't change.

More importantly this papers over a bug where the current primary plane
code forgets to update the user coordinates we store under intel_plane
unless the primary plane .update_plane() hook is actually called. This
means we have 0 in the coordinates straight after boot and any call
to intel_restore_plane() (such as from restore_fbdev_mode()) will
actually turn off the primary plane. This mess needs to be fixed properly
but that's a bigger task and the first step there is killing off
intel_pipe_set_base() and just calling the primary plane
.update_plane() hook. For the immediate problem of black screen after
boot this small patch is enough to hide it.

The problem originates from these two commits:
 commit 3a5f87c286515c54ff5c52c3e64d0c522b7570c0
 Author: Thomas Wood <thomas.wood@intel.com>
 Date:   Wed Aug 20 14:45:00 2014 +0100

    drm: fix plane rotation when restoring fbdev configuration

 commit d91a2cb8e5104233c02bbde539bd4ee455ec12ac
 Author: Sonika Jindal <sonika.jindal@intel.com>
 Date:   Fri Aug 22 14:06:04 2014 +0530

    drm/i915: Add 180 degree primary plane rotation support

Cc: Thomas Wood <thomas.wood@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Tested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Tested-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: i915: reduce memory footprint when debugging
Andy Shevchenko [Mon, 1 Sep 2014 11:12:01 +0000 (14:12 +0300)]
drm: i915: reduce memory footprint when debugging

There is no need to use hex_dump_to_buffer() since we have a kernel helper to
dump up to 64 bytes just via printk(). In our case the actual size is 15 bytes.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Add cast since %*ph expects and int for the size parameter.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't use WaGsvRC0ResidenncyMethod on chv
Ville Syrjälä [Fri, 29 Aug 2014 11:14:07 +0000 (14:14 +0300)]
drm/i915: Don't use WaGsvRC0ResidenncyMethod on chv

WaGsvRC0ResidenncyMethod is for vlv, it doesn't deal with chv
appropriately (eg. doesn't limit rps values to even numbers).

Fix a typo in the w/a name while at it.

Cc: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Preserve VGACNTR bits from the BIOS
Ville Syrjälä [Thu, 14 Aug 2014 22:22:08 +0000 (01:22 +0300)]
drm/i915: Preserve VGACNTR bits from the BIOS

My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from
S3 unless VGACNTR has been restore to the original value. The BIOS
value in this case was 0x0124008E. Setting the "VGA disable" bit
doesn't interfere with the S3 resume fortunately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add pipe B force quirk for 830M
Ville Syrjälä [Thu, 14 Aug 2014 22:22:07 +0000 (01:22 +0300)]
drm/i915: Add pipe B force quirk for 830M

830M has problems when some of the pipes are disabled. Namely if a
plane, DVO port etc. is currently assigned to a disabled pipe, it
can't moved to the other pipe until the current pipe is also enabled.
To keep things simple just leave both pipes running all the time.

Ideally I think should turn the pipes off if neither is active, and
when either becomes active we enable both. But that would reuquire
proper atomic modeset support, and probably a bit of extra care in
the order things get enabled.

v2: Reorder wrt. double wide handling changes

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agoRevert "drm/i915: Nuke pipe A quirk on i830M"
Ville Syrjälä [Thu, 14 Aug 2014 22:22:06 +0000 (01:22 +0300)]
Revert "drm/i915: Nuke pipe A quirk on i830M"

830 really does want the pipe A quirk. The planes and ports don't
react to any register writes unless the pipe currently attached
to them is running, so it's impossible to move them to the other
pipe unless both pipes are running.

Also it's documented that the DPLL must be enabled on both pipes
whenever it's needed.

This reverts commit ac6696d3236bd61503f89a1a99680fd7894d5d53.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Check pixel clock in ns2501 mode_valid hook
Ville Syrjälä [Thu, 14 Aug 2014 22:22:04 +0000 (01:22 +0300)]
drm/i915: Check pixel clock in ns2501 mode_valid hook

The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes,
60Hz and 56Hz. The magic register values we have correspond to the 60Hz
mode, and as I don't know how one would trick the VGA BIOS to set up
the 56Hz mode we can't get the magic values for the orther mode. So
when checking whether a mode is valid also check the pixel clock so that
we filter out the 56Hz variant.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Init important ns2501 registers
Ville Syrjälä [Thu, 14 Aug 2014 22:22:03 +0000 (01:22 +0300)]
drm/i915: Init important ns2501 registers

In my earlier rewrite I missed a few important registers. Thomas Richter
noticed that they're needed to make his machine resume correctly.

Looks like IEGD does a one time init of these three registers. We don't
have a good one time init place in the ns2501 driver, so let's just
stick them into the .mode_set() hook and see if that helps things along.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Rewrite ns2501 driver a bit
Ville Syrjälä [Thu, 14 Aug 2014 22:22:02 +0000 (01:22 +0300)]
drm/i915: Rewrite ns2501 driver a bit

Try to use the same programming sequence as used by the IEGD driver.

Also shovel the magic register values into a big static const array.

The register values are actually the based on what the BIOS programs
on the Fujitsu-Siemens Lifebook S6010. IEGD seemed to have hardcoded
register values (which also enabled the scaler for 1024x768 mode).
However those didn't actually work so well on the S6010. Possibly the
pipe timings that got used didn't match the ns2501 configuration.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Kill useless ns2501_dump_regs
Ville Syrjälä [Thu, 14 Aug 2014 22:22:01 +0000 (01:22 +0300)]
drm/i915: Kill useless ns2501_dump_regs

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't call DVO mode_set hook on DPMS changes
Ville Syrjälä [Thu, 14 Aug 2014 22:22:00 +0000 (01:22 +0300)]
drm/i915: Don't call DVO mode_set hook on DPMS changes

Calling the mode_set hook on DPMS changes doesn't seem to be necessary
for ns2501. Just drop it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Enable DVO between mode_set and dpms hooks
Ville Syrjälä [Thu, 14 Aug 2014 22:21:59 +0000 (01:21 +0300)]
drm/i915: Enable DVO between mode_set and dpms hooks

To more closely match the IEGD ns2501 driver behaviour, call the
mode_set hook while the DVO port is still disabled, then enable the DVO
port, and finally call the dpms hook.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: ns2501 is on DVOB
Ville Syrjälä [Thu, 14 Aug 2014 22:21:58 +0000 (01:21 +0300)]
drm/i915: ns2501 is on DVOB

On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead
of DVOC.

FIXME: Maybe need to dig out the correct DVO port from VBT

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Disable double wide even when leaving the pipe on
Ville Syrjälä [Thu, 14 Aug 2014 22:21:57 +0000 (01:21 +0300)]
drm/i915: Disable double wide even when leaving the pipe on

Disable double wide even if the pipe quirk compels us to leave the
pipe running. Double wide has certain implications for the plane
assignments so best keep it off.

Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010
when double wide was enabled prior to suspend.

We do leave the pixel clock ticking at the original rate which would
require double wide to be enabled. But since the planes are all disabled
I'm hoping that the overly fast clock won't cause any problems. Seems
to be fine so far.

v2: Disable double wide also when turning the pipe off
v3: Reorder wrt. force pipe B quirk

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()
Ville Syrjälä [Thu, 14 Aug 2014 22:21:56 +0000 (01:21 +0300)]
drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()

Just pass the intel_crtc around instead of dev_priv+pipe.

Also make intel_wait_for_pipe_off() static since it's only used in
intel_display.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Idle unused rings on gen2/3 during init/resume
Ville Syrjälä [Thu, 14 Aug 2014 22:21:55 +0000 (01:21 +0300)]
drm/i915: Idle unused rings on gen2/3 during init/resume

gen2/3 platforms have a boatload of rings we're not using. On my 830
the BIOS/hw can leave some of those "active" after resume which will
prevent c3 entry. The ring is apparently considered active whenever
head != tail even if the ring is disabled.

Disable and clear all such unused ringbuffers on init/resume.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Disable trickle feed for gen2/3
Ville Syrjälä [Thu, 14 Aug 2014 22:21:54 +0000 (01:21 +0300)]
drm/i915: Disable trickle feed for gen2/3

My 830 is unhappy with trickle feed enabled. The symptom is that
the image on the screen shifts a bit to right occasionally.

The BIOS initially disables trickle feed, but it gets reset during
suspend, so we need to re-disable it ourselves. Juse disable it
always.

Also disable it for all other gen2/3 platforms since we disable it
for all more recent platforms as well (until HSW that is). At least
my 855 doesn't seem to mind us doing this. I don't have gen3
hardware to test that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix gen2 planes B and C max watermark value
Ville Syrjälä [Thu, 14 Aug 2014 22:21:53 +0000 (01:21 +0300)]
drm/i915: Fix gen2 planes B and C max watermark value

The max watermark value for gen2 planes B and C is 0x1f, instead of
the 0x3f that plane A uses.

Also check against the max even if the pipe is disabled since the
FIFO size exceeds the plane B and C max watermark value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: make fbdev initialization asynchronous v2
Jesse Barnes [Wed, 28 May 2014 21:39:03 +0000 (14:39 -0700)]
drm/i915: make fbdev initialization asynchronous v2

This gets us out of our init code and out to userspace quite a bit
faster, but does open us up to some bugs given the state of our init
time locking.

v2: switch to async_schedule (Chris)
    check with lockdep, seems happy (Jesse)
    move hotplug enable flag set to fbdev_initial_config (Jesse)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Rebase on top of the dev_priv->enable_hotplug_processing
removal.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Init some CHV workarounds via LRIs in ring->init_context()
Ville Syrjälä [Wed, 27 Aug 2014 14:33:12 +0000 (17:33 +0300)]
drm/i915: Init some CHV workarounds via LRIs in ring->init_context()

Follow the BDW example and apply the workarounds touching registers
which are saved in the context image through LRIs in the new
ring->init_context() hook.

This makes Mesa much happier and eg. glxgears doesn't hang after
the first frame.

Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add missing wa table initialization to avoid a functional
conflict with Arun's wa table debugfs support.]
Reviewed-by: "Barbalho, Rafael" <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: trivial: remove unneed set to NULL
Gustavo Padovan [Thu, 28 Aug 2014 17:40:06 +0000 (14:40 -0300)]
drm/i915: trivial: remove unneed set to NULL

At this point of the code the obj var is already NULL, so we don't
need to set it again to NULL.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Warn about odd rps values on CHV
Ville Syrjälä [Mon, 18 Aug 2014 11:42:43 +0000 (14:42 +0300)]
drm/i915: Warn about odd rps values on CHV

CHV wants even rps opcodes so print a warning of the
min/max/rpe/rp1 values are odd, and warn if an odd value
slips through to valleyview_set_rps() and truncate it to
an even value.

Also add a comment to chv_freq_opcode() to make sure no one
changes the code without considering this requirement.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Help git along in applying the patch, somehow it silently
ended up in the vlv init_gt_powersave function.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agoMAINTAINERS: Update Daniel Vetter's email address
Daniel Vetter [Thu, 28 Aug 2014 10:17:42 +0000 (12:17 +0200)]
MAINTAINERS: Update Daniel Vetter's email address

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
10 years agodrm/i915/bdw: Render state init for Execlists
Oscar Mateo [Thu, 21 Aug 2014 10:40:54 +0000 (11:40 +0100)]
drm/i915/bdw: Render state init for Execlists

The batchbuffer that sets the render context state is submitted
in a different way, and from different places.

We needed to make both the render state preparation and free functions
outside accesible, and namespace accordingly. This mess is so that all
LR, LRC and Execlists functionality can go together in intel_lrc.c: we
can fix all of this later on, once the interfaces are clear.

v2: Create a separate ctx->rcs_initialized for the Execlists case, as
suggested by Chris Wilson.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
v3: Setup ring status page in lr_context_deferred_create when the
default context is being created. This means that the render state
init for the default context is no longer a special case.  Execute
deferred creation of the default context at the end of
logical_ring_init to allow the render state commands to be submitted.
Fix style errors reported by checkpatch. Rebased.

Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: BDW Software Turbo
Daisy Sun [Mon, 11 Aug 2014 18:08:38 +0000 (11:08 -0700)]
drm/i915/bdw: BDW Software Turbo

BDW supports GT C0 residency reporting in constant time unit. Driver
calculates GT utilization based on C0 residency and adjusts RP
frequency up/down accordingly. For offscreen workload specificly,
set frequency to RP0.

Offscreen task is not restricted by frame rate, it can be
executed as soon as possible. Transcoding and serilized workload
between CPU and GPU both need high GT performance, RP0 is a good
option in this case. RC6 will kick in to compensate power
consumption when GT is not active.

v2: Rebase on recent drm-intel-nightly
v3: Add flip timerout monitor, when no flip is deteced within
100ms, set frequency to RP0.

Signed-off-by: Daisy Sun <daisy.sun@intel.com>
[torourke: rebased on latest and resolved conflict]
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Populate mem_freq in init_gt_powerwave()
Ville Syrjälä [Mon, 18 Aug 2014 11:42:44 +0000 (14:42 +0300)]
drm/i915: Populate mem_freq in init_gt_powerwave()

init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to init_gt_powersave().

v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: s, fb->bits_per_pixel/8, pixel_size, in primary plane code
Ville Syrjälä [Wed, 27 Aug 2014 13:51:22 +0000 (16:51 +0300)]
drm/i915: s, fb->bits_per_pixel/8, pixel_size, in primary plane code

Use the pixel_size we got from drm_format_plane_cpp() instead of
fb->bits_per_pixel/8 when computing the primary plane page/linear
offsets. Avoids a few divs and makes the code more future proof
against funky pixel formats where bits_per_pixel isn't well defined.
This is what we already did in the sprite code.

Note that the relevant sprite patch was

commit ca320ac456099c29290568353d924157e626ede9
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Dec 19 12:14:22 2012 +0000

    drm/i915: Use pixel size for computing linear offsets into a sprite

This change was required on sprites because they support yuv formats
which have fb->bits_per_pixel undefined.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Add Chris' software archeology as a note to the commit
message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't dereference fb when disabling primary plane
Ville Syrjälä [Wed, 27 Aug 2014 14:48:41 +0000 (17:48 +0300)]
drm/i915: Don't dereference fb when disabling primary plane

During driver init we may not have a valid framebuffer for the primary
plane even though the plane is enabled due to failed BIOS fb takeover.
This means we have to avoid dereferencing the fb in
.update_primary_plane() when disabling the plane.

The introduction of the primary plane rotation in

 commit d91a2cb8e5104233c02bbde539bd4ee455ec12ac
 Author: Sonika Jindal <sonika.jindal@intel.com>
 Date:   Fri Aug 22 14:06:04 2014 +0530

    drm/i915: Add 180 degree primary plane rotation support

caused a regression by trying to look up the pixel format before we can
be sure there's a valid fb available. This isn't entirely unsurprising
since the rotation patches originally predate the change to the primary
plane code that calls .update_primary_plane() also when disabling the
plane:

 commit fdd508a6419217cce28213f3c9bd27c02a0d4c71
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Fri Aug 8 21:51:11 2014 +0300

    drm/i915: Call .update_primary_plane in intel_{enable,
    disable}_primary_hw_plane()

v2: Warn but don't blow up when trying to enable a plane w/o an fb (Chris)

Cc: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Export workaround data to debugfs
Arun Siluvery [Tue, 26 Aug 2014 13:44:51 +0000 (14:44 +0100)]
drm/i915/bdw: Export workaround data to debugfs

The workarounds that are applied are exported to a debugfs file;
this is used to verify their state after the test case (reset or
suspend/resume etc). This patch is only required to support i-g-t.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Apply workarounds in render ring init function
Arun Siluvery [Tue, 26 Aug 2014 13:44:50 +0000 (14:44 +0100)]
drm/i915/bdw: Apply workarounds in render ring init function

For BDW workarounds are currently initialized in init_clock_gating() but
they are lost during reset, suspend/resume etc; this patch moves the WAs
that are part of register state context to render ring init fn otherwise
default context ends up with incorrect values as they don't get initialized
until init_clock_gating fn.

v2: Add workarounds to golden render state
This method has its own issues, first of all this is different for
each gen and it is generated using a tool so adding new workaround
and mainitaining them across gens is not a straightforward process.

v3: Use LRIs to emit these workarounds (Ville)
Instead of modifying the golden render state the same LRIs are
emitted from within the driver.

v4: Use abstract name when exporting gen specific routines (Chris)

For: VIZ-4092
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: FBC flush nuke for BDW
Rodrigo Vivi [Mon, 4 Aug 2014 10:51:38 +0000 (03:51 -0700)]
drm/i915: FBC flush nuke for BDW

According to spec FBC on BDW and HSW are identical without any gaps.
So let's copy the nuke and let FBC really start compressing stuff.

Without this patch we can verify with false color that nothing is being
compressed. With the nuke in place and false color it is possible
to see false color debugs.

Unfortunatelly on some rings like BCS on BDW we have to avoid Bits 22:18 on
LRIs due to a high risk of hung. So, when using Blt ring for frontbuffer rend
cache would never been cleaned and FBC would stop compressing buffer.
One alternative is to cache clean on software frontbuffer tracking.

v2: Fix rebase conflict.
v3: Do not clean cache on BCS ring. Instead use sw frontbuffer tracking.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/ddi: use struct for ddi buf translation tables
Jani Nikula [Wed, 27 Aug 2014 13:27:30 +0000 (16:27 +0300)]
drm/i915/ddi: use struct for ddi buf translation tables

Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Resolve silent patch conflict (didn't even fail to build)
with with Sonika's preceding patch to use the
hsw_ddi_translations_fdi table to driver the fdi link training
iteration loop. Also drop the double-write loop Damien spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Rename defines for selection of ddi buffer translation slot
Sonika Jindal [Mon, 11 Aug 2014 03:27:36 +0000 (08:57 +0530)]
drm/i915: Rename defines for selection of ddi buffer translation slot

Renaming the HSW-specific macros for ddi buffer translation slot to denote the
slot and not the vswing/pre-emph values as they are platform-dependent.

This patch is based on top of the patch series for renaming the DP training
vswing/pre-emph defines:
http://lists.freedesktop.org/archives/intel-gfx/2014-August/050407.html

v2: Creating single macro with argument for slot number (Damien)
v3: Adding macro for num of translation entries (Damien)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: debug log whether backlight is being enabled or disabled
Jani Nikula [Wed, 27 Aug 2014 11:08:43 +0000 (14:08 +0300)]
drm/i915/dp: debug log whether backlight is being enabled or disabled

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Let the memory controller do all the swizzling
Damien Lespiau [Wed, 27 Aug 2014 11:24:51 +0000 (13:24 +0200)]
drm/i915/bdw: Let the memory controller do all the swizzling

Previously, it was possible for the GPU memory accesses to be swizzled
to try to optimize the fetches for tiled buffers. This swizzling was on
top of what the memory controller in the uncore already does.

With broadwell, we drop that GPU side swizzling, and the corresponding
initialization in 3 units (GAM, GT, DE). All those bits are reserved, as
specs put it:

  Before Gen8, there was a historical configuration control field to
  swizzle address bit[6] for in X/Y tiling modes. This was set in three
  different places: TILECTL[1:0], ARB_MODE[5:4], and
  DISP_ARB_CTL[14:13]"

  For Gen8 the swizzle fields are all reserved, and the CPU's memory
  controller performs all address swizzling modifications.

This also means that user space doesn't have to manually swizzle when
accessing tiled buffers from the CPU, and so we always return
I915_BIT_6_SWIZZLE_NONE from i915_gem_detect_bit_6_swizzle(), which
short-circuits the initialization of the registers mentionned above in
i915_gem_init_swizzling().

v2: Refine the explanation a bit more (Daniel)
v3: Make it BDW+ specific (Steve)

Cc: Steve Aarnio <steve.j.aarnio@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Keep the actual code to set the tiling bits for now, in case
some bios escaped to the wild that uses this - we'd need it for
fastboot.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add "Intel Corporation" as module author
Damien Lespiau [Wed, 27 Aug 2014 10:30:21 +0000 (11:30 +0100)]
drm/i915: Add "Intel Corporation" as module author

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't use a define when it's clearer to just put the value
Damien Lespiau [Wed, 27 Aug 2014 10:30:20 +0000 (11:30 +0100)]
drm/i915: Don't use a define when it's clearer to just put the value

Instead of going through hoops, just put the driver author directly as
DRM_AUTHOR() argument. This will also make it consistent when we add
Intel to the list.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: improve assert_panel_unlocked
Jani Nikula [Fri, 22 Aug 2014 12:04:13 +0000 (15:04 +0300)]
drm/i915: improve assert_panel_unlocked

Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
non-LVDS. Also don't pretend it works for DDI. There's still work to do
to get this right for eDP on PCH platforms, but this is a start.

v2: WARN_ON(HAS_DDI)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Add BDW support in the i915 debugfs entry
Vedang Patel [Tue, 26 Aug 2014 17:42:51 +0000 (10:42 -0700)]
drm/i915/bdw: Add BDW support in the i915 debugfs entry

The patch introduces fixes for the debugfs attributes emitted by
the i915 driver for GEN8. Currently, it is not emitting the correct
 attributes which include the status of RC6 states.

Change-Id: Ib2068a0cac9a5wq3f228e547fa1a097ad369d242df
Signed-off-by: Vedang Patel <vedang.patel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Differentiate between LLC or snooped for the user
Chris Wilson [Fri, 22 Aug 2014 13:41:39 +0000 (14:41 +0100)]
drm/i915: Differentiate between LLC or snooped for the user

Rather than describing an object as either "snooped or LLC", we can do
better as we should know what machine we are running on!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspend
Paulo Zanoni [Thu, 21 Aug 2014 20:09:38 +0000 (17:09 -0300)]
drm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspend

On BDW we're seeing a problem that after we runtime resume, the
outputs connected to DDI C are not detected: they don't appear in the
SDEISR register and GMBUS transactions don't work. They stop working
at the moment we call intel_opregion_notify_adapter() during runtime
suspend, but they don't go back to work when we call the same function
during runtime resume. They only work after we do a modeset and call
intel_opregion_notify_encoder(), but this point is already too late.

While debugging, I tried to pass PCI_D3hot which is the value that
matches the spec, and it seems to have solved the problem. I couldn't
find any explanation of why this solves the problem, but there's also
no documented explanation - besides our code and git log - of why
Haswell should use PCI_D1, so keep this for now in order to keep BDW
runtime PM working.

Also add a comment to point the fact that there's no spec documenting
all the weirdness involved here.

Cc: kristen.c.accardi@intel.com
Testcase: igt/pm_rpm/drm-resources-equal
Testcase: igt/pm_rpm/i2c
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating
Paulo Zanoni [Thu, 21 Aug 2014 20:09:37 +0000 (17:09 -0300)]
drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating

Because CHV uses cherryview_init_clock_gating instead of
gen8_init_clock_gating.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: call lpt_init_clock_gating on BDW too
Paulo Zanoni [Thu, 21 Aug 2014 20:09:36 +0000 (17:09 -0300)]
drm/i915: call lpt_init_clock_gating on BDW too

Because BDW has WPT, which is equivalent to LPT. This is just like the
CPT/PPT case.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: fix panel unlock register mask
Jani Nikula [Thu, 21 Aug 2014 12:06:25 +0000 (15:06 +0300)]
drm/i915: fix panel unlock register mask

Use the correct mask for the unlock bits. In theory this could have lead
to incorrect asserts but this is unlikely in practise.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Don't execute context reset and switch with Execlists
Thomas Daniel [Wed, 20 Aug 2014 15:29:24 +0000 (16:29 +0100)]
drm/i915/bdw: Don't execute context reset and switch with Execlists

These two functions make no sense in an Logical Ring Context & Execlists
world.

v2: We got rid of lrc_enabled and centralized everything in the sanitized
i915.enable_execlists instead.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
v3: Rebased.  Corrected a typo in comment for i915_switch_context and
added a comment that it should not be called in execlist mode. Added
WARN_ON if i915_switch_context is called in execlist mode. Moved check
for execlist mode out of i915_switch_context and into callers. Added
comment in context_reset explaining why nothing is done in execlist
mode.

Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
[danvet: Simplify the patch subject so I can understand it.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix to Enable GT/PM Interrupts
Deepak S [Fri, 22 Aug 2014 03:02:40 +0000 (08:32 +0530)]
drm/i915: Fix to Enable GT/PM Interrupts

Programing GT IER interrupts was fumbled while enabling Interrupts for
gen8

We forgot to program PM IER interrupt in gen8_gt_irq_postinstall based
on the new  re-worked interrupt routines.

v2: Kill the loop and init GT interrupts individually (Ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Adjust commit message as per discussion with Deepak.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Do not initialize PPGTT in the legacy way for execlists
Thomas Daniel [Wed, 20 Aug 2014 15:24:50 +0000 (16:24 +0100)]
drm/i915/bdw: Do not initialize PPGTT in the legacy way for execlists

A pending commit removes synchronous mode from switch_mm.  This breaks
execlists because switch_mm will always try to write to the legacy ring
buffer.

Return immediately from i915_ppgtt_init_gw in execlists mode.
No longer check for execlists mode in gen8_ppgtt_enable() because this
will no longer be called in execlists mode.

Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Make wait-for-pending-flips more defensive
Chris Wilson [Wed, 20 Aug 2014 12:13:34 +0000 (13:13 +0100)]
drm/i915: Make wait-for-pending-flips more defensive

Be sure to always flush a stuck pageflip even if we couldn't possibly
expect one to be there.

References: https://bugs.freedesktop.org/show_bug.cgi?id=82612
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Handle i915_ppgtt_put correctly
Michel Thierry [Tue, 19 Aug 2014 14:49:41 +0000 (15:49 +0100)]
drm/i915: Handle i915_ppgtt_put correctly

Unfortunately, the gem_obj/vma relationship is not symmetrical; a gem_obj
can look up for the same vma more than once (where the ppgtt refcount is
incremented), but will free the vma only once (i915_gem_free_object).

This difference in refcount get/put means that the ppgtt is not removed
after the context and vma are destroyed, because sometimes the refcount
will never go back to zero.

v2: Just move the ppgtt refcount into vma_create.

OTC-Jira: VIZ-3719
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Flatten intel_edp_panel_vdd_on()
Ville Syrjälä [Mon, 18 Aug 2014 19:16:03 +0000 (22:16 +0300)]
drm/i915: Flatten intel_edp_panel_vdd_on()

Less pointless indentation is always nice. There will be a bit more
code in this function once the power sequencer locking is fixed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Warn about want_panel_vdd in edp_panel_vdd_off_sync()
Ville Syrjälä [Mon, 18 Aug 2014 19:16:02 +0000 (22:16 +0300)]
drm/i915: Warn about want_panel_vdd in edp_panel_vdd_off_sync()

If we force vdd off warn if someone is still using it. With this
change the delayed vdd off work needs to check want_panel_vdd
itself to make sure it doesn't try to turn vdd off when someone
is using it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Replace big nested if block with early return
Ville Syrjälä [Mon, 18 Aug 2014 19:16:01 +0000 (22:16 +0300)]
drm/i915: Replace big nested if block with early return

Looks nicer.

Not functional change.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Add "No functional change" as requested by Jani.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add a note explaining vdd on/off handling in intel_dp_aux_ch()
Ville Syrjälä [Mon, 18 Aug 2014 19:16:00 +0000 (22:16 +0300)]
drm/i915: Add a note explaining vdd on/off handling in intel_dp_aux_ch()

Add a comment to explain why we care about the current want_panel_vdd
state in intel_dp_aux_ch().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Rename edp vdd funcs for consistency
Ville Syrjälä [Tue, 19 Aug 2014 10:24:25 +0000 (13:24 +0300)]
drm/i915: Rename edp vdd funcs for consistency

edp_* are now the lower level functions and intel_edp_* the higher level
ones. One should use them in pairs.

v2: Don't return void (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use intel_edp_panel_vdd_on() in intel_dp_probe_mst()
Ville Syrjälä [Mon, 18 Aug 2014 19:15:58 +0000 (22:15 +0300)]
drm/i915: Use intel_edp_panel_vdd_on() in intel_dp_probe_mst()

We want to use the higher level vdd on func here. Not a big deal
yet (we'd just get the warn when things go awry) but when the
locking gets fixed this becomes more important.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Parametrize PANEL_PORT_SELECT_VLV
Ville Syrjälä [Mon, 18 Aug 2014 19:15:56 +0000 (22:15 +0300)]
drm/i915: Parametrize PANEL_PORT_SELECT_VLV

Passing the port as a parameter to PANEL_PORT_SELECT_VLV results in
neater code. Sadly the PCH port select bits aren't suitable for the
same treatment and the resulting macro would be much uglier, so
leave those defines as is.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Populate lrc with aliasing ppgtt if required
Thomas Daniel [Tue, 19 Aug 2014 09:13:36 +0000 (10:13 +0100)]
drm/i915/bdw: Populate lrc with aliasing ppgtt if required

A previous commit broke aliasing PPGTT for lrc, resulting in a kernel oops
on boot. Add a check so that is full PPGTT is not in use the context is
populated with the aliasing PPGTT.

Issue: VIZ-4278
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: honour forced connector modes
Chris Wilson [Mon, 18 Aug 2014 17:35:29 +0000 (10:35 -0700)]
drm/i915: honour forced connector modes

In the move over to use BIOS connector configs, we lost the ability to
force a specific set of connectors on or off.  Try to remedy that by
dropping back to the old behavior if we detect a hard coded connector
config that tries to enable a connector (disabling is easy!).

Based on earlier patches by Jesse Barnes.

v2: Remove Jesse's patch

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't save/restore RS when not used
Ben Widawsky [Mon, 18 Aug 2014 17:35:28 +0000 (10:35 -0700)]
drm/i915: Don't save/restore RS when not used

v2: fix conflict on rebase.

Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Bring UP Power Wells before disabling RC6.
Deepak S [Mon, 18 Aug 2014 17:35:27 +0000 (10:35 -0700)]
drm/i915: Bring UP Power Wells before disabling RC6.

We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.

v2: updated commit message. (Daniel)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Deepak S <deepak.s@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Print the pipe on which the vblank wait times out
Damien Lespiau [Mon, 18 Aug 2014 12:51:00 +0000 (13:51 +0100)]
drm/i915: Print the pipe on which the vblank wait times out

Improve the debug message that tells us we've been waiting for a vblank
that never arrived. Printing the pipe could lead a "doh!" moment where
we've been waiting for a vblank on a pipe that was off for instance.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
[danvet: Polish commit message a bit.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use dev_priv as first argument of for_each_pipe()
Damien Lespiau [Mon, 18 Aug 2014 12:49:10 +0000 (13:49 +0100)]
drm/i915: Use dev_priv as first argument of for_each_pipe()

Chris has decided that enough is enough. It's time to fixup dev Vs
dev_priv. This is a modest contribution to the crusade.

v2: Still use INTEL_INFO(), for the (mythical!) case we want to hardcode
    the info struct with defines (Chris)
    Rename the macro argument from 'dev' to 'dev_priv' (Jani)

v3: Use names unlikely to be used as macro arguments (Chris)

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: don't check for i830 in vlv specific code
Jani Nikula [Fri, 22 Aug 2014 12:06:35 +0000 (15:06 +0300)]
drm/i915: don't check for i830 in vlv specific code

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Make sure error capture keeps working with Execlists
Oscar Mateo [Thu, 24 Jul 2014 16:04:43 +0000 (17:04 +0100)]
drm/i915/bdw: Make sure error capture keeps working with Execlists

Since the ringbuffer does not belong per engine anymore, we have to
make sure that we are always recording the correct ringbuffer.

TODO: This is only a small fix to keep basic error capture working, but
we need to add more information for it to be useful (e.g. dump the
context being executed).

v2: Reorder how the ringbuffer is chosen to clarify the change and
rename the variable, both changes suggested by Chris Wilson. Also,
add the TODO comment to the code, as suggested by Daniel.

Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Suppress a WARN on reading an object back for a GPU hang
Chris Wilson [Tue, 12 Aug 2014 19:05:50 +0000 (20:05 +0100)]
drm/i915: Suppress a WARN on reading an object back for a GPU hang

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Remove num_pages parameter to i915_error_object_create()
Chris Wilson [Tue, 12 Aug 2014 19:05:49 +0000 (20:05 +0100)]
drm/i915: Remove num_pages parameter to i915_error_object_create()

For cleanliness, i915_error_object_create() was written to handle the
NULL pointer in a central location. The macro that wrapped it and passed
it a num_pages to use, was not safe. As we now never limit the num_pages
to use (we did so at one point to only capture the first page of the
context), we can remove the redundant macro and be NULL safe again.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Do not access stolen memory directly by the CPU, even for error capture
Chris Wilson [Tue, 12 Aug 2014 19:05:48 +0000 (20:05 +0100)]
drm/i915: Do not access stolen memory directly by the CPU, even for error capture

For stolen pages, since it is verboten to access them directly on many
architectures, we have to read them through the GTT aperture. If they
are not accessible through the aperture, then we have to abort.

This was complicated by

commit 8b6124a633d8095b0c8364f585edff9c59568a96
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Jan 30 14:38:16 2014 +0000

    drm/i915: Don't access snooped pages through the GTT (even for error capture)

and the desire to use stolen memory for ringbuffers, contexts and
batches in the future.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: switch off backlight for backlight class 0 brightness
Jani Nikula [Tue, 12 Aug 2014 14:11:42 +0000 (17:11 +0300)]
drm/i915: switch off backlight for backlight class 0 brightness

Make backlight class sysfs brightness 0 value switch off the backlight
for connectors that have the backlight_power callback defined. For eDP,
this has the similar caveats regarding power savings as bl_power as only
the power sequencer backlight control is switched off.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: make backlight bl_power control power sequencer backlight
Jani Nikula [Tue, 12 Aug 2014 14:11:41 +0000 (17:11 +0300)]
drm/i915/dp: make backlight bl_power control power sequencer backlight

This lets the userspace switch off the backlight using the backlight
class sysfs bl_power file. The switch is done using the power sequencer;
the backlight PWM, and everything else, remains enabled. The display
backlight won't draw power, but for maximum power savings the encoder
needs to be switched off.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Tested_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: add some framework for backlight bl_power support
Jani Nikula [Wed, 13 Aug 2014 09:10:12 +0000 (12:10 +0300)]
drm/i915: add some framework for backlight bl_power support

Make backlight class sysfs bl_power a sub-state of backlight enabled, if
a backlight power connector callback is defined. It's up to the
connector callback to handle the sub-state, typically in a way that
respects panel power sequencing.

v2: Post the version that does not oops. *facepalm*.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Tested_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: split up panel power control from backlight pwm control
Jani Nikula [Tue, 12 Aug 2014 14:11:39 +0000 (17:11 +0300)]
drm/i915/dp: split up panel power control from backlight pwm control

Make it possible to change panel power control backlight state without
touching the PWM. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Tested_by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: fix i915_frequency_info on BDW
Paulo Zanoni [Fri, 1 Aug 2014 21:14:48 +0000 (18:14 -0300)]
drm/i915: fix i915_frequency_info on BDW

The GEN6_PM* registers don't exist on BDW anymore, so when we read
this file we trigger unclaimed register errors. The equivalent BDW
register for PMs is GEN8_GT_I*R(2), so use it.

Testcase: igt/pm_rpm/debugfs-read
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>