Flora Cui [Thu, 29 Oct 2015 09:32:11 +0000 (17:32 +0800)]
drm/amdgpu: add ELM/BAF pci ids
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Mon, 7 Dec 2015 10:33:10 +0000 (18:33 +0800)]
drm/amdgpu: update the core VI support for ELM/BAF
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Fri, 26 Feb 2016 02:45:25 +0000 (10:45 +0800)]
drm/amdgpu: ungate SMC clockgating first before suspend
46c34bcb6a15dd85329a39a5e72c62108626acdc put all block’s clockgating
support in SMC. The sequence in suspend routine should be adjusted
accordingly, otherwise it causes asic hang.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Tue, 16 Feb 2016 22:33:14 +0000 (17:33 -0500)]
drm/amd/amdgpu: add power gating init for Baffin
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Thu, 14 Apr 2016 21:26:07 +0000 (17:26 -0400)]
drm/amd/amdgpu: add power gating initialization support for GFX8.0
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Mon, 15 Feb 2016 07:45:59 +0000 (15:45 +0800)]
drm/amd/powerplay: add default clockgating handling
This is to workaround regression introduced in
46c34bcb6a15dd85329a39a5e72c62108626acdc. It should be reverted with a
final fix.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Fri, 12 Feb 2016 15:58:51 +0000 (10:58 -0500)]
drm/amd/amdgpu: add medium grain powergating support for Baffin
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Fri, 11 Mar 2016 19:53:39 +0000 (14:53 -0500)]
drm/amd/powerplay: add GFX per cu powergating for Baffin
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Thu, 11 Feb 2016 20:54:45 +0000 (15:54 -0500)]
drm/amd/powerplay: add GFX per cu powergating support through SMU/powerplay
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Thu, 17 Mar 2016 22:29:08 +0000 (18:29 -0400)]
drm/amd/amdgpu: add query GFX cu info in CGS query system info
Needed for per CU powergating.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Thu, 11 Feb 2016 16:09:09 +0000 (11:09 -0500)]
drm/amd/powerplay: add GFX/SYS clockgating support for ELM/BAF
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Tue, 9 Feb 2016 21:26:00 +0000 (16:26 -0500)]
drm/amd/powerplay: add all blocks clockgating support through SMU/powerplay
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
yanyang1 [Sat, 6 Feb 2016 05:28:47 +0000 (13:28 +0800)]
drm/amd/powerplay: update baffin & ellesmere smc_sk firmware.
sync the code form catalyst CL:#
1230866.
Signed-off-by: yanyang1 <Young.Yang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
yanyang1 [Fri, 5 Feb 2016 09:43:17 +0000 (17:43 +0800)]
drm/amd/powerplay: Add smc_sk firmware to baffin & ellesmere.
update relational h files.
Signed-off-by: yanyang1 <Young.Yang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
yanyang1 [Fri, 5 Feb 2016 09:39:37 +0000 (17:39 +0800)]
drm/amd/amdgpu: Add smc_sk firmware in baffin & ellesmere.
add CGS_UCODE_ID_SMU_SK.
Signed-off-by: yanyang1 <Young.Yang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Fri, 5 Feb 2016 19:47:06 +0000 (14:47 -0500)]
drm/amd/powerplay: add UVD&VCE DPM and powergating support for elm/baf
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Tue, 2 Feb 2016 21:09:24 +0000 (16:09 -0500)]
drm/amd/powerplay: add thermal control for elm/baf
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 11 Mar 2016 19:43:13 +0000 (14:43 -0500)]
drm/amd/powerplay: enable powerplay for baffin.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 11 Mar 2016 19:39:31 +0000 (14:39 -0500)]
drm/amd/powerplay: init hwmgr for ELM/BAF
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 19 Nov 2015 10:23:32 +0000 (18:23 +0800)]
drm/amd/powerplay: enable dpm for baffin.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
rezhu [Tue, 10 Nov 2015 02:26:39 +0000 (10:26 +0800)]
drm/amd/powerplay: add smu support for ellesmere/baffin
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
rezhu [Mon, 16 Nov 2015 02:33:31 +0000 (10:33 +0800)]
drm/amd/powerplay: add header files for ellesmere smu manager.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sonny Jiang [Fri, 11 Mar 2016 19:33:40 +0000 (14:33 -0500)]
drm/amdgpu: add VCE support to ELM/BAF
Ellesmere and Baffin are VCE 3.4
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sonny Jiang [Thu, 5 Nov 2015 20:17:18 +0000 (15:17 -0500)]
drm/amdgpu: add UVD support for ELM/BAF
Ellesmere and Baffin are UVD 6.3
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Thu, 29 Oct 2015 09:26:56 +0000 (17:26 +0800)]
drm/amdgpu: add GFX support for ELM/BAF
V2: use gfx_8_0_*.h instead of gfx_8_1_*.h
v3: agd: integrate support for gfx info table
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Thu, 5 Nov 2015 04:42:59 +0000 (12:42 +0800)]
drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3D
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 14 Mar 2016 20:51:24 +0000 (16:51 -0400)]
drm/amdgpu: add an interface to get gfx constants from atombios
Fetch the values from atom rather than hardcoding them in the
driver.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Thu, 29 Oct 2015 09:26:22 +0000 (17:26 +0800)]
drm/amdgpu: add SDMA support for ELM/BAF
V2: seperate baffin & ellesmere settings instead of using fiji ones.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Thu, 29 Oct 2015 09:25:48 +0000 (17:25 +0800)]
drm/amdgpu: add DCE golden setting for ELM/BAF
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Fri, 11 Mar 2016 19:28:53 +0000 (14:28 -0500)]
drm/amdgpu: add GMC support for ELM/BAF
V2: add golden_settings_baffin_a11 instead of reuse golden_settings_fiji_a10
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 15 Oct 2015 21:14:31 +0000 (17:14 -0400)]
drm/amdgpu/dce11: add dce clock setting for ELM/BAF
Setup the disp clock and dp reference clock. This is
now a separate command table on elm/baf compared to
older asics.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 20:35:33 +0000 (16:35 -0400)]
drm/amdgpu/dce11: update pll programming for ELM/BAF
SetPixelClock table handles pll divider calculation and
spread spectrum setup, so no need to use calculate the
dividers and call the ss enable cmd table.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 19:21:09 +0000 (15:21 -0400)]
drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2)
New PLL scheme on ELM/BAF.
v2: squash in pll fix. Plls are part of the phys.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 19:08:30 +0000 (15:08 -0400)]
drm/amdgpu/atom: add support for new UNIPHYTransmitterContol cmd table
New uniphy transmitter setup table for elm/baf.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 18:49:53 +0000 (14:49 -0400)]
drm/amdgpu/atom: add support for new DIGxEncoderControl cmd table
New digital encoder setup table for elm/baf.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 06:05:31 +0000 (02:05 -0400)]
drm/amdgpu/atom: add support for new SetPixelClock table
New version of the SetPixelClock table for elm/baf. The
new table calculates the pll dividers and handles spread
spectrum calculations and setup.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 05:24:49 +0000 (01:24 -0400)]
drm/amdgpu/atom: add SetDCEClock helper
New cmd table for ELM/BAF for setting the dispclock or
dprefclock.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Thu, 15 Oct 2015 04:43:41 +0000 (00:43 -0400)]
drm/amdgpu: update atombios.h (v2)
update to internal version 893
v2: Pull in gfx_info changes from 898
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Mon, 18 Apr 2016 22:25:34 +0000 (18:25 -0400)]
drm/amdgpu: bump the afmt limit for CZ, ST, Polaris
Fixes array overflow on these chips.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Mon, 18 Apr 2016 22:09:57 +0000 (18:09 -0400)]
drm/amdgpu: use defines for CRTCs and AMFT blocks
Prerequiste for the next patch which ups the limits.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Wed, 14 Oct 2015 21:17:15 +0000 (17:17 -0400)]
drm/amdgpu: add ELM/BAF DCE11 configs (v2)
Add support for the display configuration on elm/baf.
v2: add missing Stoney case
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Wed, 14 Oct 2015 21:14:16 +0000 (17:14 -0400)]
drm/amdgpu: add ELM/BAF asic types
New asic types for ellesmere and baffin.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Alex Deucher [Fri, 11 Mar 2016 19:46:46 +0000 (14:46 -0500)]
drm/amd: add DCE 11.2 register headers
Add register headers for DCE (Display and Composition Engine)
11.2.
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bas Nieuwenhuizen [Fri, 15 Apr 2016 00:47:49 +0000 (02:47 +0200)]
drm/radeon: Allow setting shader registers using DMA/COPY packet3 on SI.
Mesa uses a COPY_DATA packet to copy the grid size for indirect dispatches
into COMPUTE_USER_DATA_*.
Setting those registers with a SET_SH_REG packet is allowed, not allowing
them with other packets seems like an oversight.
v2: Clarify commit message.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 15 Apr 2016 15:19:17 +0000 (17:19 +0200)]
drm/amdgpu: remove sorting of CS BOs
Not needed any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 15 Apr 2016 15:19:16 +0000 (17:19 +0200)]
drm/amdgpu: group BOs by log2 of the size on the LRU v2
This allows us to have small BOs on the LRU before big ones.
v2: fix of by one and list corruption bug
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Wed, 13 Apr 2016 23:49:16 +0000 (09:49 +1000)]
drm/amdgpu: drop apply quirks for now.
This isn't being used so drop it.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 14 Apr 2016 07:53:55 +0000 (15:53 +0800)]
drm/amdgpu: fix error checking when reuse vmid on same ring
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 14 Apr 2016 05:42:32 +0000 (13:42 +0800)]
drm/amdgpu: only update last_flush when vmid doesn't have other new owner
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 14 Apr 2016 02:27:28 +0000 (10:27 +0800)]
drm/amdgpu: double fence slot
we introduced vmid fence, so one hw submission could produce two fences.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:40:49 +0000 (00:40 -0400)]
drm/amdgpu: enable sdma clockgating on ST
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:39:54 +0000 (00:39 -0400)]
drm/amdgpu: enable sdma clockgating on CZ
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:19:39 +0000 (00:19 -0400)]
drm/amdgpu/sdma: rename fiji cg functions
They care common for all sdma 3.0 parts
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 13 Apr 2016 16:41:50 +0000 (12:41 -0400)]
drm/amdgpu: enable gmc clockgating for ST
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:26:46 +0000 (00:26 -0400)]
drm/amdgpu: enable gmc clockgating for CZ
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 05:37:44 +0000 (01:37 -0400)]
drm/amdgpu/vi: rename fiji cg functions
They can be used for other VI parts.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 03:17:15 +0000 (23:17 -0400)]
drm/amdgpu: enable gfx clockgating for ST (v2)
v2: just enable MGCG for now since CGCG causes hangs
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 03:01:48 +0000 (23:01 -0400)]
drm/amdgpu: enable gfx clockgating for CZ
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 02:57:39 +0000 (22:57 -0400)]
drm/amdgpu/gfx: rework fiji cg functions so they can be shared
They can be shared with other asics with minor modifications.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 19:45:13 +0000 (15:45 -0400)]
drm/amdgpu: add a new set of rlc function pointers
Different asics tend to have different ways to interact
with the RLC. This just covers enter/exit of safe mode
for updating CG and PG state, but could be extended to
cover other RLC operations in the future if necessary.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 03:16:00 +0000 (23:16 -0400)]
drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 05:12:20 +0000 (01:12 -0400)]
drm/amdgpu/gfx8: rename send_serdes_cmd
So it can be shared with CZ/ST.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 05:01:18 +0000 (01:01 -0400)]
drm/amdgpu/gmc: add proper CG flags for fiji
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:52:58 +0000 (00:52 -0400)]
drm/amdgpu/common: add proper CG flags for fiji
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:42:51 +0000 (00:42 -0400)]
drm/amdgpu/sdma: add proper CG flags for fiji
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 7 Apr 2016 22:38:00 +0000 (18:38 -0400)]
drm/amdgpu/gfx: add proper CG flags for fiji
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 04:52:24 +0000 (00:52 -0400)]
drm/amdgpu: add new CG flag for ROM clockgating
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Apr 2016 09:12:07 +0000 (11:12 +0200)]
drm/ttm: implement LRU add callbacks v2
This allows fine grained control for the driver where to add a BO into the LRU.
v2: fix typo in comment
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Apr 2016 09:12:06 +0000 (11:12 +0200)]
drm/ttm: add optional LRU removal callback v2
Useful for driver specific LRU handling.
v2: fix typo in comment
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Apr 2016 09:12:05 +0000 (11:12 +0200)]
drm/ttm: remove unused validation sequence
Not used any more.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Apr 2016 09:12:04 +0000 (11:12 +0200)]
drm/ttm: remove lazy parameter from ttm_bo_wait
Not used any more.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Apr 2016 09:12:03 +0000 (11:12 +0200)]
drm/ttm: remove use_ticket parameter from ttm_bo_reserve
Not used any more.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Apr 2016 09:12:02 +0000 (11:12 +0200)]
drm/ttm: don't wait for BO on initial allocation
When we use an extern reservation object that otherwise waits for every
fence registered with it.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 13 Apr 2016 09:36:00 +0000 (11:36 +0200)]
drm/amdgpu: fix the coding style in amdgpu_ring.c
No functional change.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 13 Apr 2016 09:34:44 +0000 (11:34 +0200)]
drm/amdgpu: use the ring name for debugfs (v2)
Instead of hard coding just another name in the ring code.
v2: squash in Tom's rebase fix
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 13 Apr 2016 08:30:13 +0000 (10:30 +0200)]
drm/amdgpu: reduce the ring size for SDMA
Those are way too large.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 13 Apr 2016 08:27:35 +0000 (10:27 +0200)]
drm/amdgpu: reduce the ring size for GFX
Those are way too large.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 12 Apr 2016 14:26:34 +0000 (16:26 +0200)]
drm/amdgpu: use max_dw in ring_init
Instead of specifying the total ring size calculate that from the maximum
number of dw a submission can have and the number of concurrent submissions.
This fixes UVD with 8 concurrent submissions or more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Mon, 11 Apr 2016 18:28:55 +0000 (14:28 -0400)]
drm/amd/powerplay: fix fan speed percent setting error on Fiji
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Mon, 11 Apr 2016 18:27:51 +0000 (14:27 -0400)]
drm/amd/powerplay: fix fan speed percent setting error on Tonga
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Fri, 8 Apr 2016 01:42:17 +0000 (21:42 -0400)]
drm/ttm: Fix TTM BO accounting
TTM BO accounting is out of sync with how memory is really allocated
in ttm[_dma]_tt_alloc_page_directory. This resulted in excessive
estimated overhead with many small allocations.
ttm_dma_tt_alloc_page_directory makes a single allocation for three
arrays: pages, DMA and CPU addresses. It uses drm_calloc_large, which
uses kmalloc internally for allocations smaller than PAGE_SIZE.
ttm_round_pot should be a good approximation of its memory usage both
above and below PAGE_SIZE.
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Tue, 12 Apr 2016 03:25:48 +0000 (13:25 +1000)]
drm/amd: make a type-safe cgs_device struct. (v2)
This is just a type-safety things to avoid everyone taking void *,
it doesn't change anything.
v2: agd5f: split out the dal changes into a separate patch.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arindam Nath [Tue, 12 Apr 2016 11:46:15 +0000 (13:46 +0200)]
drm/amdgpu: handle more than 10 UVD sessions (v2)
Change History
--------------
v2:
- Make firmware version check correctly. Firmware
versions >= 1.80 should all support 40 UVD
instances.
- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
variable.
v1:
- The firmware can handle upto 40 UVD sessions.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:04 +0000 (16:30 +0200)]
drm/amd: make some function-local tables static const
These tables were initialized on stack on each call, avoid that
and save a little bit of text size.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:03 +0000 (16:30 +0200)]
drm/amd/powerplay: mark phm_master_table_* structs as const
Also adjust phm_construct_table to take a const pointer
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:02 +0000 (16:30 +0200)]
drm/amd/powerplay: Mark pem_event_action chains as const
As these arrays were of pointer to pointer type, they were
pointer to pointer to const. Make them pointer to const
pointer to const.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Mon, 2 May 2016 16:46:15 +0000 (12:46 -0400)]
drm/amdgpu: Mark all instances of struct drm_info_list as const
All these are compile time constand and the
drm_debugfs_create/remove_files functions take a const
pointer argument.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:30:00 +0000 (16:30 +0200)]
drm/amd/scheduler: Mark amdgpu_sched_ops const
This marks the struct amdgpu_sched_ops const and
adjusts amd_sched_init to take a const pointer
for the ops param. The ops member of
struct amd_gpu_scheduler is also changed to const.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nils Wallménius [Sun, 10 Apr 2016 14:29:59 +0000 (16:29 +0200)]
drm/amd: Mark some tables as const
This patch marks some compile-time constant tables 'const'.
The tables marked in this patch are the low hanging fruit
where little other changes were necesary to avoid casting
away constness etc. Also mark some tables that are private
to a file as static.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 8 Apr 2016 20:42:38 +0000 (16:42 -0400)]
drm/amd/powerplay: fix stutter setup in mclk level init
Stale ifdef.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Wed, 6 Apr 2016 20:50:25 +0000 (06:50 +1000)]
drm/radeon: add support for SET_APPEND_CNT packet3 (v2)
This adds support to the command parser for the set append counter
packet3, this is required to support atomic counters on
evergreen/cayman GPUs.
v2: fixup some of the hardcoded numbers with real register names
(Christian)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arindam Nath [Wed, 6 Apr 2016 19:33:52 +0000 (15:33 -0400)]
drm/radeon: handle more than 10 UVD sessions
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arindam Nath [Wed, 6 Apr 2016 19:33:51 +0000 (15:33 -0400)]
drm/radeon: add support for loading new UVD fw
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 9 Mar 2016 21:11:53 +0000 (22:11 +0100)]
drm/amdgpu: reuse VMIDs already assigned to a process
If we don't need to flush we can easily use another VMID
already assigned to the process.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 1 Mar 2016 15:46:18 +0000 (16:46 +0100)]
drm/amdgpu: add a fence after the VM flush
This way we can track when the flush is done.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 15 Feb 2016 11:33:02 +0000 (12:33 +0100)]
drm/amdgpu: use a sync object for VMID fences v2
v2: rebase & cleanup
This way we can store more than one fence as user for each VMID.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 8 Mar 2016 14:40:11 +0000 (15:40 +0100)]
drm/amdgpu: merge VM manager and VM context ID structure
No need to have two of them any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 30 Mar 2016 21:34:27 +0000 (17:34 -0400)]
drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update
Also add some pflip debug prints.
This change allows us to wait on pflip status until the new surface address
is actually submitted to the register.
This reverts
ed3020e923240829dcdfd3343f6e91dc02c63775
drm/amdgpu: Move MMIO flip out of spinlocked region
The original change assumed DAL will aquire locks inside DAL
implemetion of page_flip callback which eventaully didn't happen.
This moves the flip before status update which makes sense for the
non-DAL code pathes as well.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 1 Apr 2016 09:51:34 +0000 (18:51 +0900)]
drm/radeon: Support DRM_MODE_PAGE_FLIP_ASYNC
When this flag is set, we program the hardware to execute the flip
during horizontal blank (i.e. for the next scanline) instead of during
vertical blank (i.e. for the next frame).
Currently this is only supported on ASICs which have a page flip
completion interrupt (>= R600), and only if the use_pflipirq parameter
has value 2 (the default).
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Wed, 30 Mar 2016 20:30:12 +0000 (16:30 -0400)]
drm/amd/powerplay: add deep sleep divider id into DPM table on Tonga
Add a proper implementation for setting the deep sleep divider.
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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