Leo Liu [Thu, 11 May 2017 20:27:33 +0000 (16:27 -0400)]
drm/amdgpu: move amdgpu_vcn structure to vcn header
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 28 Dec 2016 18:04:16 +0000 (13:04 -0500)]
drm/amdgpu: add vcn ip block and type
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 28 Dec 2016 18:22:18 +0000 (13:22 -0500)]
drm/amdgpu: add vcn irq functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 5 May 2017 15:40:59 +0000 (11:40 -0400)]
drm/amdgpu: add vcn decode ring type and functions
Add the ring function callbacks for the decode ring.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 28 Dec 2016 17:16:48 +0000 (12:16 -0500)]
drm/amdgpu: add vcn decode ring support
Add the decode ring init.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 28 Dec 2016 16:57:38 +0000 (11:57 -0500)]
drm/amdgpu: add vcn ip block functions (v2)
Fill in the core VCN 1.0 setup functionality.
v2: squash in fixup (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 21 Dec 2016 18:56:44 +0000 (13:56 -0500)]
drm/amdgpu: add encode tests for vcn
Add encode ring and ib tests.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 21 Dec 2016 18:21:52 +0000 (13:21 -0500)]
drm/amdgpu: add initial vcn support and decode tests
VCN is the new media block on Raven. Add core support
and the ring and ib tests for decode.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 11 May 2017 20:26:16 +0000 (16:26 -0400)]
drm/amdgpu/soc15: add psp ip block
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 16 Dec 2016 02:08:48 +0000 (10:08 +0800)]
drm/amdgpu: register the psp v10 function pointers at psp sw_init
Add the psp 10.0 callbacks for PSP.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 16 Dec 2016 02:01:55 +0000 (10:01 +0800)]
drm/amdgpu: add psp v10 ip block
Add the ip block version structure for psp 10.0.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 4 May 2017 19:28:30 +0000 (15:28 -0400)]
drm/amdgpu: add psp v10 function callback for raven
PSP is the security processor. These are the support
functions.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 27 Feb 2017 06:01:55 +0000 (14:01 +0800)]
drm/amdgpu: add nbio MGCG for raven
Add medium grained nbio clockgating implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 4 May 2017 19:06:25 +0000 (15:06 -0400)]
drm/amdgpu: apply nbio7 for Raven (v3)
nbio handles misc bus io operations. Handle
differences between different nbio bus versions.
v2: switch checks from RAVEN to APU (Alex)
squash in raven rev id fetch
squash in fix uninitalized hdp flush reg index for raven
v3: add some missed RAVEN to APU checks (Alex)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 4 May 2017 18:59:54 +0000 (14:59 -0400)]
drm/amdgpu: add nbio7 support
NBIO handles misc bus io functions on the chip. This
helper lib has the apppropriate functions for NBIO 7.0.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 5 May 2017 18:29:42 +0000 (14:29 -0400)]
drm/amdgpu: enable sdma power gating for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 28 Feb 2017 08:13:32 +0000 (16:13 +0800)]
drm/amdgpu/sdma4: add dynamic power gating for raven
Add the functions to enable dynamic powergating.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 28 Feb 2017 08:07:48 +0000 (16:07 +0800)]
drm/amdgpu: init sdma power gating for raven
Initialize sdma for powergating.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 5 May 2017 18:28:27 +0000 (14:28 -0400)]
drm/amdgpu: enable sdma v4 MGCG and LS for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 17 Jan 2017 07:09:37 +0000 (15:09 +0800)]
drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 05:56:16 +0000 (13:56 +0800)]
drm/amdgpu: add Raven sdma golden setting and chip id case
Add golden settings for SDMA.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 5 May 2017 18:27:23 +0000 (14:27 -0400)]
drm/amdgpu: enable MC MGCG and LS for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 8 Feb 2017 09:07:59 +0000 (17:07 +0800)]
drm/amdgpu: add raven clock gating and light sleep for mmhub
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 16 Jan 2017 02:45:50 +0000 (10:45 +0800)]
drm/amdgpu/gmc9: change fb offset sequence so that used wider
Initialize the values earlier.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 15 Dec 2016 03:15:27 +0000 (11:15 +0800)]
drm/amdgpu/gmc9: set mc vm fb offset for raven
APU fb offset is set by sbios, which is different with DGPU.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 03:28:45 +0000 (11:28 +0800)]
drm/amdgpu: add raven case for gmc9 golden setting
Golden settings for GMC9.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 13 Feb 2017 10:45:28 +0000 (18:45 +0800)]
drm/amdgpu/gfx9: allow updating gfx mgpg state
Wire up the functions to control medium grained
powergating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 13 Feb 2017 10:40:45 +0000 (18:40 +0800)]
drm/amdgpu/gfx9: allow updating gfx cgpg state
Wire up the enable functions to enable coarse
grained powegating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 13 Feb 2017 10:00:43 +0000 (18:00 +0800)]
drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
More stuff for gfx pg.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 Feb 2017 07:47:28 +0000 (15:47 +0800)]
drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
Used to enable/disable cp powergating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 Feb 2017 07:36:34 +0000 (15:36 +0800)]
drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
Required for proper powergating operation.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 Feb 2017 07:13:17 +0000 (15:13 +0800)]
drm/amdgpu: init gfx power gating on raven
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 10 Feb 2017 06:37:03 +0000 (14:37 +0800)]
drm/amdgpu/gfx9: rlc save&restore list programming
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 13 Feb 2017 05:55:23 +0000 (13:55 +0800)]
drm/amdgpu/gfx9: add rlc bo init/fini
setup the save and restore buffers used for gfx
powergating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 9 Feb 2017 09:11:54 +0000 (17:11 +0800)]
drm/amdgpu: correct gfx9 csb size
programming pa_sc_raster_config/config1 reg is removed from gfx9 csb
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 9 Feb 2017 06:48:08 +0000 (14:48 +0800)]
drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
Required for proper handshaking between the GFX and RLC.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 8 Feb 2017 10:17:44 +0000 (18:17 +0800)]
drm/amdgpu/gfx9: extend rlc fw setup
Required for gfx powergating.
Change-Id: I5a2f8f41253686d8bb776a92aa68bf90877ebaa8
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 10 Jan 2017 03:04:25 +0000 (11:04 +0800)]
drm/amdgpu: add gfx clock gating for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 03:06:11 +0000 (11:06 +0800)]
drm/amdgpu/gfx9: add raven gfx config
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 02:49:37 +0000 (10:49 +0800)]
drm/amdgpu/gfx9: add chip name for raven when initializing microcode
Fetch the correct ucode for raven.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 02:41:58 +0000 (10:41 +0800)]
drm/amdgpu: add gc9.1 golden setting (v2)
Add the GFX9 golden settings.
v2: squash in updates
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Tue, 13 Dec 2016 07:58:33 +0000 (15:58 +0800)]
drm/amdgpu: add module firmware for raven
Fetch correct firmware for raven for gfx and sdma.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 4 May 2017 18:54:46 +0000 (14:54 -0400)]
drm/amdgpu: add Raven chip id case for ucode
Set the appropriate ucode loading mechanism. Set to
direct for now.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 18 Jan 2017 10:14:08 +0000 (18:14 +0800)]
drm/amdgpu: enable soc15 clock gating flags for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 18 Jan 2017 10:12:59 +0000 (18:12 +0800)]
drm/amdgpu/soc15: add clock gating functions for raven
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 27 Dec 2016 13:02:48 +0000 (21:02 +0800)]
drm/amd/amdgpu: fill in raven case in soc15 early init
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 02:16:00 +0000 (10:16 +0800)]
drm/amdgpu/soc15: add Raven golden setting
Add the common golden settings for Raven.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 8 Dec 2016 02:09:13 +0000 (10:09 +0800)]
drm/amdgpu: add Raven ip blocks (v2)
Add the IP blocks for RAVEN.
v2: drop DC for upstream (Alex)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Wed, 7 Dec 2016 09:31:19 +0000 (17:31 +0800)]
drm/amdgpu: add RAVEN family id definition
RAVEN is a new APU.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:09:18 +0000 (13:09 -0400)]
drm/amdgpu: add register headers for VCN 1.0
Add registers for Video Controller Next 1.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:08:39 +0000 (13:08 -0400)]
drm/amdgpu: add register headers for THM 10.0
Add registers for THerMal control 10.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:07:58 +0000 (13:07 -0400)]
drm/amdgpu: add register headers for SDMA 4.1
Add registers for SDMA 4.1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:06:58 +0000 (13:06 -0400)]
drm/amdgpu: add register headers for NBIO 7.0
Add registers for NBIO 7.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:05:53 +0000 (13:05 -0400)]
drm/amdgpu: add register headers for MP 10.0
Add registers for MP 10.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:04:55 +0000 (13:04 -0400)]
drm/amdgpu: add register headers for MMHUB 9.1
Add registers for the MultiMedia Hub 9.1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:02:36 +0000 (13:02 -0400)]
drm/amdgpu: add register headers for GC 9.1
Registers for Graphics Controller 9.1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 17:01:35 +0000 (13:01 -0400)]
drm/amdgpu: add register headers for DCN 1.0
Registers for Display Controller Next 1.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 11 May 2017 05:59:15 +0000 (13:59 +0800)]
drm/amdgpu:use job's list instead of check fence
because if the fence is really signaled, it could already
released so the fence pointer is a wild pointer, but if
we use job->base.node we are safe because job will not
be released untill amdgpu_job_timedout finished.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 11 May 2017 05:36:44 +0000 (13:36 +0800)]
drm/amdgpu/SRIOV:implement guilty job TDR for(V2)
1,TDR will kickout guilty job if it hang exceed the threshold
of the given one from kernel paramter "job_hang_limit", that
way a bad command stream will not infinitly cause GPU hang.
by default this threshold is 1 so a job will be kicked out
after it hang.
2,if a job timeout TDR routine will not reset all sched/ring,
instead if will only reset on the givn one which is indicated
by @job of amdgpu_sriov_gpu_reset, that way we don't need to
reset and recover each sched/ring if we already know which job
cause GPU hang.
3,unblock sriov_gpu_reset for AI family.
V2:
1:put kickout guilty job after sched parked.
2:since parking scheduler prior to kickout already occupies a
while, we can do last check on the in question job before
doing hw_reset.
TODO:
1:when a job is considered as guilty, we should mark some flag
in its fence status flag, and let UMD side aware that this
fence signaling is not due to job complete but job hang.
2:if gpu reset cause all video memory lost, we need introduce
a new policy to implement TDR, like drop all jobs not yet
signaled, and all IOCTL on this device will return ERROR
DEVICE_LOST.
this will be implemented later.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 11 May 2017 05:36:33 +0000 (13:36 +0800)]
drm/amdgpu:don't init entity for KIQ
We don't need a scheduler for KIQ.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 26 Apr 2017 06:51:54 +0000 (14:51 +0800)]
drm/amdgpu:only call flr_work under infinite timeout
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 26 Apr 2017 06:51:54 +0000 (14:51 +0800)]
drm/amdgpu:use job* to replace voluntary
that way we can know which job cause hang and
can do per sched reset/recovery instead of all
sched.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 5 May 2017 07:09:42 +0000 (15:09 +0800)]
drm/amdgpu:don't invoke srio-gpu-reset in gpu-reset (v2)
because we don't want to do sriov-gpu-reset under certain
cases, so just split those two funtion and don't invoke
sr-iov one from bare-metal one.
V2:
remove debugfs_gpu_reset routine on SRIOV case.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Wed, 10 May 2017 05:02:39 +0000 (13:02 +0800)]
drm/amdgpu: id reset count only is updated when used end v2
before that, we have function to check if reset happens by using reset count.
v2: always update reset count after vm flush
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 11 May 2017 18:52:48 +0000 (14:52 -0400)]
drm/amdgpu: make pipeline sync be in same place v2
v2: directly return for 'if' case.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Tue, 9 May 2017 07:50:22 +0000 (15:50 +0800)]
drm/amdgpu: add sched sync for amdgpu job v2
this is an improvement for previous patch, the sched_sync is to store fence
that could be skipped as scheduled, when job is executed, we didn't need
pipeline_sync if all fences in sched_sync are signalled, otherwise insert
pipeline_sync still.
v2: handle error when adding fence to sync failed.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> (v1)
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 8 May 2017 13:14:54 +0000 (15:14 +0200)]
drm/amdgpu: remove unsed amdgpu_gem_handle_lockup (v2)
This kind of reset handling was removed a long time ago.
v2: fix warning (Alex)
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Fri, 5 May 2017 02:50:09 +0000 (10:50 +0800)]
drm/amdgpu: print when gpu reset successed
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Roger.He <Hongbo.He@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Fri, 5 May 2017 02:33:33 +0000 (10:33 +0800)]
drm/amdgpu: fix ring0 failed on pro card
the root cause is vram content is lost completely after pci reset.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Roger.He <Hongbo.He@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger.He [Fri, 5 May 2017 05:27:10 +0000 (13:27 +0800)]
drm/amdgpu: extend lock range for race condition when gpu reset
to cover below case:
1. A task gart bind/unbind but not add to adev->gtt_list yet
2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Tue, 9 May 2017 01:36:03 +0000 (21:36 -0400)]
drm/amdgpu: Fix comments in source code
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 8 May 2017 17:41:11 +0000 (13:41 -0400)]
drm/amdgpu: fix errors in comments.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 4 May 2017 14:32:33 +0000 (10:32 -0400)]
drm/amdgpu/gfx9: move define to header file
rather than defining it locally.
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Pajkovsky [Thu, 4 May 2017 16:39:50 +0000 (12:39 -0400)]
drm/amd/amdgpu: get rid of else branch
else branch is pointless if it's right at the end of function and use
unlikely() on err path.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Nikola Pajkovsky <npajkovsky@suse.cz>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 3 May 2017 06:55:07 +0000 (14:55 +0800)]
drm/amdgpu:cleanup flag not used
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 10:09:22 +0000 (18:09 +0800)]
drm/amdgpu:use FRAME_CNTL for new GFX ucode (v2)
AI affected:
CP/HW team requires KMD insert FRAME_CONTROL(end) after
the last IB and before the fence of this DMAframe.
this is to make sure the cache are flushed, and it's a must
change no matter MCBP/SR-IOV or bare-metal case because new
CP hw won't do the cache flush for each IB anymore, it just
leaves it to KMD now.
with this patch, certain MCBP hang issue when rendering
vulkan/chained-ib are resolved.
v2: drop gfx8 changes. gfx8 is not affected (Alex)
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 09:23:44 +0000 (17:23 +0800)]
drm/amdgpu:new PM4 entry for VI/AI
TMZ package will be used for VULKAN/CHAINED-IB MCBP
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 09:05:02 +0000 (17:05 +0800)]
drm/amdgpu:change SR-IOV DMAframe scheme
According to CP/hw team requirment, to support PAL/CHAINED-IB
MCBP, kernel driver must guarantee DE_META must be inserted
right prior to the work_load DE IB (with PREEMPT flag), there
cannot be any non-work_load DE IB between-in DE_META and
work_load DE IB.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 10:05:06 +0000 (18:05 +0800)]
drm/amdgpu:unify gfx8/9 ce/de meta_data
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 09:00:13 +0000 (17:00 +0800)]
drm/amdgpu:cleanup indent/format for gfx_v9_0.c
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Tue, 2 May 2017 11:49:32 +0000 (19:49 +0800)]
drm/amdgpu: clean doorbell after sending init table to mmsch
According to HW design, need to clean doorbell after setup MMSCH
table.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Thu, 4 May 2017 06:02:31 +0000 (14:02 +0800)]
drm/amdgpu/virt: change AI ack-irq message to debug level
Change message to debug level as VI does.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Thu, 4 May 2017 03:05:13 +0000 (11:05 +0800)]
drm/amdgpu/psp: Do not load asd for SRIOV
If psp version doesn't match asd version, asd loading will be
failed. Add workaround to bypass it for sriov.
Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Trigger Huang [Wed, 26 Apr 2017 06:29:47 +0000 (02:29 -0400)]
drm/amdgpu: Bypass GMC/UVD/VCE hw_fini in SR-IOV
On vega10, some hw finish operations should not be applied in SR-IOV
case. This works as workaround to fix multi-VFs reboot/shutdown
issues.
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 26 Apr 2017 04:00:49 +0000 (12:00 +0800)]
drm/amdgpu:re-write sriov_reinit_early/late (v2)
1,this way we make those routines compatible with the sequence
requirment for both Tonga and Vega10
2,ignore PSP hw init when doing TDR, because for SR-IOV device
the ucode won't get lost after VF FLR, so no need to invoke PSP
doing the ucode reloading again.
v2: squash in ARRAY_SIZE fix
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 21 Apr 2017 11:35:11 +0000 (19:35 +0800)]
drm/amdgpu:need som change on vega10 mailbox
if sriov gpu reset is invoked by job timeout, it is run
in a global work-queue which is very slow and better not call
msleep ortherwise it takes long time to get back CPU.
so make below changes:
1: Change msleep 1 to mdelay 5
2: Ignore the ack fail from pf after time out,
because VF FLR will clear ack, sometime VF FLR is done
prior to the beginning of poll_ack so we can ignore this ack
TODO:
Put job_timedout (and the following gpu reset) in a driver thread,
instead of the global work_struct.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Sun, 23 Apr 2017 03:25:59 +0000 (11:25 +0800)]
drm/amdgpu:fix cannot receive rcv/ack irq bug
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 5 May 2017 21:30:50 +0000 (17:30 -0400)]
drm/amdgpu:kiq reg access need timeout(v2)
this is to prevent fence forever waiting if FLR occured
during register accessing.
v2:
use define instead of hardcode for the timeout msec
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 20:21:52 +0000 (16:21 -0400)]
drm/amdgpu/gfx9: wait for completion in KIQ init
We need to make sure the various init sequences submitted
to KIQ complete before testing the rings.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 20:14:09 +0000 (16:14 -0400)]
drm/amdgpu/gfx9: use new KIQ packet defines
Rather than magic numbers.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 19:54:55 +0000 (15:54 -0400)]
drm/amdgpu: add KIQ packet defines to soc15d.h
Will be used in subsequent commits rather rather than
magic numbers.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 20:32:12 +0000 (16:32 -0400)]
drm/amdgpu/gfx9: clear the compute ring on reset
To be consistent with gfx8.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 19:29:14 +0000 (15:29 -0400)]
drm/amdgpu/gfx9: create mqd backups
And properly synchronize them with the master during
queue init.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shaoyun Liu [Fri, 28 Apr 2017 21:18:26 +0000 (17:18 -0400)]
drm/amdgpu: Move kiq ring lock out of virt structure
The usage of kiq should not depend on the virtualization.
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by:Andres Rodriquez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 24 Apr 2017 03:47:05 +0000 (11:47 +0800)]
drm/amdgpu: bump module verion for reserved vmid
Interface to reserve a vmid for a specific process to
add in shader debugging that requries a fixed vmid.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Fri, 21 Apr 2017 03:13:56 +0000 (11:13 +0800)]
drm/amdgpu: implement grab reserved vmid V4
Implement the vmid reservation.
v2: move sync waiting only when flush needs
v3: fix racy
v4: peek fence instead of get fence, and fix potential context starved.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Fri, 21 Apr 2017 07:51:04 +0000 (15:51 +0800)]
drm/amdgpu: add limitation for dedicated vm number v4
Limit reserved vmids to 1 to avoid taking too many
out of commission and starving the system.
v2: move #define to amdgpu_vm.h
v3: move reserved vmid counter to id_manager,
and increase counter before allocating vmid
v4: rename to reserved_vmid_num
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 20 Apr 2017 08:18:48 +0000 (16:18 +0800)]
drm/amdgpu: reserve/unreserve vmid by vm ioctl v4
add reserve/unreserve vmid funtions. Used to reserve
vmids for certain shader debugging functionality that
required a fixed vmid for the life of the debug.
v3:
only reserve vmid from gfxhub
v4:
fix racy condition
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 20 Apr 2017 08:17:34 +0000 (16:17 +0800)]
drm/amdgpu: add reserved vmid field in vm struct v2
v2: rename dedicated_vmid to reserved_vmid
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 24 Apr 2017 03:09:04 +0000 (11:09 +0800)]
drm/amdgpu: add vm ioctl
It will be used for reserving vmid for shader debugging
that requires a fixed vmid.
v2: fix warning (Alex)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / log