GitHub/exynos8895/android_kernel_samsung_universal8895.git
11 years agodrm/i915: Add a control file for pipe CRCs
Daniel Vetter [Wed, 16 Oct 2013 11:30:34 +0000 (13:30 +0200)]
drm/i915: Add a control file for pipe CRCs

Note the "return -ENODEV;" in pipe_crc_set_source(). The ctl file is
disabled until the end of the series to be able to do incremental
improvements.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Expose latest 200 CRC value for pipe through debugfs
Shuang He [Tue, 15 Oct 2013 17:55:27 +0000 (18:55 +0100)]
drm/i915: Expose latest 200 CRC value for pipe through debugfs

There are several points in the display pipeline where CRCs can be
computed on the bits flowing there. For instance, it's usually possible
to compute the CRCs of the primary plane, the sprite plane or the CRCs
of the bits after the panel fitter (collectively called pipe CRCs).

v2: Quite a bit of rework here and there (Damien)

Signed-off-by: Shuang He <shuang.he@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Fix intermediate compile file reported by Wu Fengguang's
kernel builder.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Replace has_bsd/blt/vebox with a mask
Ben Widawsky [Tue, 15 Oct 2013 17:02:57 +0000 (10:02 -0700)]
drm/i915: Replace has_bsd/blt/vebox with a mask

I've sent this patch several times for various reasons. It essentially
cleans up a lot of code where we need to do something per ring, and want
to query whether or not the ring exists on that hardware.

It has various uses coming up, but for now it shouldn't be too
offensive.

v2: Big conflict resolution on Damien's DEV_INFO_FOR_EACH stuff

v3: Resolved vebox addition

v4: Rebased after months of disuse. Also made failed ringbuffer init
cleaner.

v5: Remove the init cleaner from v4. There is a better way to do it.
(Chris)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: cleanup context fini
Ben Widawsky [Mon, 14 Oct 2013 17:01:37 +0000 (10:01 -0700)]
drm/i915: cleanup context fini

I had this lying around from he original PPGTT series, and thought we
might try to get it in by itself.

With the introduction of context refcounting we never explicitly
ref/unref the backing object. As such, the previous fix was a bit wonky.

Aside from fixing the above, this patch also puts us in good shape for
an upcoming patch which allows a failure to occur in between
context_init and the first do_switch.

CC: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Do a fuller init after reset
Ben Widawsky [Mon, 14 Oct 2013 17:01:36 +0000 (10:01 -0700)]
drm/i915: Do a fuller init after reset

I had this lying around from he original PPGTT series, and thought we
might try to get it in by itself.

It's convenient to just call i915_gem_init_hw at reset because we'll be
adding new things to that function, and having just one function to call
instead of reimplementing it in two places is nice.

In order to accommodate we cleanup ringbuffers in order to bring them
back up cleanly. Optionally, we could also teardown/re initialize the
default context but this was causing some problems on reset which I
wasn't able to fully debug, and is unnecessary with the previous context
init/enable split.

This essentially reverts:
commit 8e88a2bd5987178d16d53686197404e149e996d9
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Tue Jun 19 18:40:00 2012 +0200

    drm/i915: don't call modeset_init_hw in i915_reset

It seems to work for me on ILK now. Perhaps it's due to:
commit 8a5c2ae753c588bcb2a4e38d1c6a39865dbf1ff3
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Thu Mar 28 13:57:19 2013 -0700

    drm/i915: fix ILK GPU reset for render

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Check 5/6 DDB split only when sprites are enabled
Ville Syrjälä [Fri, 11 Oct 2013 12:26:26 +0000 (15:26 +0300)]
drm/i915: Check 5/6 DDB split only when sprites are enabled

Using the 5/6 DDB split make sense only when sprites are enabled.
So check that before we waste any cycles computing the merged
watermarks with the 5/6 DDB split.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Rename ilk_check_wm to ilk_validate_wm_level
Ville Syrjälä [Wed, 9 Oct 2013 16:18:10 +0000 (19:18 +0300)]
drm/i915: Rename ilk_check_wm to ilk_validate_wm_level

Makes the behaviour of the function more clear.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Rename ilk_wm_max to ilk_compute_wm_maximums
Ville Syrjälä [Wed, 9 Oct 2013 16:18:09 +0000 (19:18 +0300)]
drm/i915: Rename ilk_wm_max to ilk_compute_wm_maximums

Makes the intention more clear.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Adjust watermark register masks
Ville Syrjälä [Wed, 9 Oct 2013 16:18:07 +0000 (19:18 +0300)]
drm/i915: Adjust watermark register masks

We want to be able to use the masks to decode the register contents
regardless of the hardware generation. So just expand the masks to
cover all available bits, even if those are reserved on some
generations.

v2: Don't extend WM1_LP_SR_MASK so far, for the *future*

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Remove a somewhat silly debug print from watermark code
Ville Syrjälä [Wed, 9 Oct 2013 16:18:06 +0000 (19:18 +0300)]
drm/i915: Remove a somewhat silly debug print from watermark code

This debug print just adds overhead to the watermark merging process,
and doesn't really give enough information to be useful. Just kill
and let's add something much better a bit later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Init HSW watermark tracking in intel_modeset_setup_hw_state()
Ville Syrjälä [Mon, 14 Oct 2013 11:55:24 +0000 (14:55 +0300)]
drm/i915: Init HSW watermark tracking in intel_modeset_setup_hw_state()

Fill out the HSW watermark s/w tracking structures with the current
hardware state in intel_modeset_setup_hw_state(). This allows us to skip
the HW state readback during watermark programming and just use the values
we keep around in dev_priv->wm. Reduces the overhead of the watermark
programming quite a bit.

v2: s/init_wm/wm_get_hw_state
    Remove stale comment about sprites
    Make DDB partitioning readout safer

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Fix whitespace fail.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Improve watermark dirtyness checks
Ville Syrjälä [Fri, 11 Oct 2013 16:39:52 +0000 (19:39 +0300)]
drm/i915: Improve watermark dirtyness checks

Currently hsw_write_vm_values() may write to certain watermark
registers needlessly. For instance if only, say, LP3 changes,
the current code will again disable all LP1+ watermarks even
though only LP3 needs to be reconfigured.

Add an easy to read function that will compute the dirtyness of the
watermarks, and use that information to further optimize the watermark
programming.

v2: Disable LP1+ watermarks around changing LP0 watermarks for Paulo

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Store current watermark state in dev_priv->wm
Ville Syrjälä [Wed, 9 Oct 2013 16:18:03 +0000 (19:18 +0300)]
drm/i915: Store current watermark state in dev_priv->wm

To make it easier to check what watermark updates are actually
necessary, keep copies of the relevant bits that match the current
hardware state.

Also add DDB partitioning into hsw_wm_values as that's another piece
of state we want to track.

We don't read out the hardware state on init yet, so we can't really
start using this yet, but it will be used later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Paulo asked for a comment around the memcmp to say that we
depend upon zero-initializing the entire structures due to padding.
But a later patch in this series removes the memcmp again. So this is
ok as-is.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Kill fbc_wm_enabled from intel_wm_config
Ville Syrjälä [Wed, 9 Oct 2013 16:18:02 +0000 (19:18 +0300)]
drm/i915: Kill fbc_wm_enabled from intel_wm_config

The fbc_wm_enabled member in intel_wm_config is useless for the time
being. The original idea for it was that we'd pre-compute it and so
that the WM merging process could know whether it needs to worry
about FBC watermarks at all.

But we don't have a convenient way to pre-check for the possibility
of FBC being used. intel_update_fbc() should be split up for that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Refactor wm_lp to level calculation
Ville Syrjälä [Wed, 9 Oct 2013 16:18:01 +0000 (19:18 +0300)]
drm/i915: Refactor wm_lp to level calculation

On HSW the LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4. We make the
conversion from LPn to to the level at one point current. Later we're
going to do it in a few places, so move it to a separate function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Check 5/6 DDB split only when sprites are enabled
Ville Syrjälä [Fri, 11 Oct 2013 12:26:26 +0000 (15:26 +0300)]
drm/i915: Check 5/6 DDB split only when sprites are enabled

Using the 5/6 DDB split make sense only when sprites are enabled.
So check that before we waste any cycles computing the merged
watermarks with the 5/6 DDB split.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Move some computations out from hsw_compute_wm_parameters()
Ville Syrjälä [Wed, 9 Oct 2013 16:17:59 +0000 (19:17 +0300)]
drm/i915: Move some computations out from hsw_compute_wm_parameters()

Move the watermark max computations into haswell_update_wm(). This
allows keeping the 1/2 vs. 5/6 split code in one place, and avoid having
to pass around so many things. We also save a bit of stack space by only
requiring one copy of struct hsw_wm_maximums.

Also move the intel_wm_config out from hsw_compute_wm_parameters() and
pass it it. We'll have some need for it in haswell_update_wm() later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Use intel_pipe_wm in hsw_find_best_results
Ville Syrjälä [Wed, 9 Oct 2013 16:17:58 +0000 (19:17 +0300)]
drm/i915: Use intel_pipe_wm in hsw_find_best_results

Let's try to keep using the intermediate intel_pipe_wm representation
for as long as possible. It avoids subtle knowledge about the
internals of the hardware registers when trying to choose the
best watermark configuration.

While at it replace the memset() w/ zero initialization.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Move LP1+ watermark merging out from hsw_compute_wm_results()
Ville Syrjälä [Wed, 9 Oct 2013 16:17:57 +0000 (19:17 +0300)]
drm/i915: Move LP1+ watermark merging out from hsw_compute_wm_results()

I want to convert hsw_find_best_result() to use intel_pipe_wm, so we
need to move the merging to happen outside hsw_compute_wm_results().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Don't re-compute pipe watermarks except for the affected pipe
Ville Syrjälä [Wed, 9 Oct 2013 16:17:56 +0000 (19:17 +0300)]
drm/i915: Don't re-compute pipe watermarks except for the affected pipe

No point in re-computing the watermarks for all pipes, when only one
pipe has changed. The watermarks stored under intel_crtc.wm.active are
still valid for the other pipes. We just need to redo the merging.

We can also skip the merge/update procedure completely if the new
watermarks for the affected pipe come out unchanged.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Add intel_pipe_wm and prepare for watermark pre-compute
Ville Syrjälä [Wed, 9 Oct 2013 16:17:55 +0000 (19:17 +0300)]
drm/i915: Add intel_pipe_wm and prepare for watermark pre-compute

Introduce a new struct intel_pipe_wm which contains all the
watermarks for a single pipe. Use it to unify the LP0 and LP1+
watermark computations so that we can just iterate through the
watermark levels neatly and call ilk_compute_wm_level() for each.

Also add another tool ilk_wm_merge() that merges the LP1+ watermarks
from all pipes. For that, embed one intel_pipe_wm inside intel_crtc that
contains the currently valid watermarks for each pipe.

This is mainly preparatory work for pre-computing the watermarks for
each pipe and merging them at a later time. For now the merging still
happens immediately.

v2: Add some comments about level 0 DDB split and intel_wm_config
    Add WARN_ON for level 0 being disabled
    s/lp_wm/merged

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915/dp: constify link_status
Jani Nikula [Tue, 15 Oct 2013 06:36:08 +0000 (09:36 +0300)]
drm/i915/dp: constify link_status

Follow-up to
commit 0aec288130713cf7bcf97c929ac5fab6a8e00e44
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Fri Sep 27 19:01:01 2013 +0300

    drm/dp: constify DP DPCD helpers

Requested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Don't pretend that gen2 has a hardware frame counter
Ville Syrjälä [Fri, 11 Oct 2013 18:52:44 +0000 (21:52 +0300)]
drm/i915: Don't pretend that gen2 has a hardware frame counter

Gen2 doesn't have a hardware frame counter that can be read out. Just
provide a stub .get_vblank_counter() that always returns 0 instead of
trying to read non-existing registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix gen2 scanout position readout
Ville Syrjälä [Fri, 11 Oct 2013 18:52:43 +0000 (21:52 +0300)]
drm/i915: Fix gen2 scanout position readout

Gen2 doesn't have the pixelcount register that gen3 and gen4 have.
Instead we must use the scanline counter like we do for ctg+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Improve the accuracy of get_scanout_pos on CTG+
Ville Syrjälä [Mon, 23 Sep 2013 10:02:07 +0000 (13:02 +0300)]
drm/i915: Improve the accuracy of get_scanout_pos on CTG+

The DSL register increments at the start of horizontal sync, so it
manages to miss the entire active portion of the current line.

Improve the get_scanoutpos accuracy a bit when the scanout position is
close to the start or end of vblank. We can do that by double checking
the DSL value against the vblank status bit from ISR.

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: mario.kleiner.de@gmail.com
Tested-by: mario.kleiner.de@gmail.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix scanoutpos calculations
Ville Syrjälä [Fri, 11 Oct 2013 16:10:32 +0000 (19:10 +0300)]
drm/i915: Fix scanoutpos calculations

The reported scanout position must be relative to the end of vblank.
Currently we manage to fumble that in a few ways.

First we don't consider the case when vtotal != vbl_end. While that
isn't very common (happens maybe only w/ old panel fitting hardware),
we can fix it easily enough.

The second issue is that on pre-CTG hardware we convert the pixel count
to horizontal/vertical components at the very beginning, and then forget
to adjust the horizontal component to be relative to vbl_end. So instead
we should keep our numbers in the pixel count domain while we're
adjusting the position to be relative to vbl_end. Then when we do the
conversion in the end, both vertical _and_ horizontal components will
come out correct.

v2: Change position to int from u32 to avoid sign issues

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: mario.kleiner.de@gmail.com
Tested-by: mario.kleiner.de@gmail.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Skip register reads in i915_get_crtc_scanoutpos()
Ville Syrjälä [Mon, 23 Sep 2013 11:48:50 +0000 (14:48 +0300)]
drm/i915: Skip register reads in i915_get_crtc_scanoutpos()

We have all the information we need in the mode structure, so going and
reading it from the hardware is pointless, and slower.

We never populated ->get_vblank_timestamp() in the UMS case, and as that
is the only way we'd ever call ->get_scanout_position(), we can
completely ignore UMS in i915_get_crtc_scanoutpos().

Also reorganize intel_irq_init() a bit to clarify the KMS vs. UMS
situation.

v2: Drop UMS code

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: mario.kleiner.de@gmail.com
Tested-by: mario.kleiner.de@gmail.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Use vlv_clock() in vlv_crtc_clock_get()
Ville Syrjälä [Mon, 14 Oct 2013 11:50:31 +0000 (14:50 +0300)]
drm/i915: Use vlv_clock() in vlv_crtc_clock_get()

Avoid some code duplication.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Use DIV_ROUND_CLOSEST() to calculate dot/vco
Ville Syrjälä [Mon, 14 Oct 2013 11:50:30 +0000 (14:50 +0300)]
drm/i915: Use DIV_ROUND_CLOSEST() to calculate dot/vco

Rounding down when calculating the dot/vco frequencies doesn't make much
sense. Round to closest should give slightly nicer answers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Add breadcrumbs for why the backlight is being set
Chris Wilson [Sun, 13 Oct 2013 11:56:31 +0000 (12:56 +0100)]
drm/i915: Add breadcrumbs for why the backlight is being set

At the moment we have 3 paths that lead to actually_set_backlight(),
from modesetting, ACPI/OpRegion requests and our very own
intel_backlight interface, and we have no way of distinguishing them in
the debug log. So add a debug breadcrumb to explain the source of the
backlight changes.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix pre-CTG vblank counter
Ville Syrjälä [Wed, 25 Sep 2013 16:55:26 +0000 (19:55 +0300)]
drm/i915: Fix pre-CTG vblank counter

The old style frame counter increments at the start of active video.
However for i915_get_vblank_counter() we want a counter that increments
at the start of vblank.

Fortunately the low frame counter register also contains the pixel
counter for the current frame. We can can compare that against the
vblank start pixel count to determine if we need to increment the
frame counter by 1 to get the correct answer.

Also reorganize the function pointer assignments in intel_irq_init() a
bit to avoid confusing people.

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: rename intel_fb.c to intel_fbdev.c
Daniel Vetter [Tue, 8 Oct 2013 15:44:49 +0000 (17:44 +0200)]
drm/i915: rename intel_fb.c to intel_fbdev.c

This file is all about the legacy fbdev support. If we want to extract
framebuffer functions, we better put those into a separate file.

Also rename functions accordingly, only two have used the intel_fb_
prefix anyway.

Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Kconfig option to disable the legacy fbdev support
Daniel Vetter [Wed, 9 Oct 2013 07:18:51 +0000 (09:18 +0200)]
drm/i915: Kconfig option to disable the legacy fbdev support

Boots Just Fine (tm)!

The only glitch seems to be that at least on Fedora the boot splash
gets confused and doesn't display much at all.

And since there's no ugly console flickering anymore in between, the
flicker while switching between X servers (VT support is still enabled)
is even more jarring.

Also, I'm unsure whether we don't need to somehow kick out vgacon, now
that nothing else gets in the way. But stuff seems to work, so I
don't care. Also everything still works as well with VGA_CONSOLE=n

Also the #ifdef mess needs a bit of a cleanup, follow-up patches will
do just that.

To keep the Kconfig tidy, extract all the i915 options into its own
file.

v2:
- Rebase on top of the preliminary hw support option and the
  intel_drv.h cleanup.
- Shut up warnings in i915_debugfs.c

v3: Use the right CONFIG variable, spotted by Chon Ming.

Cc: Lee, Chon Ming <chon.ming.lee@intel.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm: Add separate Kconfig option for fbdev helpers
Daniel Vetter [Tue, 8 Oct 2013 15:44:47 +0000 (17:44 +0200)]
drm: Add separate Kconfig option for fbdev helpers

For drivers which might want to disable fbdev legacy support.

Select the new option in all drivers for now, so this shouldn't result
in any change. Drivers need some work anyway to make fbdev support
optional (if they have it implemented, that is), so the recommended
way to expose this is by adding per-driver options. At least as long
as most drivers don't support disabling the fbdev support.

v2: Update for new drm drivers msm and rcar-du. Note that Rob's msm
driver can already take advantage of this, which allows us to build
msm without any fbdev depencies in the kernel!

v3: Move the MODULE_* stuff from the fbdev helper file to
drm_crtc_helper.c.

Cc: David Herrmann <dh.herrmann@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Acked-by: Dave Airlie <airlied@linux.ie>
Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix VLV frame counter registers
Ville Syrjälä [Fri, 11 Oct 2013 19:24:41 +0000 (22:24 +0300)]
drm/i915: Fix VLV frame counter registers

Supposedly VLV uses the CTG+ style frame counter registers instead of
the old gen3/4 style. Add the magic offset to the correct registers.

We should already be taking the correct codepaths for
.get_vblank_counter() and .get_scanout_position().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915/vlv: add doc names to sideband file
Jesse Barnes [Fri, 11 Oct 2013 19:09:30 +0000 (12:09 -0700)]
drm/i915/vlv: add doc names to sideband file

So digging out the right ones is a little easier.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: don't save/restore CACHE_MODE_0 on gen7+
Jesse Barnes [Fri, 11 Oct 2013 19:09:29 +0000 (12:09 -0700)]
drm/i915: don't save/restore CACHE_MODE_0 on gen7+

On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather
than restoring CACHE_MODE_0.  Don't do that.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix pipe off timeout handling for pre-gen4
Ville Syrjälä [Fri, 11 Oct 2013 11:21:31 +0000 (14:21 +0300)]
drm/i915: Fix pipe off timeout handling for pre-gen4

The current pre-gen4 pipe off code might break out of the loop
due to the timeout, but then the fail to print the warning.

Refactor the code a bit to use wait_for() to avoid the problem,
and that we also re-check the condition after the timeout has
expired.

v2: Use wait_for()

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: increase the SWSCI DSLP default timeout to 50ms
Paulo Zanoni [Wed, 9 Oct 2013 19:39:57 +0000 (16:39 -0300)]
drm/i915: increase the SWSCI DSLP default timeout to 50ms

The spec says the default timeout should be 2ms, but on my machine
this doesn't seem to be enough. Sometimes it works, sometimes I get
these messages when booting:
  - SWSCI request timed out
  - SWSCI request already in progress

And my guess is that the "already in progress" message is because the
first one is still happening.

I did some experiments on my machine (that has CONFIG_HZ=1000) and the
wait_for function usually takes 4-6 jiffies to finish, but I've seen
up to 9. So increase the timeout to 50ms. We only expect to wait for
the actual amount of time the operation takes, so even a huge timeout
shouldn't delay us more than what the hardware actually requires.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Avoid tweaking RPS before it is enabled
Chris Wilson [Thu, 10 Oct 2013 20:58:50 +0000 (21:58 +0100)]
drm/i915: Avoid tweaking RPS before it is enabled

As we delay the initial RPS enabling (upon boot and after resume), there
is a chance that we may start to render and trigger RPS boosts before we
set up the punit. Any changes we make could result in inconsistent
hardware state, with a danger of causing undefined behaviour. However,
as the boosting is a optional tweak to RPS, we can simply ignore it
whilst RPS is not yet enabled.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: tell the user KMS is required for gen6+
Jani Nikula [Thu, 10 Oct 2013 12:25:37 +0000 (15:25 +0300)]
drm/i915: tell the user KMS is required for gen6+

Educate the users why i915 won't load on gen6+ and nomodeset.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=61671
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Educate users in dmesg about reporting gpu hangs
Daniel Vetter [Wed, 9 Oct 2013 17:22:22 +0000 (19:22 +0200)]
drm/i915: Educate users in dmesg about reporting gpu hangs

Untangling me-too reports that actually aren't is really messy. And we
need to make sure the blame is put where it should be right from the
start ;-)

v2: Improve the wording from Ben's suggestions.

Cc: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Frob the message as suggested by Paulo on irc.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Finish enabling rps before use by sysfs or debugfs
Tom O'Rourke [Mon, 16 Sep 2013 21:56:43 +0000 (14:56 -0700)]
drm/i915: Finish enabling rps before use by sysfs or debugfs

Enabling rps (turbo setup) was put in a work queue because it may
take quite awhile.  This change flushes the work queue to initialize
rps values before use by sysfs or debugfs.  Specifically,
rps.delayed_resume_work is flushed before using rps.hw_max,
rps.max_delay, rps.min_delay, or rps.cur_delay.

This change fixes a problem in sysfs where show functions using
uninitialized values show incorrect values and store functions
using uninitialized values in range checks incorrectly fail to
store valid input values.  This change also addresses similar use
before initialized problems in debugfs.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Capture the initial error-state when kicking stuck rings
Chris Wilson [Thu, 10 Oct 2013 08:37:19 +0000 (09:37 +0100)]
drm/i915: Capture the initial error-state when kicking stuck rings

We lost the ability to capture the first error for a stuck ring in the
recent hangcheck robustification. Whilst both error states are
interesting (why does the GPU not recover is also essential to debug),
our primary goal is to fix the initial hang and so we need to capture
the first error state upon taking hangcheck action.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Rename primary_disabled to primary_enabled
Ville Syrjälä [Wed, 9 Oct 2013 14:24:58 +0000 (17:24 +0300)]
drm/i915: Rename primary_disabled to primary_enabled

Let's try to avoid these confusing negated booleans.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Populate primary_disabled in intel_modeset_readout_hw_state()
Ville Syrjälä [Wed, 9 Oct 2013 14:24:57 +0000 (17:24 +0300)]
drm/i915: Populate primary_disabled in intel_modeset_readout_hw_state()

Make sure our primary_disabled matches our expectations after driver
init.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70270
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: shui yangwei <yangweix.shui@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: don't leak dp_connector at intel_ddi_init
Paulo Zanoni [Wed, 9 Oct 2013 16:52:36 +0000 (13:52 -0300)]
drm/i915: don't leak dp_connector at intel_ddi_init

Regression introduced by:
    commit 311a20949f047a70935d6591010f42336f5402e7
    Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
        drm/i915: don't init DP or HDMI when not supported by DDI port

Since the commit above it is possible to have a DDI encoder that has
the HDMI connector but not the DP connector (in case the port doesn't
support DP). In this case, we must properly free the DP connector.

We just leak this once, so it's not a big deal.

Reported by kmemleak.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915/dp: update training set in a burst write with training pattern set
Jani Nikula [Fri, 4 Oct 2013 12:08:48 +0000 (15:08 +0300)]
drm/i915/dp: update training set in a burst write with training pattern set

The DP spec allows this, and requires it when full link training is
started with non-minimum voltage swing and/or non-zero pre-emphasis.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Do PCH and uncore init earlier
Ben Widawsky [Tue, 8 Oct 2013 23:31:03 +0000 (16:31 -0700)]
drm/i915: Do PCH and uncore init earlier

For future platforms we'll need to initialize our MMIO function pointers
even earlier. Specifically, we'll need to be able to have register
reads/writes at GTT initialization (in i915_gem_gtt_init). Similarly,
these platforms also have MMIO differences based on the PCH id, so
while moving stuff around, also move the PCH initialization.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Mention the function where we need register access.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: wait for IPS_ENABLE when enabling IPS
Paulo Zanoni [Thu, 19 Sep 2013 20:03:06 +0000 (17:03 -0300)]
drm/i915: wait for IPS_ENABLE when enabling IPS

At the end of haswell_crtc_enable we have an intel_wait_for_vblank
with a big comment, and the message suggests it's a workaround for
something we don't really understand. So I removed that wait and
started getting HW state readout error messages saying that the IPS
state is not what we expected.

I investigated and concluded that after you write IPS_ENABLE to
IPS_CTL, the bit will only actually become 1 on the next vblank. So
add code to wait for the IPS_ENABLE bit. We don't really need this
wait right now due to the wait I already mentioned, but at least this
one has a reason to be there, while the other one is just to
workaround some problem: we may remove it in the future.

The wait also acts as a POSTING_READ which we missed.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Keep intel_drv.h tidy
Daniel Vetter [Tue, 8 Oct 2013 17:39:29 +0000 (19:39 +0200)]
drm/i915: Keep intel_drv.h tidy

Something already got misplaced (although it's from a patch from
before Paulo's cleanup). Move it to the right spot.

v2: Remove the line to keep a neat block, requested by Paulo.

Reported-by: Paulo Zanoni <przanoni@gmail.com>
Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Remove gen specific checks in MMIO
Ben Widawsky [Sun, 6 Oct 2013 00:57:11 +0000 (17:57 -0700)]
drm/i915: Remove gen specific checks in MMIO

Now that MMIO has been split up into gen specific functions it is
obvious when HAS_FPGA_DBG_UNCLAIMED, HAS_FORCE_WAKE are needed. As such,
we can remove this extraneous condition.

As a result of this, as well as previously existing function pointers
for forcewake, we no longer need the has_force_wake member in the device
specific data structure.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Create GEN specific write MMIO
Ben Widawsky [Sat, 5 Oct 2013 04:22:54 +0000 (21:22 -0700)]
drm/i915: Create GEN specific write MMIO

Similar to the previous patch which implemented GEN specific reads; this
patch does the same for writes. Writes have a bit of adding complexity
due to the FPGA_DBG feature of HSW plus:

gen[2-4]: nothing special
gen5: ILK dummy write
gen[6-7]: forcewake shenanigans
gen[HSW}: forcewake shenanigans + FPGA_DBG

I was a bit torn about whether or not to combine 6-HSW as one function,
since the FPGA_DBG is cleanly separated, and it wouldn't make the 6-7
MMIO too messy. In the end, I chose the clearest possible solution which
splits out HSW.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Create GEN specific read MMIO
Ben Widawsky [Sat, 5 Oct 2013 04:22:53 +0000 (21:22 -0700)]
drm/i915: Create GEN specific read MMIO

Extracting the MMIO read functionality makes per gen handling a bit
simpler, and the overall function a lot easier to read. The increasing
complexity of reads doesn't get too bad as the generation number
increases:

gen[2-4]: Nothing special
gen5: ILK dummy write workaround
gen6+: forcewake shenanigans

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Extract common MMIO lines
Ben Widawsky [Sat, 5 Oct 2013 04:24:53 +0000 (21:24 -0700)]
drm/i915: Extract common MMIO lines

Just to make the churn and code duplication in upcoming patches a bit
less, turn code which is common to all GEN MMIO functions into a macro.

v2: Fix typo in subject

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Create MMIO virtual functions
Ben Widawsky [Sat, 5 Oct 2013 04:22:51 +0000 (21:22 -0700)]
drm/i915: Create MMIO virtual functions

In preparation for having per GEN MMIO functions, create, and start
using MMIO functions in our uncore data structure. This simply makes the
transition easier by allowing us to just plug in the per GEN stuff
later.

For simplicity, I moved the intel_uncore_init() function down since
those rely on static functions defined lower in the file. This is most
of the churn in this patch.

I made one unrelated change here by using off_t datatype for the offset
of the register to write. I like the clarity that this brings to the
code. If I did it as a separate patch, I am pretty certain it would get
bikeshedded to oblivion.

Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Move edram detection early_sanitize
Ben Widawsky [Sat, 5 Oct 2013 04:22:50 +0000 (21:22 -0700)]
drm/i915: Move edram detection early_sanitize

In order to be able to have virtual functions for the MMIO, we need to
use the raw access function. To keep things simple, just move this to
our early_sanitize code in uncore.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Prevent using uninitialized MMIO funcs
Ben Widawsky [Sat, 5 Oct 2013 04:22:49 +0000 (21:22 -0700)]
drm/i915: Prevent using uninitialized MMIO funcs

For upcoming patches which will have GEN specific MMIO functions, we'll
need to initialize the uncore data structure earlier than we do today.

If we do not do this, the following will be problematic:

intel_uncore_sanitize
intel_disable_gt_powersave
gen6_disable_rps
I915_WRITE(GEN6_RC_CONTROL, 0); <--- MMIO
intel_uncore_init // initializes MMIO

By initializing the function pointers first, we should be safe.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: rip out gen2 reset code
Daniel Vetter [Tue, 8 Oct 2013 10:25:41 +0000 (12:25 +0200)]
drm/i915: rip out gen2 reset code

At least on my i830M here it reliably results in hard system hangs
nowadays. This is much worse than falling back to software rendering,
so I think we should simply rip this out.

After all we don't have any gpu reset for gen3 either, and there are a
lot more of those still around.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: check that the i965g/gm 4G limit is really obeyed
Daniel Vetter [Mon, 7 Oct 2013 20:15:45 +0000 (17:15 -0300)]
drm/i915: check that the i965g/gm 4G limit is really obeyed

In truly crazy circumstances shmem might give us the wrong type of
page. So be a bit paranoid and double check this.

Reviewer: Damien Lespiau <damien.lespiau@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
References: http://lkml.org/lkml/2011/7/11/238
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Undo the PIPEA quirk for i845
Chris Wilson [Tue, 8 Oct 2013 10:16:59 +0000 (11:16 +0100)]
drm/i915: Undo the PIPEA quirk for i845

The PIPEA quirk is specifically for the issue with the PIPEB PLL on
830gm being slaved to the PIPEA PLL, and so to use PIPEB requires PIPEA
running. i845 doesn't even have the second PLL or pipe, and enabling
the quirk results in a blank DVO LVDS.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Use the real cpu max frequency for ring scaling
Ben Widawsky [Mon, 7 Oct 2013 20:15:48 +0000 (17:15 -0300)]
drm/i915: Use the real cpu max frequency for ring scaling

The policy's max frequency is not equal to the CPU's max frequency. The
ring frequency is derived from the CPU frequency, and not the policy
frequency.

One example of how this may differ through sysfs. If the sysfs max
frequency is modified, that will be used for the max ring frequency
calculation.
(/sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq). As far as I
know, no current governor uses anything but max as the default, but in
theory, they could. Similarly distributions might set policy as part of
their init process.

It's ideal to use the real frequency because when we're currently scaled
up on the GPU. In this case we likely want to race to idle, and using a
less than max ring frequency is non-optimal for this situation.

AFAIK, this patch should have no impact on a majority of people.

This behavior hasn't been changed since it was first introduced:
commit 23b2f8bb92feb83127679c53633def32d3108e70
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Tue Jun 28 13:04:16 2011 -0700

    drm/i915: load a ring frequency scaling table v3

CC: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Flush primary plane changes in sprite code
Ville Syrjälä [Tue, 1 Oct 2013 15:02:21 +0000 (18:02 +0300)]
drm/i915: Flush primary plane changes in sprite code

Flush the primary plane changes when enabling/disabling the primary
plane in response to sprite visibility.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: WARN if primary plane state doesn't match expectations
Ville Syrjälä [Tue, 1 Oct 2013 15:02:20 +0000 (18:02 +0300)]
drm/i915: WARN if primary plane state doesn't match expectations

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Rename intel_{enable, disable}_plane to intel_{enable, disable}_primary_plane
Ville Syrjälä [Tue, 1 Oct 2013 15:02:19 +0000 (18:02 +0300)]
drm/i915: Rename intel_{enable, disable}_plane to intel_{enable, disable}_primary_plane

The new names make it clearer which plane we're talking about.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Resolve small conflict with the haswell_crtc_disable_planes
extraction.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Rename intel_flush_display_plane to intel_flush_primary_plane
Ville Syrjälä [Tue, 1 Oct 2013 15:02:18 +0000 (18:02 +0300)]
drm/i915: Rename intel_flush_display_plane to intel_flush_primary_plane

The intel_flush_primary_plane name actually tells us which plane
we're talking about.

Also reorganize the internals a bit and add a missing POSTING_READ()
to make sure the hardware has seen the changes by the time we
return from the function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Enable/disable IPS when primary is enabled/disabled
Ville Syrjälä [Tue, 1 Oct 2013 15:02:17 +0000 (18:02 +0300)]
drm/i915: Enable/disable IPS when primary is enabled/disabled

IPS should be OK as long as one plane is enabled on the pipe, but
it does seem to cause problems when going between primary only and
sprite only.

This needs more investigations, but for now just disable IPS whenever
the primary plane is disabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Do the fbc vs. primary plane enable/disable in the right order
Ville Syrjälä [Tue, 1 Oct 2013 15:02:16 +0000 (18:02 +0300)]
drm/i915: Do the fbc vs. primary plane enable/disable in the right order

Disable fbc before disabling the primary plane, and enable fbc after
the primary plane has been enabled again.

Also use intel_disable_fbc() to disable FBC to avoid the pointless
overhead of intel_update_fbc(), and especially avoid having to clean
up and set up the stolen mem compressed buffer again.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Save user requested plane coordinates only on success
Ville Syrjälä [Tue, 1 Oct 2013 15:02:15 +0000 (18:02 +0300)]
drm/i915: Save user requested plane coordinates only on success

If the setplane operation fails, we shouldn't save the user's requested
plane coordinates. Since we adjust the coordinates during the clipping
process, make a copy of the originals, and once the operation has
succeeded save them for later reuse when the plane gets re-enabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Do a bit of cleanup in the sprite code
Ville Syrjälä [Tue, 1 Oct 2013 15:02:14 +0000 (18:02 +0300)]
drm/i915: Do a bit of cleanup in the sprite code

Move the variable initialization to where the variables are declared,
and kill a pointless to_intel_crtc() cast when we already have the
casted pointer.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Kill a goto from sprite disable code
Ville Syrjälä [Tue, 1 Oct 2013 15:02:13 +0000 (18:02 +0300)]
drm/i915: Kill a goto from sprite disable code

Let's not use goto when a simple if suffices. This is not error handling
code or anything, so the goto looks out of place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Reduce the time we hold struct mutex in sprite update_plane code
Ville Syrjälä [Tue, 1 Oct 2013 15:02:12 +0000 (18:02 +0300)]
drm/i915: Reduce the time we hold struct mutex in sprite update_plane code

We used to call the entire intel specific update_plane hook while
holding struct_mutex. Actually we only need to hold struct_mutex while
pinning/unpinning the obj. The plane state itself is protected by the
kms locks, and as the object is pinned we can dig out the offset and
tiling information from it without fearing that it would change
underneath us.

So now we don't need to drop and reacquire the lock around the
wait_for_vblank. Also we will need another wait_for_vblank in the IVB
specific update_plane hook, and this way we don't need to worry about
struct_mutex there either.

Also move the intel_plane->obj=NULL assignment outside strut_mutex in
disable_plane to make it clear that it's not protected by struct_mutex.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Allow sprites to be configured on a disabled pipe
Ville Syrjälä [Tue, 1 Oct 2013 15:02:11 +0000 (18:02 +0300)]
drm/i915: Allow sprites to be configured on a disabled pipe

We allow cursors to be set up when the pipe is disabled. Do the same for
sprites as well.

We need to be somewhat careful with the primary disable logic as we
don't want to accidentally enable the primary plane on a disabled pipe.

v2: Skip primary enable/disable and plane registers
    writes on disabled pipe

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Set primary_disabled in intel_{enable, disable}_plane
Ville Syrjälä [Tue, 1 Oct 2013 15:02:10 +0000 (18:02 +0300)]
drm/i915: Set primary_disabled in intel_{enable, disable}_plane

If the primary gets marked as disabled while the pipe is off for
instance, we should still re-enable it when the pipe is turned on,
unless the sprite covers it fully also in that configuration.
Unfortunately we do the plane visibility checks only in the sprite code,
which is executed after the primary enabling when turning the pipe off.

Ideally we should compute the plane visibility before touching the
hardware at all, but for now just set the primary_disabld flag
in intel_{enable,disable}_plane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915/dp: promote clock recovery failures to DRM_ERROR
Jani Nikula [Sat, 5 Oct 2013 13:13:56 +0000 (16:13 +0300)]
drm/i915/dp: promote clock recovery failures to DRM_ERROR

If channel equalization succeeds, there's no indication something went
wrong in clock recovery (unless debug is enabled). We should shout about
the failures and fix them instead of hiding them under the carpet.

This has allowed bugs like [1] stay dormant for a long time.

[1] https://bugs.freedesktop.org/show_bug.cgi?id=70117

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix VGA_DISP_DISABLE check
Ville Syrjälä [Fri, 4 Oct 2013 17:32:25 +0000 (20:32 +0300)]
drm/i915: Fix VGA_DISP_DISABLE check

The VGACNTRL register contains a bunch of other stuff besides
the VGA_DISP_DISABLE bit. When we write the register we always set those
other bits to zero, so normally the current check would work.

However on HSW disabling and re-enabling the power well will reset the
VGACNTRL register to its default value, which has several of the other
bits set as well.

So only look at the VGA_DISP_DISABLE bit when checking whether the VGA
plane needs re-disabling.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Use intel_PLL_is_valid() in vlv_find_best_dpll()
Ville Syrjälä [Fri, 27 Sep 2013 13:55:49 +0000 (16:55 +0300)]
drm/i915: Use intel_PLL_is_valid() in vlv_find_best_dpll()

Everyone else uses intel_PLL_is_valid(), so make VLV use it as well.

We don't have any special p and m limits on VLV, so skip those tests,
and we also need to skip the m1<=m2 test line PNV.

Reorganize the function a bit to move the n check alongside the rest of
the test for the non-derived dividers, and check the derived values
afterwards.

Note that this changes vlv_find_best_dpll() in two ways:
- The .vco comparison is now >max instead of >=max, and since we round
  down when calculating that stuff, we may now allow frequencies slightly
  above the max as we do on other platforms. The previous method
  disallowed exactly max and anything above it.
- We now check the .dot frequency against the data rate limits, which we
  didn't do before.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Don't lie about findind suitable PLL settings on VLV
Ville Syrjälä [Tue, 24 Sep 2013 18:26:31 +0000 (21:26 +0300)]
drm/i915: Don't lie about findind suitable PLL settings on VLV

If vlv_find_best_dpll() couldn't find suitable PLL settings,
just say so instead of lying to caller.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: intel_limits_vlv_dac and intel_limits_vlv_hdmi are the same
Ville Syrjälä [Tue, 24 Sep 2013 18:26:30 +0000 (21:26 +0300)]
drm/i915: intel_limits_vlv_dac and intel_limits_vlv_hdmi are the same

After aligning the p1 divider limits, and removing the unused p and m
limits, intel_limits_vlv_dac and intel_limits_vlv_hdmi are identical.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Remove unused dot_limit from VLV PLL limits
Ville Syrjälä [Tue, 24 Sep 2013 18:26:29 +0000 (21:26 +0300)]
drm/i915: Remove unused dot_limit from VLV PLL limits

We don't use .dot_limit for anything on VLV, so don't populate it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Remove the unused p and m limits for VLV
Ville Syrjälä [Tue, 24 Sep 2013 18:26:28 +0000 (21:26 +0300)]
drm/i915: Remove the unused p and m limits for VLV

We never check the p and m limits (which according to comments are
based on someone's guesswork), so just remove them.

VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm has no p and m
limits listed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Respect p2 divider minimum limit on VLV
Ville Syrjälä [Tue, 24 Sep 2013 18:26:27 +0000 (21:26 +0300)]
drm/i915: Respect p2 divider minimum limit on VLV

VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm tells us that the
minimum p2 divider is 2. Use that limit on the code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Allow p1 divider 2 on VLV
Ville Syrjälä [Tue, 24 Sep 2013 18:26:26 +0000 (21:26 +0300)]
drm/i915: Allow p1 divider 2 on VLV

According to VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm p1
can be 2-3 always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Clarify VLV PLL p1 limits
Ville Syrjälä [Tue, 24 Sep 2013 18:26:25 +0000 (21:26 +0300)]
drm/i915: Clarify VLV PLL p1 limits

For some reason there's a sort of off by one issue with the p1 divider.
The actual p1 limits according to
VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm is 2-3, so we should
just say that instead of saying 1-3 and avoiding the 1 via the choice of
comparison operator.

I don't know why we're using different p1 limits for intel_limits_vlv_dac
and intel_limits_vlv_hdmi, but let's preserve that for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Make sure we respect n.max on VLV
Ville Syrjälä [Tue, 24 Sep 2013 18:26:24 +0000 (21:26 +0300)]
drm/i915: Make sure we respect n.max on VLV

We limit the maximum n divider value in order to make sure the PLL's
reference inout is at least 19.2 MHz. I assume that is done to satisfy
some hardware requirement.

However we never check whether that calculated limit is below the
maximum supoorted N divider value (7). In practice that is always true
since we only support 100 MHz reference clock, but making the code
safe against higher reference clocks seems like a reasoanble thing to
do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: De-magic the VLV p2 divider step size
Ville Syrjälä [Tue, 24 Sep 2013 18:26:23 +0000 (21:26 +0300)]
drm/i915: De-magic the VLV p2 divider step size

The p2 divider on VLV needs to be even when it's > 10. The current code
to make that happen is rather weird. Just make the step size adjustement
in the for loop decrement step.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Rewrite vlv_find_best_dpll()
Ville Syrjälä [Fri, 27 Sep 2013 13:54:19 +0000 (16:54 +0300)]
drm/i915: Rewrite vlv_find_best_dpll()

Rewrite vlv_find_best_dpll() to use intel_clock_t rather than
an army of local variables.

Also extract the code to calculate the derived values into
vlv_clock().

v2: Split up the earlier fixes, extract vlv_clock()
v3: Initialize best_clock

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Don't underflow bestppm
Ville Syrjälä [Tue, 24 Sep 2013 18:26:21 +0000 (21:26 +0300)]
drm/i915: Don't underflow bestppm

We do 'bestppm - 10' in vlv_find_best_dpll() but never check whether
that might underflow. Add such a check.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Make vlv_find_best_dpll() ppm calculation safe
Ville Syrjälä [Tue, 24 Sep 2013 18:26:20 +0000 (21:26 +0300)]
drm/i915: Make vlv_find_best_dpll() ppm calculation safe

Use div_u64() to make the ppm calculation in vlv_find_best_dpll() safe
against interger overflows.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915/dp: use sizeof for memset instead of magic value
Jani Nikula [Fri, 4 Oct 2013 12:08:47 +0000 (15:08 +0300)]
drm/i915/dp: use sizeof for memset instead of magic value

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Remove yet another unused define
Damien Lespiau [Fri, 4 Oct 2013 11:27:00 +0000 (12:27 +0100)]
drm/i915: Remove yet another unused define

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Fix type mismatch and accounting in i915_gem_shrink
Chris Wilson [Fri, 4 Oct 2013 09:33:00 +0000 (10:33 +0100)]
drm/i915: Fix type mismatch and accounting in i915_gem_shrink

The interface uses an unsigned long, and we can use the unsigned counter
throughout our code, so do so. In the process, we notice one instance
where the shrink count is based on a heuristic rather than the result,
and another where we ask for too many pages to be purged.

v2: nr_to_scan needs to be promoted to a long as well, so just use
    sc->nr_to_scan directly.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915: Call io_schedule() whilst whilsting for the GPU
Chris Wilson [Fri, 4 Oct 2013 08:58:46 +0000 (09:58 +0100)]
drm/i915: Call io_schedule() whilst whilsting for the GPU

Since we are waiting upon IO completion, inform the kernel through use
of the io_schedule() call rather than the regular schedule(). This
should allow the kernel to make better decisions regarding scheduling
and power management.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agoMerge remote-tracking branch 'airlied/drm-next' into drm-intel-next
Daniel Vetter [Thu, 10 Oct 2013 10:44:43 +0000 (12:44 +0200)]
Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next

The conflict in intel_drv.h tripped me up a bit since a patch in dinq
moves all the functions around, but another one in drm-next removes a
single function. So I'ev figured backing this into a backmerge would
be good.

i915_dma.c is just adjacent lines changed, nothing nefarious there.

Conflicts:
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/intel_drv.h

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
11 years agodrm/i915/dp: get rid of intel_dp->link_configuration
Jani Nikula [Fri, 4 Oct 2013 12:08:10 +0000 (15:08 +0300)]
drm/i915/dp: get rid of intel_dp->link_configuration

It's not really needed, rather just adds another place to hold
intermediate values that could go wrong, and it's not clear that the
training pattern set or training lane set should be written at this
point at all.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
11 years agodrm/radeon/dp: use drm_dp_enhanced_frame_cap()
Jani Nikula [Fri, 4 Oct 2013 12:08:09 +0000 (15:08 +0300)]
drm/radeon/dp: use drm_dp_enhanced_frame_cap()

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
11 years agodrm/dp: add helper for checking DP_ENHANCED_FRAME_CAP in DPCD
Jani Nikula [Fri, 4 Oct 2013 12:08:08 +0000 (15:08 +0300)]
drm/dp: add helper for checking DP_ENHANCED_FRAME_CAP in DPCD

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
11 years agodrm: Kill drm perf counter leftovers
Ville Syrjälä [Fri, 4 Oct 2013 11:53:41 +0000 (14:53 +0300)]
drm: Kill drm perf counter leftovers

The user of these counters was killed in

 commit d79cdc8312689b39c6d83718c1c196af4b3cd18c
 Author: Daniel Vetter <daniel.vetter@ffwll.ch>
 Date:   Thu Aug 8 15:41:32 2013 +0200

    drm: no-op out GET_STATS ioctl

so clean up the leftovers as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
11 years agodrm: Remove pci_vendor and pci_device from struct drm_device
Ville Syrjälä [Fri, 4 Oct 2013 11:53:40 +0000 (14:53 +0300)]
drm: Remove pci_vendor and pci_device from struct drm_device

We can get the PCI vendor and device IDs via dev->pdev. So we can drop
the duplicated information.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
11 years agodrm: Kill ctx_count from struct drm_device
Ville Syrjälä [Fri, 4 Oct 2013 11:53:39 +0000 (14:53 +0300)]
drm: Kill ctx_count from struct drm_device

The only user of ctx_count is the via driver, and we can replace that
use with list_is_singular().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>