GitHub/exynos8895/android_kernel_samsung_universal8895.git
10 years agodrm/nouveau/gpio: split g92 class from nv50
Ben Skeggs [Mon, 12 May 2014 05:22:42 +0000 (15:22 +1000)]
drm/nouveau/gpio: split g92 class from nv50

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: use indirect pointer to base class definition
Ben Skeggs [Mon, 12 May 2014 04:18:06 +0000 (14:18 +1000)]
drm/nouveau/gpio: use indirect pointer to base class definition

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support training to highest rate, rather than a target
Ben Skeggs [Fri, 16 May 2014 00:49:28 +0000 (10:49 +1000)]
drm/nouveau/disp/dp: support training to highest rate, rather than a target

We really want this for, at least, MST devices.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support postcursor in link training
Ben Skeggs [Thu, 15 May 2014 12:20:40 +0000 (22:20 +1000)]
drm/nouveau/disp/dp: support postcursor in link training

Not enabled at the backends yet, but will read status and send back max
reached at level 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/core: allow event source to handle multiple event types per index
Ben Skeggs [Tue, 13 May 2014 05:30:15 +0000 (15:30 +1000)]
drm/nouveau/core: allow event source to handle multiple event types per index

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/gk208/gr: add missing registers to grctx init
Ilia Mirkin [Sat, 7 Jun 2014 19:39:45 +0000 (15:39 -0400)]
drm/gk208/gr: add missing registers to grctx init

This fixes hangs on GK208 which happen instantaneously on trying to use a
geometry shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org # v3.14+
10 years agodrm/nouveau/kms/nv04-nv40: fix pageflip events via special case.
Mario Kleiner [Mon, 12 May 2014 22:42:08 +0000 (00:42 +0200)]
drm/nouveau/kms/nv04-nv40: fix pageflip events via special case.

Cards with nv04 display engine can't reliably use vblank
counts and timestamps computed via drm_handle_vblank(), as
the function gets invoked after sending the pageflip events.

Fix this by defaulting to the old crtcid = -1 fallback path
on <= NV-50 cards, and only using the precise path on NV-50
and later.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: <stable@vger.kernel.org> # 3.13+
10 years agodrm/nv50-/mc: fix kms pageflip events by reordering irq handling order.
Mario Kleiner [Wed, 19 Mar 2014 07:12:51 +0000 (08:12 +0100)]
drm/nv50-/mc: fix kms pageflip events by reordering irq handling order.

Whenever a single nouveau_mc_intr() main gpu irq-handler invocation was
responsible for calling both, the vblank-irq handler (display engine irq)
and kms-pageflip completion handler (from fifo irq), the order of
invocation was wrong. nouveau_finish_flip() was called before
drm_handle_vblank() for the vblank of pageflip completion, so the
emitted pageflip event contained stale vblank count and timestamp
from previous vblank. This caused failure in userspace to timestamp
properly.

Reorder order of invocation of engine irq handlers: Put
NVDEV_ENGINE_DISP always on top, and thereby before NVDEV_ENGINE_FIFO,
so that drm_handle_vblank() gets called to update vblank timestamps
and count before potential pageflip events make use of that
information.

This works on nv-50 and later, where kms-pageflip completion triggers
an irq either after a separate vblank irq, or both pageflip and vblank
trigger one common irq invocation, but never before vblank irqs.

v2 (Ben):
- removed mods for nv04-nv40, it doesn't help there anyway
- this is considered a hack, and a better solution should be found

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: <stable@vger.kernel.org> # 3.13+
10 years agodrm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.
Mario Kleiner [Wed, 28 May 2014 03:22:18 +0000 (05:22 +0200)]
drm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.

nv04_disp_scanoutpos() must abort to trigger simple timestamping
fallback if vtotal/htotal regs return zero. This happens if the
output isn't a digital output, but a vga analog output, as the
regs don't get initialized in that case.

Fixes timestamping failure on nv-40 and earlier with vga output.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: <stable@vger.kernel.org> # 3.14+
10 years agodrm/nv50-/kms: wait for enough ring space in crtc_prepare()
Ben Skeggs [Mon, 19 May 2014 04:54:33 +0000 (14:54 +1000)]
drm/nv50-/kms: wait for enough ring space in crtc_prepare()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support training pattern 3
Ben Skeggs [Thu, 15 May 2014 12:00:06 +0000 (22:00 +1000)]
drm/nouveau/disp/dp: support training pattern 3

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support aux read interval during link training
Ben Skeggs [Thu, 15 May 2014 11:50:07 +0000 (21:50 +1000)]
drm/nouveau/disp/dp: support aux read interval during link training

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/gk104/gpio: fix incorrect interrupt register usage
Ben Skeggs [Mon, 12 May 2014 04:12:32 +0000 (14:12 +1000)]
drm/gk104/gpio: fix incorrect interrupt register usage

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/core: punt all object state change messages to trace level
Ben Skeggs [Fri, 16 May 2014 03:52:19 +0000 (13:52 +1000)]
drm/nouveau/core: punt all object state change messages to trace level

Leave debug for the more interesting bits of info.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/clk: allow end-user reclocking for nv40, nvaa, and nve0 clock types
Ilia Mirkin [Sun, 18 May 2014 05:04:16 +0000 (01:04 -0400)]
drm/nouveau/clk: allow end-user reclocking for nv40, nvaa, and nve0 clock types

Use with caution.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/fb: default NvMemExec to on, turning it off is used for debugging only
Ilia Mirkin [Sun, 18 May 2014 05:04:15 +0000 (01:04 -0400)]
drm/nouveau/fb: default NvMemExec to on, turning it off is used for debugging only

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function
Martin Peres [Thu, 3 Apr 2014 20:12:41 +0000 (22:12 +0200)]
drm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: bump the i2c delay for the adt7473
Martin Peres [Sun, 25 May 2014 22:42:13 +0000 (00:42 +0200)]
drm/nouveau/i2c: bump the i2c delay for the adt7473

Some adt7473 can't manage the 20µs delay we use for the bitbanging, bumping
it to 40µs seem to do the trick.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Tested-by: Marcel Dopita <mdop@seznam.cz>
10 years agodrm/nouveau/therm/fan/tach: default to 2 pulses per revolution
Martin Peres [Mon, 12 May 2014 21:19:07 +0000 (23:19 +0200)]
drm/nouveau/therm/fan/tach: default to 2 pulses per revolution

I spent some time this weekend trying to find in the vbios the number of
pulses per revolutions in the vbios but couldn't find it. It would seem
all my cards have 2 pulses per revolution so let's stick to that until
further notice.

Thermal table's id 0x48 may indicate this information but it would seem
that changing the value results in the blob power or clock gating the
RPM counter... We should ask NVIDIA about that, should be trivial-enough
for them to answer.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nvf0/device: enable video decoding engines on gk110/gk208
John Rowley [Mon, 12 May 2014 21:34:57 +0000 (21:34 +0000)]
drm/nvf0/device: enable video decoding engines on gk110/gk208

Only tested on nvf1, was advised to enable on all.

Signed-off-by: John Rowley <john.rowley08@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nvf1/device: add support for 0xf1 (gk110b)
John Rowley [Mon, 12 May 2014 21:34:56 +0000 (21:34 +0000)]
drm/nvf1/device: add support for 0xf1 (gk110b)

Signed-off-by: John Rowley <john.rowley08@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/device: support for probing GK20A
Alexandre Courbot [Fri, 2 May 2014 09:32:42 +0000 (18:32 +0900)]
drm/nouveau/device: support for probing GK20A

Set the correct subdev/engine classes when GK20A (0xea) is probed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/graph: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:41 +0000 (18:32 +0900)]
drm/nouveau/graph: add GK20A support

Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).

Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/graph: pad firmware code at load time
Alexandre Courbot [Fri, 2 May 2014 09:32:40 +0000 (18:32 +0900)]
drm/nouveau/graph: pad firmware code at load time

Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/graph: enable when using external fw
Alexandre Courbot [Fri, 2 May 2014 09:32:39 +0000 (18:32 +0900)]
drm/nouveau/graph: enable when using external fw

nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.

Relax the conditions enabling the GR engine to also include the case
where an external firmware has also been loaded.

Also switch to external firmware if the graph class has no microcode
linked to it.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/fifo: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:38 +0000 (18:32 +0900)]
drm/nouveau/fifo: add GK20A support

GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/fb: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:37 +0000 (18:32 +0900)]
drm/nouveau/fb: add GK20A support

Add a simple FB device for GK20A, as well as a RAM implementation
suitable for chips that use system memory as video RAM.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/ibus: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:36 +0000 (18:32 +0900)]
drm/nouveau/ibus: add GK20A support

Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nvc0/bar: support chips without BAR3
Alexandre Courbot [Fri, 2 May 2014 09:32:35 +0000 (18:32 +0900)]
drm/nvc0/bar: support chips without BAR3

Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/bar: only ioremap BAR3 if it exists
Alexandre Courbot [Fri, 2 May 2014 09:32:34 +0000 (18:32 +0900)]
drm/nouveau/bar: only ioremap BAR3 if it exists

Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/doc: Fix nouveau typo
Damien Lespiau [Mon, 9 Jun 2014 13:40:35 +0000 (14:40 +0100)]
drm/doc: Fix nouveau typo

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agoMerge tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into...
Dave Airlie [Mon, 9 Jun 2014 22:53:00 +0000 (08:53 +1000)]
Merge tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/panel: Changes for v3.16-rc1

This set of commits contains a couple of fixes to existing panel drivers
and support for some new panels.

One commit touches the DRM core in that in modifies the MIPI DSI support
to hook up the shutdown function so that drivers can provide code that's
run on shutdown. This is used by a subsequent commit to make the simple
panel driver power off the backlight on shutdown.

* tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/panel: simple - Add AUO B133XTN01 panel support
  drm/panel: simple - Disable panel on shutdown
  drm/panel: add support for EDT ET057090DHU panel
  drm/panel: Add support for EDT ETM0700G0DH6 and ET070080DH6 panels
  drm/panel: ld9040: add power control sequence
  drm/panel: s6e8aa0: silence array overflow warning
  drm/dsi: Support device shutdown

10 years agoMerge tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into...
Dave Airlie [Mon, 9 Jun 2014 22:51:19 +0000 (08:51 +1000)]
Merge tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v3.16-rc1

The majority of these changes are a slew of cleanups across the board.
A more noteworthy change is the addition of drm_dev_set_unique() and the
conversion of the Tegra DRM driver to use it. This allows us to get rid
of the host1x drm_bus implementation. Other USB and platform drivers can
be changed in a similar way. Unfortunately for most PCI devices there is
some userspace that relies on the old functionality and cannot be as
easily converted.

HDMI and hardware cursor support is added for Tegra124. The SOR output
gains support for exposing CRCs via debugfs, which can be used for
automated testing. Many values that were hardcoded in the SOR/eDP code
are now computed at runtime to increase compatibility with more devices.

* tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: (47 commits)
  drm/tegra: sor - Remove obsolete comment
  drm/tegra: sor - Enable only the necessary number of lanes
  drm/tegra: sor - Power on only the necessary lanes
  drm/tegra: sor - Do not program interlaced mode registers
  drm/tegra: sor - Do not hardcode link speed
  drm/tegra: sor - Do not hardcode number of blank symbols
  drm/tegra: sor - Don't hardcode link parameters
  drm/tegra: sor - Change power down ordering
  drm/tegra: sor - Fix copy/paste error
  drm/tegra: sor - Remove pixel clock rounding
  drm/tegra: sor - Make debugfs setup consistent
  drm/tegra: sor - Recursively remove debugfs tree
  drm/tegra: dp - Mark the connector as hotplug capable
  drm/tegra: dp - Implement hotplug detection in work queue
  drm/tegra: Add hardware cursor support
  drm/tegra: Remove host1x drm_bus implementation
  drm: Document how to register devices without struct drm_bus
  drm: Add device registration documentation
  drm: Introduce drm_dev_set_unique()
  gpu: host1x: Rename internal functions for clarity
  ...

10 years agodrm/panel: simple - Add AUO B133XTN01 panel support
Stéphane Marchesin [Sat, 24 May 2014 02:27:59 +0000 (19:27 -0700)]
drm/panel: simple - Add AUO B133XTN01 panel support

This panel is used by nyan-big and can be supported by the simple-panel
driver.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
[treding@nvidia.com: add device tree binding document]
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Remove obsolete comment
Thierry Reding [Thu, 5 Jun 2014 14:20:27 +0000 (16:20 +0200)]
drm/tegra: sor - Remove obsolete comment

According to the DP specification the disparity of the first symbol
should always be negative. It is therefore safe to assume that panels
will conform to that and therefore parameterizing this field should
never be necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Enable only the necessary number of lanes
Thierry Reding [Thu, 5 Jun 2014 14:29:46 +0000 (16:29 +0200)]
drm/tegra: sor - Enable only the necessary number of lanes

Instead of always enabling all four lanes, enable only the number probed
from the link.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Power on only the necessary lanes
Thierry Reding [Thu, 5 Jun 2014 14:19:48 +0000 (16:19 +0200)]
drm/tegra: sor - Power on only the necessary lanes

Power on only those lanes required for the specified link.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Do not program interlaced mode registers
Thierry Reding [Thu, 5 Jun 2014 14:17:25 +0000 (16:17 +0200)]
drm/tegra: sor - Do not program interlaced mode registers

Interlaced mode is currently not supported on the SOR, so don't program
any associated registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Do not hardcode link speed
Thierry Reding [Thu, 5 Jun 2014 14:16:23 +0000 (16:16 +0200)]
drm/tegra: sor - Do not hardcode link speed

Use the speed probed from the link at runtime rather than relying on a
hardcoded default.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Do not hardcode number of blank symbols
Thierry Reding [Thu, 5 Jun 2014 14:12:46 +0000 (16:12 +0200)]
drm/tegra: sor - Do not hardcode number of blank symbols

The number of HBLANK and VBLANK symbols can be computed at runtime so
that they can be set appropriately depending on the video mode and DP
link.

These values are used by the packet generation logic to determine how
many audio samples can be transferred during the blanking intervals.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Don't hardcode link parameters
Thierry Reding [Thu, 5 Jun 2014 14:31:10 +0000 (16:31 +0200)]
drm/tegra: sor - Don't hardcode link parameters

The currently hardcoded link parameters don't work on all eDP panels, so
compute the parameters at runtime depending on the mode and panel type
to allow the driver to cope with a wider variety of panels.

Note that the number of bits per pixel of the panel is still hardcoded,
but this can be addressed in a separate patch.

This is largely based on a patch by Stéphane Marchesin but the algorithm
was largely rewritten to be more readable and concise.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Change power down ordering
Stéphane Marchesin [Fri, 23 May 2014 03:32:48 +0000 (20:32 -0700)]
drm/tegra: sor - Change power down ordering

Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Fix copy/paste error
Stéphane Marchesin [Fri, 23 May 2014 03:32:47 +0000 (20:32 -0700)]
drm/tegra: sor - Fix copy/paste error

The comment above mentions link A/B but this isn't what the code does,
so let's fix that.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Remove pixel clock rounding
Stéphane Marchesin [Fri, 23 May 2014 03:32:46 +0000 (20:32 -0700)]
drm/tegra: sor - Remove pixel clock rounding

The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agoMerge tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel...
Dave Airlie [Fri, 6 Jun 2014 09:07:09 +0000 (19:07 +1000)]
Merge tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel into drm-next

> Bunch of stuff for 3.16 still:
> - Mipi dsi panel support for byt. Finally! From Shobhit&others. I've
>   squeezed this in since it's a regression compared to vbios and we've
>   been ridiculed about it a bit too often ...
> - connection_mutex deadlock fix in get_connector (only affects i915).
> - Core patches from Matt's primary plane from Matt Roper, I've pushed the
>   i915 stuff to 3.17.
> - vlv power well sequencing fixes from Jesse.
> - Fix for cursor size changes from Chris.
> - agpbusy fixes from Ville.
> - A few smaller things.
>

* tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel: (32 commits)
  drm/i915: BDW: Adding missing cursor offsets.
  drm: Fix getconnector connection_mutex locking
  drm/i915/bdw: Only use 2g GGTT for 32b platforms
  drm/i915: Nuke pipe A quirk on i830M
  drm/i915: fix display power sw state reporting
  drm/i915: Always apply cursor width changes
  drm/i915: tell the user if both KMS and UMS are disabled
  drm/plane-helper: Add drm_plane_helper_check_update() (v3)
  drm: Check CRTC compatibility in setplane
  drm/i915: use VBT to determine whether to enumerate the VGA port
  drm/i915: Don't WARN about ring idle bit on gen2
  drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object
  drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS
  drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
  drm/i915: Flip the sense of AGPBUSY_DIS bit
  drm/i915: Set AGPBUSY# bit in init_clock_gating
  drm/i915/vlv: add pll assertion when disabling DPIO common well
  drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well
  drm/i915/vlv: re-order power wells so DPIO common comes after TX
  drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well
  ...

10 years agodrm/tegra: sor - Make debugfs setup consistent
Thierry Reding [Wed, 28 May 2014 11:46:12 +0000 (13:46 +0200)]
drm/tegra: sor - Make debugfs setup consistent

Other output drivers set up debugfs slightly differently. Bring the SOR
driver in line with those for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Recursively remove debugfs tree
Thierry Reding [Fri, 25 Apr 2014 14:48:36 +0000 (16:48 +0200)]
drm/tegra: sor - Recursively remove debugfs tree

Removing only the root directory will fail when there are still files in
it. Instead of manually removing all files, remove the whole directory
recursively.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dp - Mark the connector as hotplug capable
Thierry Reding [Fri, 25 Apr 2014 14:44:48 +0000 (16:44 +0200)]
drm/tegra: dp - Mark the connector as hotplug capable

Doing so allows the hotplug events generated by the connector to be
properly handled by the DRM poll helpers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dp - Implement hotplug detection in work queue
Thierry Reding [Fri, 25 Apr 2014 14:42:32 +0000 (16:42 +0200)]
drm/tegra: dp - Implement hotplug detection in work queue

Calling the drm_helper_hpd_irq_event() helper can sleep, so instead of
invoking it directly from the interrupt handler, schedule a work queue
and run it from there.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: Add hardware cursor support
Thierry Reding [Fri, 20 Dec 2013 12:58:33 +0000 (13:58 +0100)]
drm/tegra: Add hardware cursor support

Enable hardware cursor support on Tegra124. Earlier generations support
the hardware cursor to some degree as well, but not in a way that can be
generically exposed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: Remove host1x drm_bus implementation
Thierry Reding [Thu, 22 May 2014 07:57:15 +0000 (09:57 +0200)]
drm/tegra: Remove host1x drm_bus implementation

The DRM core can now cope with drivers that don't have an associated
struct drm_bus, so the host1x implementation is no longer useful.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm: Document how to register devices without struct drm_bus
Thierry Reding [Wed, 23 Apr 2014 09:52:10 +0000 (11:52 +0200)]
drm: Document how to register devices without struct drm_bus

With the recent addition of the drm_set_unique() function, devices can
now be registered without requiring a drm_bus. Add a brief description
to the DRM docbook to show how that can be achieved.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm: Add device registration documentation
Thierry Reding [Mon, 19 May 2014 11:39:07 +0000 (13:39 +0200)]
drm: Add device registration documentation

Describe how devices are registered using the drm_*_init() functions.
Adding this to docbook requires a largish set of changes to the comments
in drm_{pci,usb,platform}.c since they are doxygen-style rather than
proper kernel-doc and therefore mess with the docbook generation.

While at it, mark usage of drm_put_dev() as discouraged in favour of
calling drm_dev_unregister() and drm_dev_unref() directly.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm: Introduce drm_dev_set_unique()
Thierry Reding [Fri, 11 Apr 2014 13:23:00 +0000 (15:23 +0200)]
drm: Introduce drm_dev_set_unique()

Add a helper function that allows drivers to statically set the unique
name of the device. This will allow platform and USB drivers to get rid
of their DRM bus implementations and directly use drm_dev_alloc() and
drm_dev_register().

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agogpu: host1x: Rename internal functions for clarity
Thierry Reding [Thu, 22 May 2014 09:12:17 +0000 (11:12 +0200)]
gpu: host1x: Rename internal functions for clarity

The internal host1x_{,un}register_client() functions can potentially be
confused with public the host1x_client_{,un}register() functions.

Rename them to host1x_{add,del}_client() to remove some of the possible
confusion.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: gem - Make tegra_bo_import() static
Thierry Reding [Tue, 13 May 2014 14:46:11 +0000 (16:46 +0200)]
drm/tegra: gem - Make tegra_bo_import() static

The function is never used outside of the source file and therefore can
be locally scoped.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Add Tegra124 support
Thierry Reding [Fri, 15 Nov 2013 15:07:32 +0000 (16:07 +0100)]
drm/tegra: hdmi - Add Tegra124 support

Tegra124 is mostly backwards-compatible with Tegra114. However, Tegra124
supports a few more features (e.g. interlacing, ...). Introduce a new
compatible string and TMDS tables to cope with these differences.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Protect CRC debugfs against enable state
Thierry Reding [Wed, 26 Mar 2014 10:13:16 +0000 (11:13 +0100)]
drm/tegra: sor - Protect CRC debugfs against enable state

Accessing the CRC debugfs file will hang the system if the SOR is not
enabled, so make sure that it is stays enabled until the CRC has been
read.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Do not needlessly recompute pclk
Thierry Reding [Fri, 14 Mar 2014 13:20:42 +0000 (14:20 +0100)]
drm/tegra: dsi - Do not needlessly recompute pclk

In some cases the pixel clock used to not be correct, which is why it
had to be recomputed. It turns out that the reason why it wasn't correct
is that it was used wrongly. If used correctly there's not need for the
recomputation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Compute shift clock divider in output drivers
Thierry Reding [Wed, 26 Mar 2014 12:32:21 +0000 (13:32 +0100)]
drm/tegra: dc - Compute shift clock divider in output drivers

The shift clock divider is highly dependent on the type of output, so
push computation of it down into the output drivers. The old code used
to work merely by accident.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Move around shift clock programming
Thierry Reding [Wed, 26 Mar 2014 11:32:14 +0000 (12:32 +0100)]
drm/tegra: dc - Move around shift clock programming

Program the shift clock divider in tegra_crtc_setup_clk() since that's
where the divider is computed, so passing it around can be avoided.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Reset controller on driver unload
Thierry Reding [Fri, 14 Mar 2014 13:25:43 +0000 (14:25 +0100)]
drm/tegra: dsi - Reset controller on driver unload

Assert the DSI controller's reset when the driver is unloaded to reduce
power consumption and to put the controller into a known state for
subsequent driver reloads.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Fix typo when disabling controller
Thierry Reding [Fri, 14 Mar 2014 13:19:17 +0000 (14:19 +0100)]
drm/tegra: dsi - Fix typo when disabling controller

When disabling the DSI controller, the code wasn't really doing what it
was supposed to.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Add enable guard
Thierry Reding [Fri, 14 Mar 2014 13:15:10 +0000 (14:15 +0100)]
drm/tegra: dsi - Add enable guard

To prevent the enable or disable operations to potentially be run
multiple times, add guards to return early when the output is already
in the targetted state.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Initialize proper packet sequences
Thierry Reding [Fri, 14 Mar 2014 13:13:15 +0000 (14:13 +0100)]
drm/tegra: dsi - Initialize proper packet sequences

The packet sequencer needs to be programmed depending on the video mode
of the attached peripheral. Add support for non-burst video modes with
sync events (as opposed to sync pulses) and select either sequence
depending on the video mode.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Implement VDD supply support
Thierry Reding [Fri, 14 Mar 2014 13:07:50 +0000 (14:07 +0100)]
drm/tegra: dsi - Implement VDD supply support

The DSI controllers are powered by a (typically 1.2V) regulator. Usually
this is always on, so there was no need to support enabling or disabling
it thus far. But in order not to consume any power when DSI is inactive,
give the driver a chance to enable or disable the supply as needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Remove unneeded code
Thierry Reding [Fri, 14 Mar 2014 13:02:28 +0000 (14:02 +0100)]
drm/tegra: dsi - Remove unneeded code

A bunch of registers are initialized to 0 upon during driver probe. It
turns out that none of these are actually needed, so they can simply be
dropped.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dsi - Use internal pixel format
Thierry Reding [Thu, 13 Mar 2014 07:50:39 +0000 (08:50 +0100)]
drm/tegra: dsi - Use internal pixel format

The pixel format enumeration values used by the Tegra DSI controller
don't match those defined by the DSI framework. Make sure to convert
them to the internal format before writing it to the register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Fix disable sequence
Thierry Reding [Wed, 16 Apr 2014 08:55:25 +0000 (10:55 +0200)]
drm/tegra: hdmi - Fix disable sequence

For some reason when the PW*_ENABLE and PM*_ENABLE fields are cleared
during disable, the HDMI output stops working properly. Resetting and
initializing doesn't help.

Comment out those accesses for now until it has been determined what to
do about them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Disable LVDS mode
Thierry Reding [Wed, 16 Apr 2014 08:47:36 +0000 (10:47 +0200)]
drm/tegra: hdmi - Disable LVDS mode

Disable LVDS mode according to register documentation. It seems like
this has no effect on the operation of HDMI, but it's probably a good
idea to do this anyway.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Use proper power-up sequence
Thierry Reding [Wed, 16 Apr 2014 08:46:24 +0000 (10:46 +0200)]
drm/tegra: hdmi - Use proper power-up sequence

This reflects the power-up sequence as described in the documentation,
but it doesn't seem to be strictly necessary to get HDMI to work.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Clean up clock usage
Thierry Reding [Wed, 16 Apr 2014 08:43:41 +0000 (10:43 +0200)]
drm/tegra: hdmi - Clean up clock usage

Clocks are never enabled or disabled in atomic context, so we can use
the clk_prepare_enable() and clk_disable_unprepare() helpers instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Reverse regulator enable ordering
Thierry Reding [Wed, 16 Apr 2014 08:24:12 +0000 (10:24 +0200)]
drm/tegra: hdmi - Reverse regulator enable ordering

Schematics indicate that the AVDD_HDMI_PLL supply should be enabled
prior to the AVDD_HDMI supply.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Remove duplicate code
Thierry Reding [Wed, 26 Mar 2014 11:21:25 +0000 (12:21 +0100)]
drm/tegra: hdmi - Remove duplicate code

The generic Tegra output code already sets up the clocks properly, so
there's no need to do it again when the HDMI output is enabled.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: hdmi - Add connector supply support
Thierry Reding [Fri, 28 Feb 2014 15:57:34 +0000 (16:57 +0100)]
drm/tegra: hdmi - Add connector supply support

Revert commit 18ebc0f404d5 "drm/tegra: hdmi: Enable VDD earlier for
hotplug/DDC" and instead add a new supply for the +5V pin on the HDMI
connector.

The vdd-supply property refers to the regulator that supplies the
AVDD_HDMI input on Tegra, rather than the +5V HDMI connector pin. This
was never a problem before, because all boards had that pin hooked up to
a regulator that was always on. Starting with Dalmore and continuing
with Venice2, the +5V pin is controllable via a GPIO. For reasons
unknown, the GPIO ended up as the controlling GPIO of the AVDD_HDMI
supply in the Dalmore and Venice2 DTS files. But that's not correct.
Instead, a separate supply must be introduced so that the +5V pin can be
controlled separately from the supplies that feed the HDMI block within
Tegra.

A new hdmi-supply property is introduced that takes the place of the
vdd-supply and vdd-supply is only enabled when HDMI is enabled rather
than all the time.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Use proper H/V ref-to-sync values
Thierry Reding [Wed, 16 Apr 2014 07:22:38 +0000 (09:22 +0200)]
drm/tegra: dc - Use proper H/V ref-to-sync values

For HDMI compliance both of these values need to be set to 1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Do not touch power control register
Thierry Reding [Wed, 16 Apr 2014 07:52:31 +0000 (09:52 +0200)]
drm/tegra: dc - Do not touch power control register

Setting the bits in this register is dependent on the output type driven
by the display controller. All output drivers already set these properly
so there is no need to do it here again.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Reshuffle code to get rid of prototypes
Thierry Reding [Fri, 14 Mar 2014 08:54:58 +0000 (09:54 +0100)]
drm/tegra: dc - Reshuffle code to get rid of prototypes

The tegra_dc_format() and tegra_dc_setup_window() functions are only
used internally by the display controller driver. Move them upwards in
order to make them static and get rid of the function prototypes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Rename INVERT_V to V_DIRECTION
Thierry Reding [Tue, 25 Feb 2014 11:04:06 +0000 (12:04 +0100)]
drm/tegra: dc - Rename INVERT_V to V_DIRECTION

V_DIRECTION is the name of the field in the documentation, so use that
for consistency. Also add the H_DIRECTION field for completeness.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: sor - Add CRC debugfs support
Thierry Reding [Fri, 31 Jan 2014 09:02:15 +0000 (10:02 +0100)]
drm/tegra: sor - Add CRC debugfs support

The SOR allows the computation of a 32 bit CRC of the content that it
transmits. This functionality is exposed via debugfs and is useful to
verify proper operation of the SOR.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: dc - Add YUYV support
Thierry Reding [Wed, 29 Jan 2014 19:31:17 +0000 (20:31 +0100)]
drm/tegra: dc - Add YUYV support

YUYV is UYVY with swapped bytes. Luckily the Tegra DC hardware can swap
bytes during scan-out, so supporting YUYV is simply a matter of writing
the correct value to the byteswap register.

This patch modifies tegra_dc_format() to return the byte swap parameter
via an output parameter in addition to returning the pixel format. Many
other formats can potentially be supported in a similar way.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/tegra: Cleanup header file
Thierry Reding [Wed, 16 Apr 2014 07:54:21 +0000 (09:54 +0200)]
drm/tegra: Cleanup header file

Remove extern keyword from function prototypes since it isn't needed and
drop an unnecessary forward declaration.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm: Fix getconnector connection_mutex locking
Daniel Vetter [Thu, 5 Jun 2014 09:12:03 +0000 (11:12 +0200)]
drm: Fix getconnector connection_mutex locking

I've fumbled my own idea and enthusiastically wrapped all the
getconnector code with the connection_mutex. But we only need it to
chase the connector->encoder link. Even there it's not really needed
since races with userspace won't matter, but better paranoid and
consistent about this stuff.

If we grap it everywhere connector probe callbacks can't grab it
themselves, which means they'll deadlock. i915 does that for the load
detect pipe. Furthermore i915 needs to do a ww dance since we also
need to grab the mutex of the load detect crtc.

This is a regression from

commit 6e9f798d91c526982cca0026cd451e8fdbf18aaf
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu May 29 23:54:47 2014 +0200

    drm: Split connection_mutex out of mode_config.mutex (v3)

Cc: Rob Clark <robdclark@gmail.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
10 years agodrm/panel: simple - Disable panel on shutdown
Thierry Reding [Tue, 29 Apr 2014 15:21:21 +0000 (17:21 +0200)]
drm/panel: simple - Disable panel on shutdown

When a device is shut down, disable the panel to make sure the display
backlight doesn't stay lit.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/panel: add support for EDT ET057090DHU panel
Stefan Agner [Thu, 15 May 2014 09:38:45 +0000 (11:38 +0200)]
drm/panel: add support for EDT ET057090DHU panel

This panel is sold by Toradex for Colibri T20/T30 and Apalis T30
evaluation kits.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/panel: Add support for EDT ETM0700G0DH6 and ET070080DH6 panels
Philipp Zabel [Thu, 15 May 2014 10:25:47 +0000 (12:25 +0200)]
drm/panel: Add support for EDT ETM0700G0DH6 and ET070080DH6 panels

The EDT ETM0700G0DH6 and ET070080DH6 are 7" 800x480 panels,
which can be supported by the simple panel driver.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/panel: ld9040: add power control sequence
Andrzej Hajda [Tue, 8 Apr 2014 10:58:05 +0000 (12:58 +0200)]
drm/panel: ld9040: add power control sequence

Some ld9040 panels do not start without providing power control sequence
during initialization. The patch fixes the driver by providing such
sequence for all panels.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/panel: s6e8aa0: silence array overflow warning
Dan Carpenter [Wed, 9 Apr 2014 15:21:12 +0000 (18:21 +0300)]
drm/panel: s6e8aa0: silence array overflow warning

Smatch complains that we are reading beyond the end of the array here:

drivers/gpu/drm/panel/panel-s6e8aa0.c:852 s6e8aa0_read_mtp_id()
warn: buffer overflow 's6e8aa0_variants' 4 <= 4

We set the error code, so it's not harmful but it looks like a return
was intended here so lets add that and silence the warning.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/dsi: Support device shutdown
Thierry Reding [Tue, 29 Apr 2014 15:19:57 +0000 (17:19 +0200)]
drm/dsi: Support device shutdown

Hook up the MIPI DSI bus's .shutdown() function to allow drivers to
implement code that should be run when a device is shut down.

Signed-off-by: Thierry Reding <treding@nvidia.com>
10 years agodrm/i915: BDW: Adding missing cursor offsets.
Rodrigo Vivi [Thu, 5 Jun 2014 00:09:30 +0000 (17:09 -0700)]
drm/i915: BDW: Adding missing cursor offsets.

BDW uses IVB cursor offsets.

Whithout this patch it is not possible to use multiple outputs with cursor
on BDW.
The cursor gets completely crazy because update position uses the wrong
cursor register for the second pipe.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: stable@vger.kernel.org
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79621
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Fix getconnector connection_mutex locking
Daniel Vetter [Thu, 5 Jun 2014 09:07:20 +0000 (11:07 +0200)]
drm: Fix getconnector connection_mutex locking

I've fumbled my own idea and enthusiastically wrapped all the
getconnector code with the connection_mutex. But we only need it to
chase the connector->encoder link. Even there it's not really needed
since races with userspace won't matter, but better paranoid and
consistent about this stuff.

If we grap it everywhere connector probe callbacks can't grab it
themselves, which means they'll deadlock. i915 does that for the load
detect pipe. Furthermore i915 needs to do a ww dance since we also
need to grab the mutex of the load detect crtc.

This is a regression from

commit 6e9f798d91c526982cca0026cd451e8fdbf18aaf
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu May 29 23:54:47 2014 +0200

    drm: Split connection_mutex out of mode_config.mutex (v3)

Cc: Rob Clark <robdclark@gmail.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agoMerge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-next
Dave Airlie [Thu, 5 Jun 2014 10:28:59 +0000 (20:28 +1000)]
Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-next

Merge drm-fixes into drm-next.

Both i915 and radeon need this done for later patches.

Conflicts:
drivers/gpu/drm/drm_crtc_helper.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_gem_gtt.c

10 years agodrm/i915/bdw: Only use 2g GGTT for 32b platforms
Ben Widawsky [Tue, 27 May 2014 23:53:08 +0000 (16:53 -0700)]
drm/i915/bdw: Only use 2g GGTT for 32b platforms

Daniel requested in the bug that I use a 3GB fallback size. Since this
is not in the spec as a valid size, I decided against it. We could
potentially add a patch to bump it to 3GB on top of this one.

This probably should be CC: stable - but I'll let the powers that be
decide that one.

Regression from a revert of the revert:
commit 7907f45bf9f67a1c5e5d4ae05bab428d7c2f43b2
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Wed Feb 19 22:05:46 2014 -0800

    Revert "drm/i915/bdw: Limit GTT to 2GB"

v2: Change ifdef to 32b, instead of ifndef
update comment

v3. Update comment to not wrap (Daniel).
Update commit message

v4: s/CONFIG_32/CONFIG_X86_32 (Jani).

v5: s/CONFIG_x86_32BIT/CONFIG_x86_32, as meant in v4
s/32B/32b (chris)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76619
Cc: stable@vger.kernel.org
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: "Yang, Guang A" <guang.a.yang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Nuke pipe A quirk on i830M
Daniel Vetter [Mon, 2 Jun 2014 15:57:18 +0000 (17:57 +0200)]
drm/i915: Nuke pipe A quirk on i830M

Apparently it does more harm than good. Thomas Richter reports that
it helps his machine (Thinkpad X31) and there's another report from a
Fujitsu S6010. Also, we've nuked it on i845G already to make Chris'
machine happy.

Cc: Thomas Richter <richter@rus.uni-stuttgart.de>
References: http://mid.mail-archive.com/538C54E0.8090507@rus.uni-stuttgart.de
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: fix display power sw state reporting
Imre Deak [Mon, 2 Jun 2014 11:21:10 +0000 (14:21 +0300)]
drm/i915: fix display power sw state reporting

Atm, we refcount both power domains and power wells and
intel_display_power_enabled_sw() returns the power domain refcount. What
the callers are really interested in though is the sw state of the
underlying power wells. Due to this we will report incorrectly that a
given power domain is off if its power wells were enabled via another
power domain, for example POWER_DOMAIN_INIT which enables all power
wells.

As a fix return instead the state based on the refcount of all power
wells included in the passed in power domain.

References: https://bugs.freedesktop.org/show_bug.cgi?id=79505
References: https://bugs.freedesktop.org/show_bug.cgi?id=79038
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Always apply cursor width changes
Chris Wilson [Fri, 30 May 2014 13:35:26 +0000 (16:35 +0300)]
drm/i915: Always apply cursor width changes

It is possible for userspace to create a big object large enough for a
256x256, and then switch over to using it as a 64x64 cursor. This
requires the cursor update routines to check for a change in width on
every update, rather than just when the cursor is originally enabled.

This also fixes an issue with 845g/865g which cannot change the base
address of the cursor whilst it is active.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[Antti:rebased, adjusted macro names and moved some lines, no functional
changes]
Reviewed-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Tested-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Cc: stable@vger.kernel.org
Testcase: igt/kms_cursor_crc/cursor-size-change
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: tell the user if both KMS and UMS are disabled
Jani Nikula [Mon, 2 Jun 2014 13:58:30 +0000 (16:58 +0300)]
drm/i915: tell the user if both KMS and UMS are disabled

If both KMS is disabled (by i915.modeset=0 or nomodeset parameters) and
UMS is disabled (by CONFIG_DRM_I915_UMS=n, the default), the user might
not be aware his setup is not supported. Inform the users (and, by
extension, the poor i915 developers having to read their dmesgs in bug
reports) why their graphics experience might be lacking.

A similar message was added on the UMS path in
commit e147accbd19f55489dabdcc4dc3551cc3e3f2553
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Thu Oct 10 15:25:37 2013 +0300

    drm/i915: tell the user KMS is required for gen6+

but it won't be reached if CONFIG_DRM_I915_UMS=n since
commit b30324adaf8d2e5950a602bde63030d15a61826f
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Nov 13 22:11:25 2013 +0100

    drm/i915: Deprecated UMS support

v2: Use DRM_DEBUG_DRIVER.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/plane-helper: Add drm_plane_helper_check_update() (v3)
Matt Roper [Thu, 29 May 2014 15:06:52 +0000 (08:06 -0700)]
drm/plane-helper: Add drm_plane_helper_check_update() (v3)

Pull the parameter checking from drm_primary_helper_update() out into
its own function; drivers that provide their own setplane()
implementations rather than using the helper may still want to share
this parameter checking logic.

A few of the checks here were also updated based on suggestions by
Ville Syrjälä.

v3:
 - s/primary_helper/plane_helper/ --- this checking logic may be useful
   for other types of planes as well.
 - Fix visibility check (need to dereference visibility pointer)
v2:
 - Pass src/dest/clip rects and min/max scaling down to helper to avoid
   duplication of effort between helper and drivers (suggested by
   Ville).
 - Allow caller to specify whether the primary plane should be
   updatable while the crtc is disabled.

Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
[danvet: Include header properly and fixup declaration mismatch to
make this compile.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm: Check CRTC compatibility in setplane
Matt Roper [Thu, 29 May 2014 15:06:51 +0000 (08:06 -0700)]
drm: Check CRTC compatibility in setplane

The DRM core setplane code should check that the plane is usable on the
specified CRTC before calling into the driver.

Prior to this patch, a plane's possible_crtcs field was purely
informational for userspace and was never actually verified at the
kernel level (aside from the primary plane helper).

Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: use VBT to determine whether to enumerate the VGA port
Jesse Barnes [Fri, 4 Apr 2014 23:12:07 +0000 (16:12 -0700)]
drm/i915: use VBT to determine whether to enumerate the VGA port

Some platforms may not have it, and enumerating it is both confusing and
time consuming due to the hotplug and DDC probing.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>