GitHub/exynos8895/android_kernel_samsung_universal8895.git
10 years agodrm/i915: Drop the excessive vblank waits from modeset codepaths
Ville Syrjälä [Fri, 25 Apr 2014 10:30:12 +0000 (13:30 +0300)]
drm/i915: Drop the excessive vblank waits from modeset codepaths

Now that we've plugged the mmio vs. ring flip race, we shouldn't need
these vblank waits in the modeset codepaths anymore. So get rid of
them.

v2: gen2 needs to wait for planes to turn off before disabling pipe

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Wait for vblank in hsw_enable_ips()
Ville Syrjälä [Tue, 15 Apr 2014 18:41:35 +0000 (21:41 +0300)]
drm/i915: Wait for vblank in hsw_enable_ips()

Now that the vblank wait is gone from intel_enable_primary_plane(),
hsw_enable_ips() needs to do the vblank wait itself.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix mmio vs. CS flip race on ILK+
Ville Syrjälä [Tue, 15 Apr 2014 18:41:34 +0000 (21:41 +0300)]
drm/i915: Fix mmio vs. CS flip race on ILK+

Starting from ILK, mmio flips also cause a flip done interrupt to be
signalled. This means if we first do a set_base and follow it
immediately with the CS flip, we might mistake the flip done interrupt
caused by the set_base as the flip done interrupt caused by the CS
flip.

The hardware has a flip counter which increments every time a mmio or
CS flip is issued. It basically counts the number of DSPSURF register
writes. This means we can sample the counter before we put the CS
flip into the ring, and then when we get a flip done interrupt we can
check whether the CS flip has actually performed the surface address
update, or if the interrupt was caused by a previous but yet
unfinished mmio flip.

Even with the flip counter we still have a race condition of the CS flip
base address update happens after the mmio flip done interrupt was
raised but not yet processed by the driver. When the interrupt is
eventually processed, the flip counter will already indicate that the
CS flip has been executed, but it would not actually complete until the
next start of vblank. We can use the DSPSURFLIVE register to check
whether the hardware is actually scanning out of the buffer we expect,
or if we managed hit this race window.

This covers all the cases where the CS flip actually changes the base
address. If the base address remains unchanged, we might still complete
the CS flip before it has actually completed. But since the address
didn't change anyway, the premature flip completion can't result in
userspace overwriting data that's still being scanned out.

CTG already has the flip counter and DSPSURFLIVE registers, and
although the flip done interrupt is still limited to CS flips alone,
the code now also checks the flip counter on CTG as well.

v2: s/dspsurf/gtt_offset/ (Chris)

Testcase: igt/kms_mmio_vs_cs_flip/setcrtc_vs_cs_flip
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73027
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Add g4x_ prefix to flip_count_after_eq.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: drop encoder hot_plug calls at resume
Jesse Barnes [Tue, 20 May 2014 22:25:33 +0000 (15:25 -0700)]
drm/i915: drop encoder hot_plug calls at resume

We really just want to go detect displays again and fire off a hotplug
event if things have changed, not go through full hotplug processing.

Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Drop now misleading DDI comment from dp_link_down
Daniel Vetter [Tue, 20 May 2014 20:46:50 +0000 (22:46 +0200)]
drm/i915: Drop now misleading DDI comment from dp_link_down

Since

commit 2e82a7203182d0883d0f9450d40ad6e1c6578ad9
Author: Imre Deak <imre.deak@intel.com>
Date:   Fri Jan 17 15:46:43 2014 +0200

    drm/i915: don't disable DP port after a failed link training

and

commit 5d6a1116c6475404e6505b708320f9579ae19acd
Author: Imre Deak <imre.deak@intel.com>
Date:   Thu Jan 16 18:35:57 2014 +0200

    drm/i915: don't disable the DP port if the link is lost

we no longer call intel_dp_link_down from generic DP code, but only
from the !HAS_DDI dp encoder functions. hsw/bdw have their own encoder
disabling callback in intel_ddi.c.

Hence the early return is no longer needed and the big comment just
confusing, so let's rip it out. To ensure what we don't accidentally
use this again on ddi encoders add a WARN_ON instead.

Spotted while reading through intel_dp.c

Cc: Imre Deak <imre.deak@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: shuffle panel code
Jani Nikula [Tue, 29 Apr 2014 20:30:48 +0000 (23:30 +0300)]
drm/i915: shuffle panel code

Somehow a few functions have been dropped in the middle of backlight
code. Move them around. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Clear GDSR after reset on ILK
Ville Syrjälä [Mon, 19 May 2014 16:23:26 +0000 (19:23 +0300)]
drm/i915: Clear GDSR after reset on ILK

Clear the reset domain after a succesful GPU reset on ilk. We already
do that on gen4, so let's try to be a bit more consistent. And if
ether render or media reset fails, we might use the leftover value
in the register to pinpoint the culprit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Kill RMW from ILK reset code
Ville Syrjälä [Mon, 19 May 2014 16:23:25 +0000 (19:23 +0300)]
drm/i915: Kill RMW from ILK reset code

All the other bits in the GDSR register are read-only, so we don't have
to preserve them when we perform a GPU reset.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: add missing unregister_oom_notifier to the error/unload path
Imre Deak [Tue, 20 May 2014 16:47:20 +0000 (19:47 +0300)]
drm/i915: add missing unregister_oom_notifier to the error/unload path

I'm trying to reduce the WARNs during driver reload and this was one of
them. Also while at it remove the redundant condition from before
unregister_shrinker().

v2:
- fix the error path too and move the unregister to its logical place
(Chris)
- remove redundant condition from before unregister_shrinker()

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Drop /** */ comments from i915_reg.h
Ville Syrjälä [Fri, 25 Apr 2014 17:14:30 +0000 (20:14 +0300)]
drm/i915: Drop /** */ comments from i915_reg.h

The comments in i915_reg.h aren't proper kernel-doc comments, so replace
the magic /** with just /*

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Add a bunch of pre production workarounds
Ville Syrjälä [Wed, 9 Apr 2014 10:28:41 +0000 (13:28 +0300)]
drm/i915/chv: Add a bunch of pre production workarounds

The following workarounds should be needed for pre-production hardware
only:
* WaDisablePwrmtrEvent:chv
* WaSetMaskForGfxBusyness:chv
* WaDisableGunitClockGating:chv
* WaDisableFfDopClockGating:chv
* WaDisableDopClockGating:chv

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Use RMW to toggle swing calc init
Ville Syrjälä [Wed, 9 Apr 2014 10:29:04 +0000 (13:29 +0300)]
drm/i915/chv: Use RMW to toggle swing calc init

The spec only tells us to set individual bits here and there. So we use
RMW for most things. Do the same for the swing calc init.

Eventually we should optimize things to just blast the final value in
with group access whenever possible. But to do that someone needs to
take a good look at what's the reset value for each registers, and
possibly if the BIOS manages to frob with some of them. For now
use RMW access always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Don't do group access reads from TX lanes either
Ville Syrjälä [Wed, 9 Apr 2014 10:29:03 +0000 (13:29 +0300)]
drm/i915/chv: Don't do group access reads from TX lanes either

Like PCS, TX group reads return 0xffffffff. So we need to target each
lane separately if we want to use RMW cycles to update the registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Don't use PCS group access reads
Ville Syrjälä [Wed, 9 Apr 2014 10:29:02 +0000 (13:29 +0300)]
drm/i915/chv: Don't use PCS group access reads

All PCS groups access reads return 0xffffffff, so we can't use group
access for RMW cycles. Instead target each spline separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Fight conflict with misplaced ; .... ARGH!]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Set soft reset override bit for data lane resets
Ville Syrjälä [Mon, 28 Apr 2014 11:15:24 +0000 (14:15 +0300)]
drm/i915/chv: Set soft reset override bit for data lane resets

The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.

v2: Fix mispalced ';' (Mika)

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Reset data lanes in encoder .post_disable() hook
Ville Syrjälä [Wed, 9 Apr 2014 10:29:00 +0000 (13:29 +0300)]
drm/i915/chv: Reset data lanes in encoder .post_disable() hook

Seems like we shouldn't leave the data lane resert deasserted when
the port if disabled. So propagate the reset the data lanes in
the encoder .post_disable() hook.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Turn off dclkp after the PLL has been disabled
Ville Syrjälä [Wed, 9 Apr 2014 10:28:59 +0000 (13:28 +0300)]
drm/i915/chv: Turn off dclkp after the PLL has been disabled

During the enable sequence we first enable the dclkp output to the
display controller, and then enable the PLL. Do the opposite during
the disable sequence.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Move data lane deassert to encoder pre_enable
Ville Syrjälä [Wed, 9 Apr 2014 10:28:58 +0000 (13:28 +0300)]
drm/i915/chv: Move data lane deassert to encoder pre_enable

We need to pick the correct data lanes based on the port not the
pipe, so move the data lane deassert into the encoder .pre_enable()
hook from the chv_enable_pll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Fix CHV PLL state tracking
Ville Syrjälä [Wed, 9 Apr 2014 10:28:57 +0000 (13:28 +0300)]
drm/i915/chv: Fix CHV PLL state tracking

Setup the pipe config dpll state correctly for CHV. Also add
a assert_pipe_disabled() to chv_disable_pll(), and program the
DPLL_MD registers in chv_enable_pll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Register port D encoders and connectors
Ville Syrjälä [Wed, 9 Apr 2014 10:28:56 +0000 (13:28 +0300)]
drm/i915/chv: Register port D encoders and connectors

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Fix PORT_TO_PIPE for CHV
Ville Syrjälä [Wed, 9 Apr 2014 10:28:55 +0000 (13:28 +0300)]
drm/i915/chv: Fix PORT_TO_PIPE for CHV

Fix the encoder .get_config hooks to report the correct active pipe for
CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Bump num_pipes to 3
Ville Syrjälä [Wed, 9 Apr 2014 10:28:54 +0000 (13:28 +0300)]
drm/i915/chv: Bump num_pipes to 3

CHV has three pipes so let's expose them all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Add cursor pipe offsets
Ville Syrjälä [Wed, 9 Apr 2014 10:28:53 +0000 (13:28 +0300)]
drm/i915/chv: Add cursor pipe offsets

Unsurprisingly the cursor C regiters are also at a weird offset on CHV.
Add more pipe offsets to handle them.

This also gets rid of most of the differences between the i9xx vs. ivb
cursor code. We can unify the remaining code as well, but I'll leave
that for another patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Fix gmbus for port D
Ville Syrjälä [Wed, 9 Apr 2014 10:28:52 +0000 (13:28 +0300)]
drm/i915/chv: Fix gmbus for port D

On CHV the GMBUS port for port D is different from other gmch platforms
which have port D. Fix it up.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Configure crtc_mask correctly for CHV
Ville Syrjälä [Mon, 28 Apr 2014 11:07:43 +0000 (14:07 +0300)]
drm/i915/chv: Configure crtc_mask correctly for CHV

On CHV pipe C can driver only port D, and pipes A and B can drivbe only
ports B and C. Configure the crtc_mask appropriately to reflect that.

v2: Moar braces (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Make CHV irq handler loop until all interrupts are consumed
Ville Syrjälä [Wed, 9 Apr 2014 10:28:50 +0000 (13:28 +0300)]
drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV
Ville Syrjälä [Wed, 9 Apr 2014 10:28:49 +0000 (13:28 +0300)]
drrm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more
Ville Syrjälä [Wed, 9 Apr 2014 10:28:48 +0000 (13:28 +0300)]
drm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Add CHV display support
Rafael Barbalho [Mon, 28 Apr 2014 11:00:42 +0000 (14:00 +0300)]
drm/i915/chv: Add CHV display support

Add support for the third pipe in cherrview

v2: Don't use spaces for indentation (Jani)
    Wrap long lines

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: slightly massaged the patch]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV
Rafael Barbalho [Wed, 9 Apr 2014 10:28:40 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

Cherryview also needs this WA.

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
[vsyrjala: Looks like it's for pre-prodution hw only]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Add some workaround notes
Ville Syrjälä [Mon, 28 Apr 2014 11:31:09 +0000 (14:31 +0300)]
drm/i915/chv: Add some workaround notes

We implement the following workarounds:
* WaDisableAsyncFlipPerfMode:chv
* WaProgramMiArbOnOffAroundMiSetContext:chv

v2: Drop WaDisableSemaphoreAndSyncFlipWait note

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaDisableSDEUnitClockGating:chv
Ville Syrjälä [Wed, 9 Apr 2014 10:28:38 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaDisableSDEUnitClockGating:chv

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaDisableCSUnitClockGating:chv
Ville Syrjälä [Wed, 9 Apr 2014 10:28:37 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaDisableCSUnitClockGating:chv

This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it seems safer to just set the bit.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv
Ville Syrjälä [Wed, 9 Apr 2014 10:28:36 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv

BDW has the same requirement but the w/a database doens't list
this w/a for BDW. Seems to be another one of those "stick a bunch
of known workarounds into this bag and write something on the label"
type of things.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCountFullforc...
Ville Syrjälä [Wed, 9 Apr 2014 10:28:35 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaVSRefCountFullforceMissDisable:chv and WaDSRefCountFullforceMissDisable:chv

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv
Ville Syrjälä [Wed, 9 Apr 2014 10:28:34 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Implement WaDisablePartialInstShootdown:chv
Ville Syrjälä [Wed, 9 Apr 2014 10:28:33 +0000 (13:28 +0300)]
drm/i915/chv: Implement WaDisablePartialInstShootdown:chv

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: s/ironlake_/intel_ for the enable_share_dpll function
Daniel Vetter [Thu, 24 Apr 2014 21:55:14 +0000 (23:55 +0200)]
drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

Besides the fairly useless BUG_ON the logic is completely generic
and cane be used on any platform what wants to reuse the shared
dpll support code.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Extract intel_prepare_shared_dpll
Daniel Vetter [Thu, 24 Apr 2014 21:55:13 +0000 (23:55 +0200)]
drm/i915: Extract intel_prepare_shared_dpll

This is the last piece of code which write state to the hardware in
the ironalake ->crtc_mode_set callback.

I think we could merge this with the pll->enable hook, but otoh the
ordering requirements with the ldvs port are really tricky. Doing the
FP0/1 writes up-front before we even prepare the lvds port (in the
pre_pll_enable hook) like on i9xx seems safest.

With this ilk+ platforms are now ready for runtime PM with DPMS. Since
hsw/bdw also support runtime pm besides snb we need to first make the
haswell code save before we can touch the core code.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Only update shared dpll state when needed
Daniel Vetter [Tue, 20 May 2014 13:19:19 +0000 (15:19 +0200)]
drm/i915: Only update shared dpll state when needed

Instead of every time it isn't active: We only need to do that when
the pll is currently unused, i.e. when pll->refcount == 0. For
paranoia add a warning for the ibx case where plls have a fixed
mapping and hence should always be unused after the call to
intel_put_shared_dpll.

v2: Simplify control flow and use struct assignment instead of memcpy
as suggested by Damien.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Extract vlv_prepare_pll
Daniel Vetter [Thu, 24 Apr 2014 21:55:11 +0000 (23:55 +0200)]
drm/i915: Extract vlv_prepare_pll

With this all hw writes are also gone from the ->crtc_mode_set hook on
vlv. I wondered whether we should track more of the pll state in the
pipe config, but otoh as long as we don't have shared plls that's not
really useful - the cross-checking of the port clock should be
sufficient.

While at it also de-magic some of the pipe checks, this has been
irking me since a long time.

Whit this vlv is now ready for runtime PM on dpms. If we'd have
runtime PM support in general ...

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Extract i9xx_set_pll_dividers
Daniel Vetter [Thu, 24 Apr 2014 21:55:10 +0000 (23:55 +0200)]
drm/i915: Extract i9xx_set_pll_dividers

These two writes are the very last hw writes from the
->crtc_modeset_callback on pre-gen5 hardware. As usual vlv is a bit
different, so this here is just warm-up.

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Shovel hw setup code out of hsw_crtc_mode_set
Daniel Vetter [Thu, 24 Apr 2014 21:55:09 +0000 (23:55 +0200)]
drm/i915: Shovel hw setup code out of hsw_crtc_mode_set

Again the same story: This code just transform sw state from the pipe
config into hardware state. And again we can't move the pll code, but
this time around because the state isn't properly tracked in the pipe
config.

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Shovel hw setup code out of ilk_crtc_mode_set
Daniel Vetter [Thu, 24 Apr 2014 21:55:08 +0000 (23:55 +0200)]
drm/i915: Shovel hw setup code out of ilk_crtc_mode_set

Again this code just transforms sw state from the pipe config into
hardware state, so we can just move it around. Unfortunately again a
few forward declarations since intel_display.c is becoming a bit of a
mess.

Note that both for i9xx and ironlake code the only things remaining in
the ->crtc_mode_set hook is now the clock state computation and
sharing code. That needs to be moved into the compute config stage so
that we can catch impossible configurations earlier.

Also note that some of the DPLL hw setup code is still run from within
->crtc_mode_set, namele the pll->mode_set callback. We need to move
that first before we can do fancy things like enable runtime PM for
dpms off.

v2: Make it compile again after the rebase, bisectability issue
reported by Wu Fengguang.

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set
Daniel Vetter [Thu, 24 Apr 2014 21:55:07 +0000 (23:55 +0200)]
drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set

Now this really should be in the pipe config somewhere, but till now
it isn't. We can at least move it up a bit next to all the other pll
code since intel_dp_set_m_n really doesn't depend upon this.

This is just prep work so that moving all the hw frobbing code from
->crtc_mode_set to ->crtc_enable is clean.

v2: Do the same for haswell while at it, not just for ivb.

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Shovel hw setup code out of i9xx_crtc_mode_set
Daniel Vetter [Thu, 24 Apr 2014 21:55:06 +0000 (23:55 +0200)]
drm/i915: Shovel hw setup code out of i9xx_crtc_mode_set

All these functions simply convert sw state as encoded in the pipe
config or primary framebuffer into hardware state. So we can move them
all into the crtc enable hook. Unfortunately this means a little bit
of duplication between the i9xx and vlv functions, but since we
already have highly refactored code I think this is acceptable.

Also a pile of forward declarations unfortunately.

Note also that the various <platform>_update_pll functions are still
called from within the ->crtc_mode_set hook. Mostly they compute the
clock state for the pipe config, but unfortunately there are some
random register writes interspersed. Those need to be moved out first
before we can enable runtime PM for DPMS.

Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Implement an oom-notifier for last resort shrinking
Chris Wilson [Tue, 20 May 2014 07:28:43 +0000 (08:28 +0100)]
drm/i915: Implement an oom-notifier for last resort shrinking

Before the process killer is invoked, oom-notifiers are executed for one
last try at recovering pages. We can hook into this callback to be sure
that everything that can be is purged from our page lists, and to give a
summary of how much memory is still pinned by the GPU in the case of an
oom. This should be really valuable for debugging OOM issues.

Note that the last-ditch effort call to shrink_all we've previously
called from our normal shrinker when we could free as much as the vm
demaned is moved into the oom notifier. Since the shrinker accounting
races against bind/unbind operations we might have called shrink_all
prematurely, which this approach with an oom notifier avoids.

References: https://bugs.freedesktop.org/show_bug.cgi?id=72742
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: lu hua <huax.lu@intel.com>
[danvet: Bikeshed logical | into || and pimp commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix ILK GPU reset domain bits
Ville Syrjälä [Mon, 19 May 2014 16:23:24 +0000 (19:23 +0300)]
drm/i915: Fix ILK GPU reset domain bits

We're using the reset domains bits for g4x on ilk. But on ilk those bits
actually shifted by one bit. Fix it up so that we use the correct bits.

We were actually always writing 0x2 to the reset domain bits, which
is a reserved value. In practice it looks like the hardware ignores that
value since nothing happens if I write that value when there's a 3D
workload running. Writing the _correct_ render domain value actually
makes the GPU stop.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix ILK reset wait
Ville Syrjälä [Mon, 19 May 2014 16:23:23 +0000 (19:23 +0300)]
drm/i915: Fix ILK reset wait

We should be waiting for the reset bit to clear, not remain set.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Drop bogus comments about display reset
Ville Syrjälä [Mon, 19 May 2014 16:23:22 +0000 (19:23 +0300)]
drm/i915: Drop bogus comments about display reset

There are comments in the gen4-5 reset functions stating that we can't
reset render and media without also doing a display reset. But that's
exactly what the code does, ie. we don't perform a display reset. Drop
the bogus comments.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Invalidate our pages under memory pressure
Chris Wilson [Tue, 25 Mar 2014 13:23:06 +0000 (13:23 +0000)]
drm/i915: Invalidate our pages under memory pressure

Try to flush out dirty pages into the swapcache (and from there into the
swapfile) when under memory pressure and forced to drop GEM objects from
memory. In effect, this should just allow us to discard unused pages for
memory reclaim and to start writeback earlier.

v2: Hugh Dickins warned that explicitly starting writeback from
shrink_slab was prone to deadlocks within shmemfs.

Cc: Hugh Dickins <hughd@google.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Refactor common lock handling between shrinker count/scan
Chris Wilson [Tue, 25 Mar 2014 13:23:05 +0000 (13:23 +0000)]
drm/i915: Refactor common lock handling between shrinker count/scan

We can share a few lines of tricky lock handling we need to use for both
shrinker routines and in the process fix the return value for count()
when reporting a deadlock.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Include bound and active pages in the count of shrinkable objects
Chris Wilson [Tue, 25 Mar 2014 13:23:04 +0000 (13:23 +0000)]
drm/i915: Include bound and active pages in the count of shrinkable objects

When the machine is under a lot of memory pressure and being stressed by
multiple GPU threads, we quite often report fewer than shrinker->batch
(i.e. SHRINK_BATCH) pages to be freed. This causes the shrink_control to
skip calling into i915.ko to release pages, despite the GPU holding onto
most of the physical pages in its active lists.

References: https://bugs.freedesktop.org/show_bug.cgi?id=72742
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Translate ENOSPC from shmem_get_page() to ENOMEM
Chris Wilson [Tue, 25 Mar 2014 13:23:03 +0000 (13:23 +0000)]
drm/i915: Translate ENOSPC from shmem_get_page() to ENOMEM

shmemfs first checks if there is enough memory to allocate the page
and reports ENOSPC should there be insufficient, along with
the usual ENOMEM for a genuine allocation failure.

We use ENOSPC in our driver to mean that we have run out of aperture
space and so want to translate the error from shmemfs back to
our usual understanding of ENOMEM. None of the the other GEM users
appear to distinguish between ENOMEM and ENOSPC in their error handling,
hence it is easiest to do the fixup in i915.ko

Cc: Hugh Dickins <hughd@google.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Robert Beckett <robert.beckett@intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Add MIPI mmio reg base
Shashank Sharma [Mon, 19 May 2014 15:24:03 +0000 (20:54 +0530)]
drm/i915: Add MIPI mmio reg base

This patch adds a mmio base address variable for DSI display,
to make the DSI code generic, so that, if required, the same code
can be re-used for future platforms with different mmio base.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Appease checkpatch.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't die in wait_for_pending_flips
Daniel Vetter [Mon, 19 May 2014 14:09:35 +0000 (16:09 +0200)]
drm/i915: Don't die in wait_for_pending_flips

We can apperently miss them, but breaking the entire driver hampers
testing. So bail out after one minute, our customerary "this is a lost
cause" timeout.

References: https://bugs.freedesktop.org/show_bug.cgi?id=78383
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: vlv/chv: fix DSI sideband register accessing
Imre Deak [Mon, 19 May 2014 08:41:18 +0000 (11:41 +0300)]
drm/i915: vlv/chv: fix DSI sideband register accessing

So far we used the wrong opcodes to access the DSI registers, so the
register writes during DSI programming didn't actually succeed and left
the registers unchanged. This wasn't a problem for the initial modeset,
where the BIOS-programmed values happened to work, but after resuming
from s0ix these registers are reset and failing to program them results
in a blank screen.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: rename IOSF sideband opcodes according to the spec
Imre Deak [Mon, 19 May 2014 08:41:17 +0000 (11:41 +0300)]
drm/i915: rename IOSF sideband opcodes according to the spec

These opcodes are not specific for an endpoint, but are the same for all
endpoints. So rename them accordingly, using the name the VLV2 sideband
HAS uses. Also move the macros to the .c file, since they aren't used
anywhere else.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrivers/gpu/drm/i915/intel_display: coding style fixes
Robin Schroer [Sun, 18 May 2014 00:24:50 +0000 (02:24 +0200)]
drivers/gpu/drm/i915/intel_display: coding style fixes

Fixed several switch statements, curly braces, dereference operators
and keywords.

Signed-off-by: Robin Schroer <sulamiification@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Move fb pinning into __intel_set_mode
Daniel Vetter [Thu, 24 Apr 2014 21:55:05 +0000 (23:55 +0200)]
drm/i915: Move fb pinning into __intel_set_mode

Our two ->crtc_mode_set callbacks really don't care whether the fb is
pinned and set up already or not - all the state computation and
handling which originally looked at the framebuffer is already using
the indirection through the pipe configuration.

Eventually we want to move this up a bit more, but as long as the crtc
mode_set callback still exists (and as long as we don't need to pin an
entire pile of planes due to atomic modesets) there's not much point
in it. So I'll let this be for now.

v2: Don't forget about haswell ...

Reviewed-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Inline set_base into crtc_mode_set
Daniel Vetter [Thu, 24 Apr 2014 21:55:04 +0000 (23:55 +0200)]
drm/i915: Inline set_base into crtc_mode_set

A lot of the code in set_base is uncessary when the crtc is off, so we
can get rid of it all. Also, we don't need to call the fbc/psr update
functions since the crtc enable/disable hooks do that already.

The only things we really need are:
- Pin the new framebuffer and potentially unpin the old framebuffer
  (if the crtc has been on and we only change the configuration).
- Update the plane registers.

The first step will move out of platform code with the very next
patch.

v2: Don't forget about haswell ...

Reviewed-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable
Daniel Vetter [Thu, 24 Apr 2014 21:55:03 +0000 (23:55 +0200)]
drm/i915: Sprinkle intel_edp_psr_update over crtc_enable/disable

My plan here is to split up set_base into a prepare step, which does
the pinning, and a commit stage, which updates the hw state. Eventually
we should be able to move the prepare step at the beginning of any
atomic update. For now I only want to move the commit step into the
crtc_enable callbacks.

As a prep step sprinkle intel_edp_psr_update all over the place so
that we don't have to concern ourselves with that in the commit step.

v2: Rebase on top of Ville's enable/disable functions for all planes.

v3: Rebase more.

Reviewed-by: Akash Goel <akash.goel@intel.com> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: More cargo-culted locking for intel_update_fbc
Daniel Vetter [Thu, 24 Apr 2014 21:55:02 +0000 (23:55 +0200)]
drm/i915: More cargo-culted locking for intel_update_fbc

Just for consistency, this patch won't fix anything really.

v2: Rebase over all the recent plane enabling shuffling.

Reviewed-by: Akash Goel <akash.goel@intel.com> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Make ->update_primary_plane infallible
Daniel Vetter [Thu, 24 Apr 2014 21:55:01 +0000 (23:55 +0200)]
drm/i915: Make ->update_primary_plane infallible

Way back we've used this to reject framebuffers with unsupported
pixel formats. But since the modesetting reorg with the compute
config stage we reject those much earlier and just BUG() in this
callback. So switch to a void return type.

Reviewed-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Retire requests before creating a new one
Chris Wilson [Thu, 15 May 2014 09:41:42 +0000 (10:41 +0100)]
drm/i915: Retire requests before creating a new one

More fallout from

commit c8725f3dc0911d4354315a65150aecd8b7d0d74a
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Mar 17 12:21:55 2014 +0000

    drm/i915: Do not call retire_requests from wait_for_rendering

is that we can completely fill all of memory using small objects, such
that we exhaust the filp space, and spend all of our time evicting
objects from the aperture. As such, we never fill the ring, and never
trigger the last resort flushing in

commit 1cf0ba14740d96fbf6f58a201f000a34b74f4725
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon May 5 09:07:33 2014 +0100

    drm/i915: Flush request queue when waiting for ring space

and so all the requests are left active and the objects keep that last
active reference. Eventually the system comes to a halt as it runs out
of memory.

The impact is mainly limited to test cases as regular userspace will
trigger retirement by manually checking whether an object is active.

Testcase: igt/gem_lut_handle
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78724
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Guo Jinxian <jinxianx.guo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Only unpin the default ctx object if it exists
Chris Wilson [Fri, 16 May 2014 17:59:00 +0000 (18:59 +0100)]
drm/i915: Only unpin the default ctx object if it exists

Since commit 691e6415c891b8b2b082a120b896b443531c4d45
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Apr 9 09:07:36 2014 +0100

    drm/i915: Always use kref tracking for all contexts.

we have contexts everywhere, and so we must be careful to distinguish
fake contexts, which do not have an associated bo, and real ones, which
do. In particular, we now need to be careful not to dereference NULL
pointers.

This is one such example, as the commit highlighted above failed to move
the unpinning of the default ctx object into the real-context-only
branch.

Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78792
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Convert uncleared FIFO underrun message to errors
Ville Syrjälä [Fri, 16 May 2014 16:40:23 +0000 (19:40 +0300)]
drm/i915: Convert uncleared FIFO underrun message to errors

Some platforms have a shared error interrupt, so if FIFO underrun
reporting gets disabled for one pipe/transcoder it gets disabled
for all pipes/transcoders.

When we disable FIFO underrun reporting we check whether the
interrupt was enabled or not. If it wasn't we might have missed
an underrun and we perform one last check right there. Currently
we print a debug message when an underrun is detect using this
mechanism. Promote the message to DRM_ERROR() to match the other
underrun error messages.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Introduce mapping of user pages into video memory (userptr) ioctl
Chris Wilson [Fri, 16 May 2014 13:22:37 +0000 (14:22 +0100)]
drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl

By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, with zero-copy downloads to the GPU and efficient
readback making the intermixed streaming of CPU and GPU operations
fairly efficient. This ability has many widespread implications from
faster rendering of client-side software rasterisers (chromium),
mitigation of stalls due to read back (firefox) and to faster pipelining
of texture data (such as pixel buffer objects in GL or data blobs in CL).

v2: Compile with CONFIG_MMU_NOTIFIER
v3: We can sleep while performing invalidate-range, which we can utilise
to drop our page references prior to the kernel manipulating the vma
(for either discard or cloning) and so protect normal users.
v4: Only run the invalidate notifier if the range intercepts the bo.
v5: Prevent userspace from attempting to GTT mmap non-page aligned buffers
v6: Recheck after reacquire mutex for lost mmu.
v7: Fix implicit padding of ioctl struct by rounding to next 64bit boundary.
v8: Fix rebasing error after forwarding porting the back port.
v9: Limit the userptr to page aligned entries. We now expect userspace
    to handle all the offset-in-page adjustments itself.
v10: Prevent vma from being copied across fork to avoid issues with cow.
v11: Drop vma behaviour changes -- locking is nigh on impossible.
     Use a worker to load user pages to avoid lock inversions.
v12: Use get_task_mm()/mmput() for correct refcounting of mm.
v13: Use a worker to release the mmu_notifier to avoid lock inversion
v14: Decouple mmu_notifier from struct_mutex using a custom mmu_notifer
     with its own locking and tree of objects for each mm/mmu_notifier.
v15: Prevent overlapping userptr objects, and invalidate all objects
     within the mmu_notifier range
v16: Fix a typo for iterating over multiple objects in the range and
     rearrange error path to destroy the mmu_notifier locklessly.
     Also close a race between invalidate_range and the get_pages_worker.
v17: Close a race between get_pages_worker/invalidate_range and fresh
     allocations of the same userptr range - and notice that
     struct_mutex was presumed to be held when during creation it wasn't.
v18: Sigh. Fix the refactor of st_set_pages() to allocate enough memory
     for the struct sg_table and to clear it before reporting an error.
v19: Always error out on read-only userptr requests as we don't have the
     hardware infrastructure to support them at the moment.
v20: Refuse to implement read-only support until we have the required
     infrastructure - but reserve the bit in flags for future use.
v21: use_mm() is not required for get_user_pages(). It is only meant to
     be used to fix up the kernel thread's current->mm for use with
     copy_user().
v22: Use sg_alloc_table_from_pages for that chunky feeling
v23: Export a function for sanity checking dma-buf rather than encode
     userptr details elsewhere, and clean up comments based on
     suggestions by Bradley.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Cc: "Volkin, Bradley D" <bradley.d.volkin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com>
[danvet: Frob ioctl allocation to pick the next one - will cause a bit
of fuss with create2 apparently, but such are the rules.]
[danvet2: oops, forgot to git add after manual patch application]
[danvet3: Appease sparse.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Be careful with non-disp bit in PMINTRMSK
Mika Kuoppala [Fri, 16 May 2014 10:44:12 +0000 (13:44 +0300)]
drm/i915: Be careful with non-disp bit in PMINTRMSK

Bit 31 in GEN6_PMINTRMSK is not an interrupt disable bit with gen8.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Gracefully handle obj not bound to GGTT in is_pin_display
Oscar Mateo [Fri, 16 May 2014 13:20:43 +0000 (14:20 +0100)]
drm/i915: Gracefully handle obj not bound to GGTT in is_pin_display

Otherwise, we do a NULL pointer dereference.

I've seen this happen while handling an error in
i915_gem_object_pin_to_display_plane():

If i915_gem_object_set_cache_level() fails, we call is_pin_display()
to handle the error. At this point, the object is still not pinned
to GGTT and maybe not even bound, so we have to check before we
dereference its GGTT vma.

The IGT kms_flip/bo-too-big tests for this bug.

v2: Chris Wilson says restoring the old value is easier, but that
is_pin_display is useful as a theory of operation. Take the solomonic
decision: at least this way is_pin_display is a little more robust
(until Chris can kill it off).

v3: Chris suggests the WARN in i915_gem_obj_to_ggtt has outlived its
usefulness: add a reminder to remove it.

Issue: VIZ-3772
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Testcase: igt/kms_flip/bo-too-big
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Stop calling encoder->mode_set
Daniel Vetter [Thu, 24 Apr 2014 21:55:00 +0000 (23:55 +0200)]
drm/i915: Stop calling encoder->mode_set

All the callbacks are gone now.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dsi: Remove ->mode_set callback
Daniel Vetter [Thu, 24 Apr 2014 21:54:59 +0000 (23:54 +0200)]
drm/i915/dsi: Remove ->mode_set callback

Looking at our current dsi driver I note that:
- We don't have any slave driver right now.
- There's zero support for the hardware state readout and cross check
  code.
- All the modeset state seems to be tracked in the intel_dsi structure
  instead of the pipe config.

Given all that I can't properly audit the dsi ->mode_set callback. So
just do it as the first thing in the ->pre_pll_enable hook and hope
for the best.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/ddi: Remove ->mode_set callback
Daniel Vetter [Thu, 24 Apr 2014 21:54:58 +0000 (23:54 +0200)]
drm/i915/ddi: Remove ->mode_set callback

A bit more care required here since there are some very few things
between the call to encoder->mode_set and encoder->pre_enable. But
they're either book-keeping or only matter for the vga port on the
pch. So of no concern.

Note that with the new sequence we write the infoframes after
selecting the clock source, but that shouldn't matter. I've simply
opted for this to have simpler code.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/lvds: Remove ->mode_set callback
Daniel Vetter [Thu, 24 Apr 2014 21:54:57 +0000 (23:54 +0200)]
drm/i915/lvds: Remove ->mode_set callback

All the hard work was already done, only thing left to do is remove
the empty callback. And a now rather misleading comment I've spotted
while reading through code.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/hdmi: Remove ->mode_set callback
Daniel Vetter [Thu, 24 Apr 2014 21:54:56 +0000 (23:54 +0200)]
drm/i915/hdmi: Remove ->mode_set callback

Similar to dp the only thing we do is call intel_write_eld and prepare
a bit of state for the enable hooks. The only difference is that we
write that to the hardware instead of keeping track of it somewhere in
software.

Still we can just move all this to the very first enable hook.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/hdmi: Remove redundant IS_VLV checks
Daniel Vetter [Thu, 24 Apr 2014 21:54:55 +0000 (23:54 +0200)]
drm/i915/hdmi: Remove redundant IS_VLV checks

Those functions are only used on vlv platforms, so no need to check.
Especially if we're not too consistent about it.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: Remove ->mode_set callback
Daniel Vetter [Thu, 24 Apr 2014 21:54:54 +0000 (23:54 +0200)]
drm/i915/dp: Remove ->mode_set callback

With all the preceding refactoring the dp mode_set callback only
computes a bit of state (all derived from the pipe config) and also
writes the eld. As long as we do that before we enable the audio bit
or depend upon the correct value in intel_dp->DP we'll be fine.

No other hw state is touched.

We therefore only need to check that clearing intel_dp->DP is save.
Which it is since when we re-enable we already mask out all the bits
the link training code sets. And we need to keep on doing that so that
the re-train loop walking over pre-emph/voltage-swing values still
works properly.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
Daniel Vetter [Thu, 24 Apr 2014 21:54:53 +0000 (23:54 +0200)]
drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp

Only ilk/snb/ivb need the port A pll setup, so move it to the
pre_enable hook for those platforms. We can savely do this since on
those platforms there's nothing that touches the hardware between the
encoder->mode_set and the encoder->pre_enable calls.

Also add a comment that port A is ilk+ only.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Track has_audio in the pipe config
Daniel Vetter [Thu, 24 Apr 2014 21:54:52 +0000 (23:54 +0200)]
drm/i915: Track has_audio in the pipe config

Including state readout and cross-checking. This allows us to get rid
of crtc->eld_vld on hsw+. It also means that fastboot will be unhappy
if the BIOS hasn't set up the audio routing like we want it too.

Wrt fastboot and external screens I see a few options:
- Don't.
- Try to fix up eld, infoframes and audio settings after the fact. But
  that means some pretty extensive reworking of our code which
  currently does all this while the pipe/port is still off.

I won't bother with converting SDVO over to this because the audio
support for SDVO is very lacking:
- We don't update the eld.
- We don't update the audio state on the sdvo encoder.
- We don't check whether the platform can even feed audio to the sdvo
  encoder.

I've converted hdmi, dp & ddi all in one go since ddi needs both hdmi
and dp converted and so doing it step-by-step would have required a
few intermediate hacks.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Simplify audio handling on DDI ports
Daniel Vetter [Thu, 24 Apr 2014 21:54:51 +0000 (23:54 +0200)]
drm/i915: Simplify audio handling on DDI ports

There's no need to check whether audio is enabled (which for ddi ports
is done through the crtc->eld_vld flag) since at the cost of a
potentially unecessary register rmw cycle we can unconditionally do
this.

Note that the edp check is just paranoia since we won't ever call the
write_eld function for an edp panel.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/sdvo: use config->has_hdmi_sink
Daniel Vetter [Thu, 24 Apr 2014 21:54:50 +0000 (23:54 +0200)]
drm/i915/sdvo: use config->has_hdmi_sink

This way we can rely on the state cross-checker to have a bit
assurance that we'll get it right.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: state readout and cross checking for limited_color_range
Daniel Vetter [Thu, 24 Apr 2014 21:54:49 +0000 (23:54 +0200)]
drm/i915: state readout and cross checking for limited_color_range

At least on those platforms which have a simple bit and don't rely
on the fully programmable CSC unit to do this.

Note that with the current code this includes CHV, but I guess that
platform will match BYT.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/sdvo: Use pipe_config->limited_color_range consistently
Daniel Vetter [Thu, 24 Apr 2014 21:54:48 +0000 (23:54 +0200)]
drm/i915/sdvo: Use pipe_config->limited_color_range consistently

We in the pre_enable hook we should only rely on the pipe config and
not on some other state set through properties or detect functions.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Track hdmi mode in the pipe config
Daniel Vetter [Thu, 24 Apr 2014 21:54:47 +0000 (23:54 +0200)]
drm/i915: Track hdmi mode in the pipe config

Also add state readout and cross-check support. The only invasive change
is wiring up the new flag to the ->set_infoframes callbacks.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/hdmi: Enable hdmi mode on g4x, too
Daniel Vetter [Thu, 24 Apr 2014 21:54:46 +0000 (23:54 +0200)]
drm/i915/hdmi: Enable hdmi mode on g4x, too

For compliance we really should be sending NULL infoframes always
when we detect a hdmi capable monitor. Also remove the now redudant
setting for the has_audio case and enforce that audio is only
possible with a hdmi sink.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Enable rc6 with bdw
Mika Kuoppala [Thu, 15 May 2014 17:58:11 +0000 (20:58 +0300)]
drm/i915: Enable rc6 with bdw

Everything should be in place so enable rc6/rps for bdw.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Fix rc6 options debug info
Mika Kuoppala [Thu, 15 May 2014 17:58:10 +0000 (20:58 +0300)]
drm/i915: Fix rc6 options debug info

by correctly displaying result and requested.

Suggested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Enable PM Interrupts target via Display Interface.
Deepak S [Thu, 15 May 2014 17:58:09 +0000 (20:58 +0300)]
drm/i915: Enable PM Interrupts target via Display Interface.

In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.

v2: Add (1<<31) mask (Ville)

v3: Add Gen check for the mask (ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/bdw: Implement a basic PM interrupt handler
Ben Widawsky [Thu, 15 May 2014 17:58:08 +0000 (20:58 +0300)]
drm/i915/bdw: Implement a basic PM interrupt handler

Almost all of it is reusable from the existing code. The primary
difference is we need to do even less in the interrupt handler, since
interrupts are not shared in the same way.

The patch is mostly a copy-paste of the existing snb+ code, with updates
to the relevant parts requiring changes to the interrupt handling. As
such it /should/ be relatively trivial. It's highly likely that I missed
some places where I need a gen8 version of the PM interrupts, but it has
become invisible to me by now.

This patch could probably be split into adding the new functions,
followed by actually handling the interrupts. Since the code is
currently disabled (and broken) I think the patch stands better by
itself.

v2: Move the commit about not touching the ringbuffer interrupt to the
snb_* function where it belongs (Rodrigo)

v3: Rebased on Paulo's runtime PM changes

v4: Not well validated, but rebase on
commit 730488b2eddded4497f63f70867b1256cd9e117c
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date:   Fri Mar 7 20:12:32 2014 -0300

    drm/i915: kill dev_priv->pm.regsave

v5: Rebased on latest code base. (Deepak)

v6: Remove conflict markers, Unnecessary empty line and use right
IIR interrupt (Ville)

v7: mask modified without rmw (Ville Syrjälä)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Bail out early on gen6_signal if no semaphores
Mika Kuoppala [Thu, 15 May 2014 17:58:07 +0000 (20:58 +0300)]
drm/i915: Bail out early on gen6_signal if no semaphores

If we dont have semaphores enabled, we allocate 4
dwords for signalling. But end up emitting more regardless.

Fix this by bailing out early if semaphores are not enabled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78274
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78283
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: MIPI PPS delays added
Shobhit Kumar [Mon, 14 Apr 2014 05:48:26 +0000 (11:18 +0530)]
drm/i915: MIPI PPS delays added

Added as generic parameters which will be initialized in the panel
driver and are specific to panels.

Backlight delays have also kept as placeholders and will be used used
once we have MIPI backlight enabling support

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: MIPI init count programming as generic parameter
Shobhit Kumar [Mon, 14 Apr 2014 05:48:25 +0000 (11:18 +0530)]
drm/i915: MIPI init count programming as generic parameter

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Correct MIPI operation mode as per expected values from VBT
Shobhit Kumar [Mon, 14 Apr 2014 05:48:24 +0000 (11:18 +0530)]
drm/i915: Correct MIPI operation mode as per expected values from VBT

In VBT fields operation mode is 0 for Video mode and 1 for command mode.
This field will be directly used as is in generic panel driver. So
adjust accordingly.

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: add null render states for gen6, gen7 and gen8
Mika Kuoppala [Wed, 14 May 2014 14:02:17 +0000 (17:02 +0300)]
drm/i915: add null render states for gen6, gen7 and gen8

These are generated with intel-gpu-tools/tools/null_state_gen

v2: Don't use header file for states (Daniel Vetter)

v3: Proper URB state size for gen8/GT3 (Damien Lespiau)

Tested-by: Kristen Carlson Accardi <kristen@linux.intel.com> (v1)
Tested-by: Oscar Mateo <oscar.mateo@intel.com> (v2)
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: add render state initialization
Mika Kuoppala [Wed, 14 May 2014 14:02:16 +0000 (17:02 +0300)]
drm/i915: add render state initialization

HW guys say that it is not a cool idea to let device
go into rc6 without proper 3d pipeline state.

For each new uninitialized context, generate a
valid null render state to be run on context
creation.

This patch introduces a skeleton with empty states.

v2: - No need to vmap (Chris Wilson)
    - use .c files for state (Daniel Vetter)
    - no need to flush as i915_add_request does it
    - remove parameter for batch alloc size
    - don't wait for the init (Ben Widawsky)

v3: - move to cpu/gpu (Chris Wilson)

Tested-by: Kristen Carlson Accardi <kristen@linux.intel.com> (v1)
Tested-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Only do gtt cleanup in vma_unbind for the global vma
Daniel Vetter [Fri, 14 Feb 2014 13:06:07 +0000 (14:06 +0100)]
drm/i915: Only do gtt cleanup in vma_unbind for the global vma

Otherwise we end up tearing down fences when e.g. the client quits
way too early. Might or might not fix a fence pin_count BUG Ville has
reported.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't drop pinned fences
Daniel Vetter [Fri, 14 Feb 2014 13:06:05 +0000 (14:06 +0100)]
drm/i915: Don't drop pinned fences

Userspace can currently provoke this when e.g. trying to use a pinned
scanout as a cursor or overlay target. Later on that might lead to
some fun fence pin count mayhem.

Spurred by Ville's report that something goes wrong here and
originally I've thought that this might slip through the pwrite gtt
fastpath. But that one checks of obj tiling, so should be ok.

But one thing that _does_ blow up is the vma unbinding with more than
one address space. The next patch will fix this.

v2: Use a WARN_ON - Chris pointed out that we already catch all cases
so userspace can't provoke this like I've originally feared.

While reviewing relevant code I've noticed a pile of DRM_ERROR in the
overlay&cursor code which are all triggerable by userspace. Tune them
down while at it.

v3: Split out the DRM_ERROR->DRM_DEBUG_KMS change into a separate patch,
as requested by Chris.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: use dev_priv directly in i915_driver_unload
Daniel Vetter [Tue, 13 May 2014 20:21:59 +0000 (22:21 +0200)]
drm/i915: use dev_priv directly in i915_driver_unload

Noticed while playing with coccinelle.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use the connector name in fbdev debug messages
Chris Wilson [Tue, 13 May 2014 12:45:09 +0000 (13:45 +0100)]
drm/i915: Use the connector name in fbdev debug messages

During initial probing of the modes to assign to the fbdev console, we
use the CRTC and connector ids. These are much harder for us to
understand than if we used their actual names (or pipe in the CRTC
case). Similarly, we want to manually print the mode size rather than
rely on mode->name being set.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Use for_each_crtc() when iterating through the CRTCs
Damien Lespiau [Tue, 13 May 2014 22:32:24 +0000 (23:32 +0100)]
drm/i915: Use for_each_crtc() when iterating through the CRTCs

Patch done using the following semantic patch (thanks Daniel for the
help!)

  @@
  iterator name list_for_each_entry;
  iterator name for_each_crtc;
  struct drm_crtc * crtc;
  struct drm_device * dev;
  @@
  -list_for_each_entry(crtc,&dev->mode_config.crtc_list, head) {
  +for_each_crtc(dev,crtc) {
   ...
  }

Followed by a couple of fixups by hand (that spatch doesn't match the
cases where list_for_each_entry() is not followed by a set of '{', '}',
but I couldn't figure out a way to leave the '{' out of the iterator
match).

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>