GitHub/moto-9609/android_kernel_motorola_exynos9610.git
9 years agodrm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code
Ville Syrjälä [Tue, 2 Jun 2015 12:37:35 +0000 (15:37 +0300)]
drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code

 commit 65ca7514e21adbee25b8175fc909759c735d00ff
 Author: Damien Lespiau <damien.lespiau@intel.com>
 Date:   Mon Feb 9 19:33:22 2015 +0000

    drm/i915/skl: Implement WaBarrierPerformanceFixDisable

got misapplied and the code landed in chv_init_workarounds() instead of
the intended skl_init_workarounds(). Move it over to the right place.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
9 years agodrm/i915: abstract hpd irq storm detection
Jani Nikula [Fri, 29 May 2015 13:14:37 +0000 (16:14 +0300)]
drm/i915: abstract hpd irq storm detection

Simplify intel_hpd_irq_handler() by extracting HPD irq storm detection
to a separate function.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Silence compiler warning
Ander Conselvan de Oliveira [Fri, 29 May 2015 11:28:09 +0000 (14:28 +0300)]
drm/i915: Silence compiler warning

Silence the following -Wmaybe-uninitialized warnings and make the code
more clear.

drivers/gpu/drm/i915/intel_display.c: In function ‘__intel_set_mode’:
drivers/gpu/drm/i915/intel_display.c:11844:14: warning: ‘crtc_state’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  return state->mode_changed || state->active_changed;
              ^
drivers/gpu/drm/i915/intel_display.c:11854:25: note: ‘crtc_state’ was declared here
  struct drm_crtc_state *crtc_state;
                         ^
drivers/gpu/drm/i915/intel_display.c:11868:6: warning: ‘crtc’ may be used uninitialized in this function [-Wmaybe-uninitialized]
   if (crtc != intel_encoder->base.crtc)
      ^
drivers/gpu/drm/i915/intel_display.c:11853:19: note: ‘crtc’ was declared here
  struct drm_crtc *crtc;

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: clear hpd status sticky bits earlier
Jani Nikula [Thu, 28 May 2015 12:43:54 +0000 (15:43 +0300)]
drm/i915/bxt: clear hpd status sticky bits earlier

The hotplug status is cached in hp_control, and will be passed on to
bottom halves through intel_hpd_irq_handler(), so we can clear the
sticky bits earlier.

While at it, drop the redundant logging of the hotplug status, which
will also be logged by pch_get_hpd_pins().

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: abstract away platform specific parts from hpd handling
Jani Nikula [Thu, 28 May 2015 12:43:53 +0000 (15:43 +0300)]
drm/i915: abstract away platform specific parts from hpd handling

Split intel_hpd_irq_handler into platforms specific and platform
agnostic parts. The platform specific parts decode the registers into
information about which hpd pins triggered, and if they were long
pulses. The platform agnostic parts do further processing, such as
interrupt storm mitigation and scheduling bottom halves.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: simplify condition for digital port
Jani Nikula [Thu, 28 May 2015 12:43:52 +0000 (15:43 +0300)]
drm/i915: simplify condition for digital port

As the hpd loops have been merged together, we don't have to maintain
state for all hpd triggers.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: merge the two hpd loops in intel_hpd_irq_handler to one
Jani Nikula [Thu, 28 May 2015 12:43:51 +0000 (15:43 +0300)]
drm/i915: merge the two hpd loops in intel_hpd_irq_handler to one

Nothing in the two consecutive loops over hpd pins depends on state in a
larger context than the single hpd pin. If we skip the rest of the loop
on short hpd pulses, we can merge the two loops into one.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: put back the indent in intel_hpd_irq_handler
Jani Nikula [Thu, 28 May 2015 12:43:50 +0000 (15:43 +0300)]
drm/i915: put back the indent in intel_hpd_irq_handler

In an unfortunate back and forth stepping, retract the earlier change to
reduce indent. This is to make merging the two loops easier. No
functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: simplify conditions for skipping the 2nd hpd loop iterations
Jani Nikula [Thu, 28 May 2015 12:43:49 +0000 (15:43 +0300)]
drm/i915: simplify conditions for skipping the 2nd hpd loop iterations

Multiple positive and negative checks for hpd[i] & hotplug_trigger gets
hard to read. Simplify. This should make follow-up patches merging the
two loops easier. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: add for_each_hpd_pin to iterate over hotplug pins
Jani Nikula [Thu, 28 May 2015 12:43:48 +0000 (15:43 +0300)]
drm/i915: add for_each_hpd_pin to iterate over hotplug pins

No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Warn when cdclk for the platforms is not known
Ville Syrjälä [Fri, 22 May 2015 08:22:34 +0000 (11:22 +0300)]
drm/i915: Warn when cdclk for the platforms is not known

Print a warning if we fall through the .get_display_clock_speed() function
pointer setup. We end up assuming a 133MHz cdclk which should mean that
at least we avoid any 0 deivisions and whatnot. But this could at least
help remind people that they have to provide this function for new platforms.

v2: Rebased to the latest
v3: Rebased to the latest

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add cdclk extraction for g33, g965gm and g4x
Ville Syrjälä [Fri, 22 May 2015 08:22:33 +0000 (11:22 +0300)]
drm/i915: Add cdclk extraction for g33, g965gm and g4x

Implement cdclk extraction for g33, 965gm and g4x platforms. The details
came from configdb. Sadly there isn't anything there for other gen3/gen4
chipsets.

So far I've tested this on one ELK where it gave me a HPLL VCO of 5333
MHz and cdclk of 444 MHz which seems perfectly sane for this machine.

v2: Rebased to the latest
v3: Rebased to the latest

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix 852GM/GMV cdclk
Ville Syrjälä [Fri, 22 May 2015 08:22:32 +0000 (11:22 +0300)]
drm/i915: Fix 852GM/GMV cdclk

It seems 852GM/GMV uses a different HPLLCC encoding than the other
85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that
using the PCI revision (sinc the device ID seems useless for that). I'm
not at all sure this is a good idea, but according to the specs it
should work.

v2: Rebased to the latest
v3: Rebased to the latest

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix i855 get_display_clock_speed
Ville Syrjälä [Fri, 22 May 2015 08:22:31 +0000 (11:22 +0300)]
drm/i915: Fix i855 get_display_clock_speed

Actually read the HPLLCC register insted of assuming it's 0. Fix the
HPLLCC bit definitions and all the missing ones from the 852GME spec.

852GME, 854 and 855 all seem to match the same HPLLC encoding even
though only some of the values are valid is some of the platforms.

v2: Rebased to the latest
v3: Rebased to the latest

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Only show view type for GGTT VMAs
Tvrtko Ursulin [Wed, 27 May 2015 09:52:32 +0000 (10:52 +0100)]
drm/i915: Only show view type for GGTT VMAs

Printing it for PPGTT VMAs only adds noise since we have defined
view types are only applicable for GGTT.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Don't try to store the wrong central frequency
Damien Lespiau [Thu, 7 May 2015 17:38:47 +0000 (18:38 +0100)]
drm/i915/skl: Don't try to store the wrong central frequency

The orignal code started by storing the actual central frequency (in Hz,
using a uint64_t) in a uint32_t which codes for the register value. That
can't be right.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Correctly prefix HSW/BDW HDMI clock functions
Damien Lespiau [Thu, 7 May 2015 17:38:46 +0000 (18:38 +0100)]
drm/i915: Correctly prefix HSW/BDW HDMI clock functions

Those functions were the only one in existence when they were
introduced. We now know they are only valid for HSW/BDW.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Remove unnecessary () used with abs_diff()
Damien Lespiau [Thu, 7 May 2015 17:38:44 +0000 (18:38 +0100)]
drm/i915/skl: Remove unnecessary () used with abs_diff()

abs_diff() properly protects its parameters, so no need for the outer ()
here.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Remove unnecessary () used with div_u64()
Damien Lespiau [Thu, 7 May 2015 17:38:43 +0000 (18:38 +0100)]
drm/i915/skl: Remove unnecessary () used with div_u64()

div_u64() can be either a inline function or a define, but in either
case it's safe to provide expressions as parameters without outer ()
around them.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Factor out computing the DPLL paramaters from the dividers
Damien Lespiau [Thu, 7 May 2015 17:38:42 +0000 (18:38 +0100)]
drm/i915/skl: Factor out computing the DPLL paramaters from the dividers

This part doesn't depend on how we compute the DPLL dividers (p and
p0/p1/p2) and can be reused even if we change the algorithm to do so.
(something that is planned for a followup patch)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Use a more idomatic early return
Damien Lespiau [Thu, 7 May 2015 17:38:41 +0000 (18:38 +0100)]
drm/i915/skl: Use a more idomatic early return

We can coalesce the WARN() condition with the WARN() itself and, as we
are returning early, we can de-intent the rest of the function.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Propagate the error if we fail to find a suitable DPLL divider
Damien Lespiau [Thu, 7 May 2015 17:38:40 +0000 (18:38 +0100)]
drm/i915/skl: Propagate the error if we fail to find a suitable DPLL divider

At the moment, even if we fail to find a suitable divider, we'll still
try to set the mode with bogus parameters.

Just fail the modeset if we can't generate the frequency.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failing
Damien Lespiau [Thu, 7 May 2015 17:38:39 +0000 (18:38 +0100)]
drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failing

This helps debugging.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Make sure to break when not finding suitable PLL dividers
Damien Lespiau [Thu, 7 May 2015 17:38:38 +0000 (18:38 +0100)]
drm/i915/skl: Make sure to break when not finding suitable PLL dividers

Right now, when finishing the cycle with odd dividers without finding a
suitable candidate, we end up in an infinite loop. Make sure to break in
that case.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/dsi: remove non-op hot plug callback
Jani Nikula [Wed, 27 May 2015 12:03:45 +0000 (15:03 +0300)]
drm/i915/dsi: remove non-op hot plug callback

Not needed or used.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: remove useless DP and DDI encoder ->hot_plug hooks
Jani Nikula [Wed, 27 May 2015 12:03:44 +0000 (15:03 +0300)]
drm/i915: remove useless DP and DDI encoder ->hot_plug hooks

The hotplug callbacks for DP and DDI effectively did nothing. Remove
them.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: group all hotplug related fields into a new struct in dev_priv
Jani Nikula [Wed, 27 May 2015 12:03:42 +0000 (15:03 +0300)]
drm/i915: group all hotplug related fields into a new struct in dev_priv

There are plenty of hotplug related fields in struct drm_i915_private
scattered all around. Group them under one hotplug struct. Clean up
naming while at it. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: reduce indent in intel_hpd_irq_handler
Jani Nikula [Wed, 27 May 2015 12:03:41 +0000 (15:03 +0300)]
drm/i915: reduce indent in intel_hpd_irq_handler

Continue to loop early if there's nothing to do. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: reduce duplicate conditions in i9xx_hpd_irq_handler
Jani Nikula [Wed, 27 May 2015 12:03:40 +0000 (15:03 +0300)]
drm/i915: reduce duplicate conditions in i9xx_hpd_irq_handler

Move dp aux irq handling within the same branch instead of duplicating
the conditions. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: reduce indent in i9xx_hpd_irq_handler
Jani Nikula [Wed, 27 May 2015 12:03:39 +0000 (15:03 +0300)]
drm/i915: reduce indent in i9xx_hpd_irq_handler

Bail out early if nothing to do. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: add a context parameter to {en, dis}able zero address mapping
David Weinehall [Wed, 20 May 2015 14:00:13 +0000 (17:00 +0300)]
drm/i915: add a context parameter to {en, dis}able zero address mapping

Export a new context parameter that can be set/queried through the
context_{get,set}param ioctls.  This parameter is passed as a context
flag and decides whether or not a GPU address mapping is allowed to
be made at address zero.  The default is to allow such mappings.

Signed-off-by: David Weinehall <david.weinehall@intel.com>
Acked-by: "Zou, Nanhai" <nanhai.zou@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: disable IPS while getting the sink CRCs
Paulo Zanoni [Mon, 25 May 2015 21:52:29 +0000 (18:52 -0300)]
drm/i915: disable IPS while getting the sink CRCs

This commit is the "sink CRC" version of:

commit 8c740dcea254a1472df2c0ac5ac585412a2507ec
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date:   Fri Oct 17 18:42:03 2014 -0300
    drm/i915: disable IPS while getting the pipe CRCs.

For some unknown reason, when IPS gets enabled, the sink CRC changes.
Since hsw_enable_ips() doesn't really guarantee to enable IPS (it
depends on package C-states), we can't really predict if IPS is
enabled or disabled while running our CRC tests, so let's just
completely disable IPS while sink CRCs are being used.

If we find a way to make IPS not change the pipe CRC result, we may
want to fix IPS and then revert this patch (and 8c740dcea too). While
this doesn't happen, let's merge this patch, so the IGT tests relying
on sink CRCs can work properly.

This was discovered while developing a new IGT test, which will
probably be called kms_frontbuffer_tracking.

Testcase: igt/kms_frontbuffer_tracking (not on upstream IGT yet)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Disable 12bpc hdmi for now
Daniel Vetter [Thu, 28 May 2015 07:38:45 +0000 (09:38 +0200)]
drm/i915: Disable 12bpc hdmi for now

It's totally broken, and since

commit d328c9d78d64ca11e744fe227096990430a88477
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Apr 10 16:22:37 2015 +0200

    drm/i915: Select starting pipe bpp irrespective or the primary plane

the kernel will try to use it even for the common rgb888 framebuffers.
Ville has patches to fix it all up properly, but unfortunately they're
stuck in review limbo. And since the 4.2 feature cutoff has passed we
need to somehow  handle this regression.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Adjust sideband locking a bit for CHV/VLV
Ville Syrjälä [Tue, 26 May 2015 17:42:31 +0000 (20:42 +0300)]
drm/i915: Adjust sideband locking a bit for CHV/VLV

chv_enable_pll() doesn't need to hold sb_lock for the entire duration of
the function. Drop the lock as soon as possible.

valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle
with sb_lock. Grab the lock a few lines earlier so we can make do
with a single lock+unlock cycle always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: s/dpio_lock/sb_lock/
Ville Syrjälä [Tue, 26 May 2015 17:42:30 +0000 (20:42 +0300)]
drm/i915: s/dpio_lock/sb_lock/

Rename dpio_lock to sb_lock to inform the reader that its primary
purpose is to protect the sideband mailbox rather than some DPIO
state.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Kill intel_flush_primary_plane()
Ville Syrjälä [Tue, 26 May 2015 17:27:23 +0000 (20:27 +0300)]
drm/i915: Kill intel_flush_primary_plane()

The primary plane frobbing was removed from the sprite code in
 commit ecce87ea3ab55ad0dc64460e6422c357d158a55e
 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
 Date:   Tue Apr 21 17:12:50 2015 +0300

    drm/i915: Remove implicitly disabling primary plane for now

but the intel_flush_primary_plane() calls were left behind. Replace them
with straight forward POSTING_READ() of the sprite surface address
register.

The other user of intel_flush_primary_plane() is g4x_disable_trickle_feed()
where we can just inline the steps directly.

This allows intel_flush_primary_plane() to be killed off.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Throw out WIP CHV power well definitions
Ville Syrjälä [Tue, 26 May 2015 17:22:39 +0000 (20:22 +0300)]
drm/i915: Throw out WIP CHV power well definitions

Expecting CHV power wells to be just an extended versions of the VLV
power wells, a bunch of commented out power wells were added in
anticipation when Punit folks would implement it all. Turns out they
never did, and instead CHV has fewer power wells than VLV. Rip out all
the #if 0'ed junk that's not needed.

v2: Rename the "pipe-a" well to "display" to match VLV
    Clarify the pipe A power well relationship to pipes B and C (Deepak)

Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use the default 600ns LDO programming sequence delay
Ville Syrjälä [Tue, 26 May 2015 17:22:38 +0000 (20:22 +0300)]
drm/i915: Use the default 600ns LDO programming sequence delay

Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the spec says that 600ns is "Used by default for initial
bringup", and the BIOS seems to use that, so let's do the same.

Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove unnecessary null check in execlists_context_unqueue
Michel Thierry [Mon, 27 Apr 2015 11:31:44 +0000 (12:31 +0100)]
drm/i915: Remove unnecessary null check in execlists_context_unqueue

commit 53292cdb066950611e5bc2e0eb109c7edb42af78 ("drm/i915: Workaround
to avoid lite restore with HEAD==TAIL") added a check for req0 != null
which is unnecessary.

The only way req0 could be null is if the list was empty, and this is
already addressed at the beginning of execlists_context_unqueue().

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use spinlocks for checking when to waitboost
Chris Wilson [Thu, 21 May 2015 20:01:47 +0000 (21:01 +0100)]
drm/i915: Use spinlocks for checking when to waitboost

In commit 1854d5ca0dd7a9fc11243ff220a3e93fce2b4d3e
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Apr 7 16:20:32 2015 +0100

    drm/i915: Deminish contribution of wait-boosting from clients

we removed an atomic timer based check for allowing waitboosting and
moved it below the mutex taken during RPS. However, that mutex can be
held for long periods of time on Vallyview/Cherryview as communication
with the PCU is slow. As clients may frequently wait for results (e.g.
such as tranform feedback) we introduced contention between the client
and the RPS worker. We can take advantage of the RPS worker, by
switching the wait boost decision to use spin locks and defer the
actual reclocking to the worker.

Fixes a regression of up to 45% on Baytrail and Baswell!

v2 (Daniel):
- Use max_freq_softlimit instead of the not-yet-merged boost
  frequency.
- Don't inject a fake irq into the boost work, instead treat
  client_boost as just another legit waker.

v3: Drop the now unused mask (Chris).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90112
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix the confusing comment about the ioctl limits
Damien Lespiau [Tue, 26 May 2015 13:57:19 +0000 (14:57 +0100)]
drm/i915: Fix the confusing comment about the ioctl limits

It was reported that this comment was confusing, and indeed it is.

v2: (one year later!) Add the range for the DRM_I915_* iotcl defines
    (Daniel)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agoRevert "drm/i915: Force clean compilation with -Werror"
Daniel Vetter [Tue, 26 May 2015 05:46:21 +0000 (07:46 +0200)]
Revert "drm/i915: Force clean compilation with -Werror"

This reverts commit 118182e9d7d5afa0c7c10f568afb46ab78b462e9.

It's causing too much trouble when compile-testing for non-i915 folks.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Update DRIVER_DATE to 20150522
Daniel Vetter [Fri, 22 May 2015 17:45:27 +0000 (19:45 +0200)]
drm/i915: Update DRIVER_DATE to 20150522

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Introduce DRM_I915_THROTTLE_JIFFIES
Chris Wilson [Thu, 21 May 2015 20:01:48 +0000 (21:01 +0100)]
drm/i915: Introduce DRM_I915_THROTTLE_JIFFIES

As Daniel commented on

commit b7ffe1362c5f468b853223acc9268804aa92afc8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Apr 27 13:41:24 2015 +0100

    drm/i915: Free RPS boosts for all laggards

it is better to be explicit when sharing hardcoded values such as
throttle/boost timeouts. Make it so!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use the correct destructor for freeing requests on error
Chris Wilson [Thu, 21 May 2015 20:01:45 +0000 (21:01 +0100)]
drm/i915: Use the correct destructor for freeing requests on error

After allocating from the slab cache, we then need to free the request
back into the slab cache upon error (and not call kfree as that leads
to eventual memory corruption).

Fixes regression from
commit efab6d8dd158fdccbe6a030f89fbf9ca0a9564e4
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Apr 7 16:20:57 2015 +0100

    drm/i915: Use a separate slab for requests

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: don't fail colorkey + scaler request
Chandra Konduru [Mon, 18 May 2015 23:18:44 +0000 (16:18 -0700)]
drm/i915/skl: don't fail colorkey + scaler request

There is a mplayer video failure reported with xv.
This is because there is a request to do both plane scaling
and colorkey. Because skl hw doesn't support plane scaling
and colorkey at the same time, request is failed which is expected
behavior.

To make xv operate, this patch allows colorkey continue to work
without using scaler. Then behavior would be similar to platforms
without plane scaler support.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90449
[danvet: change can_scale to bool as requested by Ville.]
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Enable GTT caching on gen8
Ville Syrjälä [Tue, 19 May 2015 17:32:57 +0000 (20:32 +0300)]
drm/i915: Enable GTT caching on gen8

GTT caching was disabled by default on gen8 due to not working with
big pages. Some information suggests that it got fixed, but still
GTT caching has been left disabled by default. Or could be it just
meant that the default was changed to off, and hence the problem
got solved.

Enable GTT caching in the hopes of some performance increase.
Whether or not the big pages issue has been fixed is irrelevant
at this stage since we don't use big pages.

This gives me a 1-2% improvement in xonotic on my BSW. Haven't tried
BDW, but supposedly it has larger TLBs so might not benefit as much.
On HSW GTT caching is enabled by default.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating()
Ville Syrjälä [Tue, 19 May 2015 17:32:56 +0000 (20:32 +0300)]
drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating()

GEN8_L3SQCREG1 isn't saved in the context (verified by going through
a context dump), and so we shouldn't be using the ring w/a code to
initialize it. Also Bspec explicitly talks about MMIO and writing it
with the CPU.

Additionally there's another w/a WaTempDisableDOPClkGating:bdw which
tells us to disable DOP clock gating around the GEN8_L3SQCREG1 write
to make sure everyone notices the change. So let's do that as well.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use ilk_init_lp_watermarks() on BDW
Ville Syrjälä [Tue, 19 May 2015 17:32:55 +0000 (20:32 +0300)]
drm/i915: Use ilk_init_lp_watermarks() on BDW

We're not using ilk_init_lp_watermarks() on BDW for some reason.
Probably due to the BDW patches and the relevant WM patches landing
roughlly at the same time. Fix it up.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Disable FDI RX/TX before the ports
Ville Syrjälä [Tue, 5 May 2015 14:17:38 +0000 (17:17 +0300)]
drm/i915: Disable FDI RX/TX before the ports

Bspec says we should disable the FDI RX/TX before disabling the PCH
ports. Do so.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Disable CRT port after pipe on PCH platforms
Ville Syrjälä [Tue, 5 May 2015 14:17:37 +0000 (17:17 +0300)]
drm/i915: Disable CRT port after pipe on PCH platforms

Follow the BSpec sequence for the CRT port as well on PCH platforms,
ie. disable the pipe before the port.

Didn't bother looking at DDI in detail yet, so leave that one be even
though the CRT is a PCH port there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Disable SDVO port after the pipe on PCH platforms
Ville Syrjälä [Tue, 5 May 2015 14:17:36 +0000 (17:17 +0300)]
drm/i915: Disable SDVO port after the pipe on PCH platforms

While at it also remove the redundant/unneeded w/a like done for hdmi
already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Mention that this also removes the unneeded w/a, as suggested
by Jesse.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Disable HDMI port after the pipe on PCH platforms
Ville Syrjälä [Tue, 5 May 2015 14:17:35 +0000 (17:17 +0300)]
drm/i915: Disable HDMI port after the pipe on PCH platforms

BSpec says we should disable all ports after the pipe on PCH
platforms. Do so. Fixes a pipe off timeout on ILK now caused by
the transcoder B workaround.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix the IBX transcoder B workarounds
Ville Syrjälä [Tue, 5 May 2015 14:17:34 +0000 (17:17 +0300)]
drm/i915: Fix the IBX transcoder B workarounds

Currently the IBX transcoder B workarounds are not working correctly.
Well, the HDMI one seems to be working somewhat, but the DP one is
definitely busted.

After a bit of experimentation it looks like the best way to make this
work is first disable the port on transcoder B, and then re-enable it
transcoder A, and immediately disable it again.

We can also clean up the code by noting that we can't be called without
a valid crtc. And also note that port A on ILK does not need the
workaround, so let's check for that one too.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Write the SDVO reg twice on IBX
Ville Syrjälä [Tue, 5 May 2015 14:17:33 +0000 (17:17 +0300)]
drm/i915: Write the SDVO reg twice on IBX

On IBX the SDVO/HDMI register write may be masked when enabling the
port, so it may need to written twice. The HDMI code does this, but
the SDVO code does not. Add the workaround to the SDVO code as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix DP enhanced framing for CPT
Ville Syrjälä [Tue, 5 May 2015 14:17:31 +0000 (17:17 +0300)]
drm/i915: Fix DP enhanced framing for CPT

Currently we're always enabling enhanced framing on CPT even if the sink
doesn't support it. Fix this up by actaully looking at what the sink
tells us.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Clean up the CPT DP .get_hw_state() port readout
Ville Syrjälä [Tue, 5 May 2015 14:17:30 +0000 (17:17 +0300)]
drm/i915: Clean up the CPT DP .get_hw_state() port readout

Define a TRANS_DP_PIPE_TO_PORT() to make the CPT DP .get_hw_state()
pipe readout neater.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Clarfify the DP code platform checks
Ville Syrjälä [Tue, 5 May 2015 14:17:29 +0000 (17:17 +0300)]
drm/i915: Clarfify the DP code platform checks

intel_dp.c is a mess with all the checks for different
platform/PCH variants and ports. Try to clean it up by recognizing
the following facts:
- IVB port A, and CPT port B/C/D are always the special cases
- VLV/CHV don't have port A
- Using the same kind of logic everywhere makes things much easier to
  parse

So let's move the IVB port A and PCH port B/C/D checks to be done first,
and let the other cases fall through, and always check for these things
using the same logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove the double register write from intel_disable_hdmi()
Ville Syrjälä [Tue, 5 May 2015 14:17:28 +0000 (17:17 +0300)]
drm/i915: Remove the double register write from intel_disable_hdmi()

IBX can have problems with the first write to the port register getting
masked when enabling the port. We are trying to apply the workaround
also when disabling the port where it's not needed, and we also try
to apply it for CPT/PPT as well which don't need it. Just kill it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Resolve conflict with the remove CHV if block.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi()
Ville Syrjälä [Tue, 5 May 2015 14:17:27 +0000 (17:17 +0300)]
drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi()

The IBX 12bpc port enable toggle is only relevant when enabling
the port, not when disabling it. Also this code doesn't actually
toggle anything, and essentially just writes the port register
one extra time. Furthermore CPT/PPT don't need such workarounds
and yet we include them. Just kill it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Deinit/init the display at suspend/resume
Damien Lespiau [Thu, 21 May 2015 15:37:48 +0000 (16:37 +0100)]
drm/i915/skl: Deinit/init the display at suspend/resume

We need to re-init the display hardware when going out of suspend. This
includes:

  - Hooking the PCH to the reset logic
  - Restoring CDCDLK
  - Enabling the DDB power

Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:

  - DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
    of supported frequencies. As eDP also uses DPLL0 for its link rate,
    once DPLL0 is on, we restrict the possible eDP link rates the chosen
    VCO.
  - CDCLK also limits the bandwidth available to push pixels.

So, as a first step, this commit restore what the BIOS set, until I can
do more testing.

In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:

  #include <stdio.h>
  #include <stdint.h>
  #include <assert.h>

  #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))

  static const struct dpll_freq {
          unsigned int freq;
          unsigned int decimal;
  } freqs[] = {
          { .freq = 308570, .decimal = 0b01001100111},
          { .freq = 337500, .decimal = 0b01010100001},
          { .freq = 432000, .decimal = 0b01101011110},
          { .freq = 450000, .decimal = 0b01110000010},
          { .freq = 540000, .decimal = 0b10000110110},
          { .freq = 617140, .decimal = 0b10011010000},
          { .freq = 675000, .decimal = 0b10101000100},
  };

  static void intbits(unsigned int v)
  {
          int i;

          for(i = 10; i >= 0; i--)
                  putchar('0' + ((v >> i) & 1));
  }

  static unsigned int freq_decimal(unsigned int freq /* in kHz */)
  {
          return (freq - 1000) / 500;
  }

  static void test_freq(const struct dpll_freq *entry)
  {
          unsigned int decimal = freq_decimal(entry->freq);

          printf("freq: %d, expected: ", entry->freq);
          intbits(entry->decimal);
          printf(", got: ");
          intbits(decimal);
          putchar('\n');

          assert(decimal == entry->decimal);
  }

  int main(int argc, char **argv)
  {
          int i;

          for (i = 0; i < ARRAY_SIZE(freqs); i++)
                  test_freq(&freqs[i]);

          return 0;
  }

v2:
  - Rebase on top of -nightly
  - Use (freq - 1000) / 500 for the decimal frequency (Ville)
  - Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
  - Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
    be consistent with the BXT code (Ville)
  - Store boot CDCLK in ddi_pll_init (Ville)
  - Merge dev_priv's skl_boot_cdclk into cdclk_freq
  - Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
  - Replace various '0' by SKL_DPLL0 to be a bit more explicit that
    we're programming DPLL0
  - Busy poll the PCU before doing the frequency change. It takes about
    3/4 cycles, each separated by 10us, to get the ACK from the CPU
    (Ville)

v3:
  - Restore dev_priv->skl_boot_cdclk, leaving unification with
    dev_priv->cdclk_freq for a later patch (Daniel, Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Free RPS boosts for all laggards
Chris Wilson [Mon, 27 Apr 2015 12:41:24 +0000 (13:41 +0100)]
drm/i915: Free RPS boosts for all laggards

If the client stalls on a congested request, chosen to be 20ms old to
match throttling, allow the client a free RPS boost.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: s/rq/req/]
[danvet: s/0/NULL/ reported by 0-day build]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Don't downclock whilst we have clients waiting for GPU results
Chris Wilson [Mon, 27 Apr 2015 12:41:23 +0000 (13:41 +0100)]
drm/i915: Don't downclock whilst we have clients waiting for GPU results

If we have clients stalled waiting for requests, ignore the GPU if it
signals that it should downclock due to low load. This helps prevent
the automatic timeout from causing extremely long running batches from
taking even longer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Convert RPS tracking to a intel_rps_client struct
Chris Wilson [Mon, 27 Apr 2015 12:41:22 +0000 (13:41 +0100)]
drm/i915: Convert RPS tracking to a intel_rps_client struct

Now that we have internal clients, rather than faking a whole
drm_i915_file_private just for tracking RPS boosts, create a new struct
intel_rps_client and pass it along when waiting.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: s/rq/req/]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Limit mmio flip RPS boosts
Chris Wilson [Mon, 27 Apr 2015 12:41:21 +0000 (13:41 +0100)]
drm/i915: Limit mmio flip RPS boosts

Since we will often pageflip to an active surface, we will often have to
wait for the surface to be written before issuing the flip. Also we are
likely to wait on that surface in plenty of time before the vblank.
Since we have a mechanism for boosting when a flip misses the expected
vblank, curtain the number of times we RPS boost when simply waiting for
mmioflip.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: s/rq/req/]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Limit ring synchronisation (sw sempahores) RPS boosts
Chris Wilson [Mon, 27 Apr 2015 12:41:20 +0000 (13:41 +0100)]
drm/i915: Limit ring synchronisation (sw sempahores) RPS boosts

Ring switches can occur many times per frame, and are often out of
control, causing frequent RPS boosting for no practical benefit. Treat
the sw semaphore synchronisation as a separate client and only allow it
to boost once per busy/idle cycle.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: s/rq/req/]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Inline check required for object syncing prior to execbuf
Chris Wilson [Mon, 27 Apr 2015 12:41:18 +0000 (13:41 +0100)]
drm/i915: Inline check required for object syncing prior to execbuf

This trims a little overhead from the common case of not needing to
synchronize between rings.

v2: execlists is special and likes to duplicate code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Implement inter-engine read-read optimisations
Chris Wilson [Mon, 27 Apr 2015 12:41:17 +0000 (13:41 +0100)]
drm/i915: Implement inter-engine read-read optimisations

Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls as we synchronise between rings -
greatly impacting the current performance of Broadwell versus Haswell in
certain workloads (like video decode). With the introduction of
reference counted requests, it is much easier to track the last request
per ring, as well as the last global write request so that we can
optimise inter-engine read read requests (as well as better optimise
certain CPU waits).

v2: Fix inverted readonly condition for nonblocking waits.
v3: Handle non-continguous engine array after waits
v4: Rebase, tidy, rewrite ring list debugging
v5: Use obj->active as a bitfield, it looks cool
v6: Micro-optimise, mostly involving moving code around
v7: Fix retire-requests-upto for execlists (and multiple rq->ringbuf)
v8: Rebase
v9: Refactor i915_gem_object_sync() to allow the compiler to better
optimise it.

Benchmark: igt/gem_read_read_speed
hsw:gt3e (with semaphores):
Before: Time to read-read 1024k: 275.794µs
After:  Time to read-read 1024k: 123.260µs

hsw:gt3e (w/o semaphores):
Before: Time to read-read 1024k: 230.433µs
After:  Time to read-read 1024k: 124.593µs

bdw-u (w/o semaphores):             Before          After
Time to read-read 1x1:            26.274µs       10.350µs
Time to read-read 128x128:        40.097µs       21.366µs
Time to read-read 256x256:        77.087µs       42.608µs
Time to read-read 512x512:       281.999µs      181.155µs
Time to read-read 1024x1024:    1196.141µs     1118.223µs
Time to read-read 2048x2048:    5639.072µs     5225.837µs
Time to read-read 4096x4096:   22401.662µs    21137.067µs
Time to read-read 8192x8192:   89617.735µs    85637.681µs

Testcase: igt/gem_concurrent_blit (read-read and friends)
Cc: Lionel Landwerlin <lionel.g.landwerlin@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v8]
[danvet: s/\<rq\>/req/g]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: s/\<rq\>/req/g
Daniel Vetter [Thu, 21 May 2015 12:21:25 +0000 (14:21 +0200)]
drm/i915: s/\<rq\>/req/g

The merged seqno->request conversion from John called request
variables req, but some (not all) of Chris' recent patches changed
those to just rq. We've had a lenghty (and inconclusive) discussion on
irc which is the more meaningful name with maybe at most a slight bias
towards req.

Given that the "don't change names without good reason to avoid
conflicts" rule applies, so lets go back to a req everywhere for
consistency. I'll sed any patches for which this will cause conflicts
before applying.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: John Harrison <John.C.Harrison@Intel.com>
[danvet: s/origina/merged/ as pointed out by Chris - the first
mass-conversion patch was from Chris, the merged one from John.]
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
Imre Deak [Tue, 19 May 2015 14:05:42 +0000 (17:05 +0300)]
drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent

v2:
- set the override disable flag too on stepping F0 (mika)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+
Imre Deak [Tue, 19 May 2015 14:05:41 +0000 (17:05 +0300)]
drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+

On B0 and C0 steppings the workaround enable bit would be overriden by
default, so the overriding must be disabled.

The WA was added in
commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3
Author: Nick Hoath <nicholas.hoath@intel.com>
Date:   Fri Apr 10 13:12:26 2015 +0100

    drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent

Spotted-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Force clean compilation with -Werror
Chris Wilson [Wed, 20 May 2015 13:12:47 +0000 (14:12 +0100)]
drm/i915: Force clean compilation with -Werror

Our driver compiles clean (nowadays thanks to 0day) but for me, at least,
it would be beneficial if the compiler threw an error rather than a
warning when it found a piece of suspect code. (I use this to
compile-check patch series and want to break on the first compiler error
in order to fix the patch.)

v2: Kick off a new "Debugging" submenu for i915.ko

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Add "DRM i915" to the menu name as requested by Chris.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Kill the dev variable in intel_suspend_complete()
Damien Lespiau [Wed, 20 May 2015 13:45:16 +0000 (14:45 +0100)]
drm/i915: Kill the dev variable in intel_suspend_complete()

The macros we use there are the magic ones that can take either dev or
dev_priv. We'd like to move as much as possible towards dev_priv though.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add a space after ', ' and don't capitalize mid-sentence
Damien Lespiau [Wed, 20 May 2015 13:45:15 +0000 (14:45 +0100)]
drm/i915: Add a space after ', ' and don't capitalize mid-sentence

Couldn't let it go!

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: Also add bxt_resume_prepare() to the S3/S4 path
Damien Lespiau [Wed, 20 May 2015 13:45:14 +0000 (14:45 +0100)]
drm/i915/bxt: Also add bxt_resume_prepare() to the S3/S4 path

Currently bxt_resume_prepare() is only used in the runtime-resume path.
Add it to the full S3/S4 path as well.

v2: Rebase on top of the vlv_resume_prepare() shuffling around

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Swapping 90 and 270 to be compliant with Xrandr
Sonika Jindal [Wed, 20 May 2015 08:10:48 +0000 (13:40 +0530)]
drm/i915/skl: Swapping 90 and 270 to be compliant with Xrandr

Since DRM_ROTATE is counter clockwise (which is compliant with Xrandr),
and HW rotation is clockwise, swapping 90/270 to work as expected from
userspace.

v2: Rebased

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update comment in clear_intel_crtc_state()
Ander Conselvan de Oliveira [Wed, 20 May 2015 06:03:27 +0000 (09:03 +0300)]
drm/i915: Update comment in clear_intel_crtc_state()

Explain why a few fields of the new pipe_config have their values
preserved, while the others are zeroed.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: add F0 stepping ID
Imre Deak [Tue, 19 May 2015 12:05:00 +0000 (15:05 +0300)]
drm/i915/skl: add F0 stepping ID

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A
Imre Deak [Tue, 19 May 2015 12:04:59 +0000 (15:04 +0300)]
drm/i915/bxt: limit WaDisableMaskBasedCammingInRCC to stepping A

Also make the WA comment consistent with the rest, where the stepping
info is not shown.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Tighten the exposure ARGB/ABGR 8888 formats
Damien Lespiau [Tue, 19 May 2015 11:29:16 +0000 (12:29 +0100)]
drm/i915: Tighten the exposure ARGB/ABGR 8888 formats

ARGB8888 is used for cursors on all platforms so we need to allow it
everywhere.

ABGR8888 is currently only honoured:
  - on VLV/CHV in sprite planes
  - on SKL+ for primary and sprite planes
so only allow it for those platforms.

Note that we only support ARGB8888/ABGR8888 on the primary plane for
SKL/BXT because we have in line of sight the pipe bottom color on those
platforms and because the primary plane programming on VLV/CHV doesn't
anything different for those formats today.

v2: Fix the logic to forbid the creation ABGR2101010 fbs (Ville)
v3: Still allow the creation of ARGB8888 fbs now that cursor planes use
    real fb objects (found by PRTS).

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix 'suspedn' typo
Damien Lespiau [Mon, 18 May 2015 18:53:48 +0000 (19:53 +0100)]
drm/i915: Fix 'suspedn' typo

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: Move around lane stagger calculation
Vandana Kannan [Wed, 13 May 2015 06:50:35 +0000 (12:20 +0530)]
drm/i915/bxt: Move around lane stagger calculation

Making lane stagger calculation common for HDMI and DP

v2: Imre's comments addressed
- Remove lane stagger from bxt_clk_div and make it a local variable in
ddi_pll_select

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: Port PLL programming BUN
Vandana Kannan [Wed, 13 May 2015 06:48:52 +0000 (12:18 +0530)]
drm/i915/bxt: Port PLL programming BUN

BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.

VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
Fast Clock = Desired Output / 2
VCO = Fast Clock * P1 * P2

Prop_coeff, int_coeff, and tdctargetcnt modified according to above
calculation.

BUN 2: Port PLLs require additional programming at certain frequencies -
DCO amplitude in PORT_PLL_10

Review comments from Siva which were addressed in the initial version of the
patch.
- Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
- Calculate for HDMI
- Correct values for vco = 5.4
- return in case of invalid vco range

v2: Imre's review comments addressed
- change dcoampovr_en to dcoampovr_en_h
- change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
- Correct lane stagger value for 324MHz
- Make coef common for HDMI and DP
- remove superfluous comments

v3: Imre's comments addressed
- Remove Prop_coeff, int_coeff, tdctargetcnt, dcoampovr_en, gain_ctl,
dcoampovr_en_h from bxt_clk_div and make them local variables.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> [v1]
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: add HAS_DP_MST feature test macro
Jani Nikula [Mon, 18 May 2015 14:10:01 +0000 (17:10 +0300)]
drm/i915: add HAS_DP_MST feature test macro

Be in line with other features that we have.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/dp: make link rate printing prettier
Jani Nikula [Mon, 18 May 2015 13:01:45 +0000 (16:01 +0300)]
drm/i915/dp: make link rate printing prettier

Turn

    [drm:intel_dp_print_rates] source rates: 162000,270000,540000,
    [drm:intel_dp_print_rates] sink rates: 162000,270000,
    [drm:intel_dp_print_rates] common rates: 162000,270000,

into

    [drm:intel_dp_print_rates] source rates: 162000, 270000, 540000
    [drm:intel_dp_print_rates] sink rates: 162000, 270000
    [drm:intel_dp_print_rates] common rates: 162000, 270000

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bxt: Update the Broxton PCI ids
Damien Lespiau [Fri, 15 May 2015 18:43:56 +0000 (19:43 +0100)]
drm/i915/bxt: Update the Broxton PCI ids

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Don't expose ARGB1555 on gen2/3
Damien Lespiau [Fri, 15 May 2015 18:06:03 +0000 (19:06 +0100)]
drm/i915: Don't expose ARGB1555 on gen2/3

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove ARBG/ABGR 2101010 on platform not supporting those formats
Damien Lespiau [Fri, 15 May 2015 18:06:01 +0000 (19:06 +0100)]
drm/i915: Remove ARBG/ABGR 2101010 on platform not supporting those formats

We just have have VLV and CHV sprites programming the hardware
differently for the ABGR2101010 so keep them working.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Remove the COMMON_PRIMARY_FORMATS defines
Damien Lespiau [Fri, 15 May 2015 18:06:00 +0000 (19:06 +0100)]
drm/i915: Remove the COMMON_PRIMARY_FORMATS defines

That define makes it hard to figure out what is the actual list of
formats at a glance. Expand it then.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use uninterruptible mutex_lock for userptr bo creation
Chris Wilson [Fri, 15 May 2015 10:42:21 +0000 (11:42 +0100)]
drm/i915: Use uninterruptible mutex_lock for userptr bo creation

Mika encountered one pathological scenario under X where acquiring all
the mm locks (required to insert a mmu notifier) was very slow, so slow
that by the time we tried to lock the struct_mutex with the usual call
to i915_mutex_lock_interruptible(), X's signal timer had fired causing
us to restart the ioctl (and so looped indefinitely).

While I suspect this is the result of another bug (something leaking mm
perhaps?) we can forgo the error checking and interuptible nature of the
lock here so we only have to pay the expense once and get on with it.
This does expose the userptr creation routine to a driver livelock
though by not being interruptible.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Init ret to avoid issues reported by PRTS.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Preserve ddi_pll_sel when allocating new pipe_config
Ander Conselvan de Oliveira [Fri, 15 May 2015 08:51:50 +0000 (11:51 +0300)]
drm/i915: Preserve ddi_pll_sel when allocating new pipe_config

When the modeset code is reached with a CRTC that only needs a flip, the
code that assigns PLLs is skipped. But since there is still a state swap
for that CRTC, the current PLL assignment needs to be preserved. I
missed the ddi_pll_sel field in the following commit, which causes
warnings in DDI platforms.

commit 4978cc93d9ac240b435ce60431aef24239b4c270
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Tue Apr 21 17:13:21 2015 +0300

    drm/i915: Preserve shared DPLL information in new pipe_config

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90410
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Dump some DPLL fields in pipe config debug
Tvrtko Ursulin [Thu, 14 May 2015 12:38:31 +0000 (13:38 +0100)]
drm/i915: Dump some DPLL fields in pipe config debug

v2: Split strings to 80 char, add ddi_pll_sel and fixed typo. (Damien Lespiau)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Don't overwrite (e)DP PLL selection on SKL
Ander Conselvan de Oliveira [Fri, 15 May 2015 10:34:29 +0000 (13:34 +0300)]
drm/i915: Don't overwrite (e)DP PLL selection on SKL

In the following commit, the place where the contents of dpll_hw_state
in crtc_state where zeroed was changed. Prior to that commit, it
happened when the new state was allocated, but now that happens just
before the call the .crtc_compute_clock() hook. The DP code for SKL,
however, sets up the (private) PLL in the encoder compute config
function that has already run by the time that memset() is reached,
causing the previous value to be lost.

This patch fixes the issue by moving the memset() down the call chain,
so that it is only called if the values in dpll_hw_state are going to be
updated.

commit 4978cc93d9ac240b435ce60431aef24239b4c270
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Tue Apr 21 17:13:21 2015 +0300

    drm/i915: Preserve shared DPLL information in new pipe_config

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90462
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reported-and-tested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bios: be more explicit about discarding iomem address space
Jani Nikula [Wed, 13 May 2015 12:34:05 +0000 (15:34 +0300)]
drm/i915/bios: be more explicit about discarding iomem address space

Add one explicit discard of __iomem address space qualifier in
validate_vbt(), and respect it otherwise. This adds clarity in the code,
and reduces the sparse warnings from the module to just one.

Quoting Daniel, "The vbt really is plain old memory. Except that it's
reserved in the e820 table as something special and hence treated as io
range by the kernel. But it is memory, hence casting away the __iomem is
imo the right approach."

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Output scaler related pipe config debug in a single line
Tvrtko Ursulin [Wed, 13 May 2015 15:51:08 +0000 (16:51 +0100)]
drm/i915: Output scaler related pipe config debug in a single line

Just so it is grouped logically in line with other data and makes a
rather verbose output a bit shorter.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chandra Konduru <chandra.konduru@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bios: abstract finding VBT in BIOS to a separate function
Jani Nikula [Wed, 13 May 2015 12:34:04 +0000 (15:34 +0300)]
drm/i915/bios: abstract finding VBT in BIOS to a separate function

Improve clarity. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bios: remove a redundant NULL pointer check
Jani Nikula [Wed, 13 May 2015 12:34:03 +0000 (15:34 +0300)]
drm/i915/bios: remove a redundant NULL pointer check

We never pass a non-NULL vbt to validate_vbt, and we can safely expect
the callers to not change.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Remove unnecessary local variables in skl_plane_ctl*()
Damien Lespiau [Fri, 15 May 2015 14:07:02 +0000 (15:07 +0100)]
drm/i915/skl: Remove unnecessary local variables in skl_plane_ctl*()

Ville noticed in another patch we we didn't need them at all, so remove
them. It's worth saying that it makes no difference to code generated as
gcc is clever enough to optimize it out.

v2: Remove 'break' after 'return' in switches (Ville)

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/dsi: add support for DSI PLL N1 divisor values
Jani Nikula [Wed, 13 May 2015 07:35:25 +0000 (10:35 +0300)]
drm/i915/dsi: add support for DSI PLL N1 divisor values

Currently DSI PLL N1 is hardcoded off. Make it possible to use it
later. This should have no functional changes for now.

v2: s/ffz(~(n))/ffs(n) - 1/ (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Documentation for CSR firmware
Animesh Manna [Wed, 13 May 2015 16:43:29 +0000 (22:13 +0530)]
drm/i915/skl: Documentation for CSR firmware

Added docbook info regarding context save and restore (CSR)
firmware support added from gen9 onwards to drive newly added
DMC (Display microcontroller) in display engine.

v1: Initial version as RFC.

v2: Used "DOC:" tag for csr description based on review comment from Daniel.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>