Markus Elfring [Thu, 20 Apr 2017 05:34:54 +0000 (07:34 +0200)]
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
The script "checkpatch.pl" pointed information out like the following.
* CHECK: Comparison to NULL could be written "!drvdata"
Thus adjust this expression.
* WARNING: Possible unnecessary 'out of memory' message
Thus remove such a statement here.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Wed, 19 Apr 2017 20:37:30 +0000 (22:37 +0200)]
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
Multiplications for the size determination of memory allocations
indicated that array data structures should be processed.
Thus use the corresponding function "devm_kcalloc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Wed, 19 Apr 2017 17:43:03 +0000 (19:43 +0200)]
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
Multiplications for the size determination of memory allocations
indicated that array data structures should be processed.
Thus use the corresponding function "kcalloc".
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
John Crispin [Mon, 23 Jan 2017 12:48:27 +0000 (13:48 +0100)]
reset: mediatek: Add MT2701 ethsys reset controller include file
Add the missing reset bits of the ethsys core to the mt2701-reset include
file, so that we can reference them from within a devicetree file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
John Crispin [Mon, 23 Jan 2017 12:48:26 +0000 (13:48 +0100)]
clk: mediatek: add mt2701 ethernet reset
The ethernet clock core has a reset register that is currently not exposed
to the user. Fix this by adding the missing registration code.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 22 Apr 2017 02:19:46 +0000 (19:19 -0700)]
Merge tag 'sunxi-clk-for-4.12-2' of https://git./linux/kernel/git/sunxi/linux into HEAD
Pull Allwinner clock changes, take 2 from Maxime Ripard:
A few minor bug and comment fixes, plus some fixes for the PRCM CCU driver
merged in the prior pull request
* tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
clk: sunxi-ng: use 1 as fallback for minimum multiplier
clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value
clk: sunxi-ng: fix PRCM CCU ir clk parent
Daniel Lezcano [Mon, 17 Apr 2017 17:19:25 +0000 (19:19 +0200)]
clk: hi6220: Add the hi655x's pmic clock
The hi655x multi function device is a PMIC providing regulators.
The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement
this clock in order to add it in the hi655x MFD and allow proper wireless
initialization.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
[sboyd@codeaurora.org: Remove clkdev usage]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Arnd Bergmann [Wed, 19 Apr 2017 17:44:56 +0000 (19:44 +0200)]
clk: ti: fix building without legacy omap3
When CONFIG_ATAGS or CONFIG_OMAP3 is disabled, we get a build error:
In file included from include/linux/clk-provider.h:15:0,
from drivers/clk/ti/clk.c:19:
drivers/clk/ti/clk.c: In function 'ti_clk_add_aliases':
drivers/clk/ti/clk.c:438:29: error: 'simple_clk_match_table' undeclared (first use in this function); did you mean 'simple_attr_write'?
Moving the match table down fixes it.
Fixes:
c17435c56bb1 ("clk: ti: add API for creating aliases automatically for simple clock types")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Arnd Bergmann [Wed, 19 Apr 2017 21:43:10 +0000 (23:43 +0200)]
clk: ti: fix linker error with !SOC_OMAP4
When none of the OMAP4-generation SoCs are enabled, we run into a link
error for am43xx/am43xx:
drivers/clk/ti/dpll.o: In function `of_ti_am3_dpll_x2_setup':
dpll.c:(.init.text+0xd8): undefined reference to `clkhwops_omap4_dpllmx'
This is easily fixed by adding another #ifdef.
While looking at the code, I also spotted another problem with the
assignment of hw_ops variable that is not used again later. I'm
changing this to setting clk_hw->ops instead, which I guess is what
was intended here.
Fixes:
473adbf4e028 ("clk: ti: dpll44xx: fix clksel register initialization")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Replaced fixes tag with correct one]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Tue, 18 Apr 2017 09:15:56 +0000 (11:15 +0200)]
clk: hi3620: Fix a typo in one variable name
The script "checkpatch.pl" pointed information out like the following.
CHECK: 'seperated' may be misspelled - perhaps 'separated'?
Thus rename the affected variable.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Tue, 18 Apr 2017 08:50:53 +0000 (10:50 +0200)]
clk: hi3620: Delete error messages for a failed memory allocation in two functions
The script "checkpatch.pl" pointed information out like the following.
WARNING: Possible unnecessary 'out of memory' message
Thus remove such statements here.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Tue, 18 Apr 2017 08:30:04 +0000 (10:30 +0200)]
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
* A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kcalloc".
This issue was detected by using the Coccinelle software.
* Replace the specification of a data type by a pointer dereference
to make the corresponding size determination a bit safer according to
the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Tue, 18 Apr 2017 08:12:32 +0000 (10:12 +0200)]
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
The script "checkpatch.pl" pointed information out like the following.
WARNING: Possible unnecessary 'out of memory' message
Thus remove such statements here.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Tue, 18 Apr 2017 08:15:19 +0000 (10:15 +0200)]
clk: hisilicon: Use devm_kmalloc_array() in hisi_clk_alloc()
* A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "devm_kmalloc_array".
This issue was detected by using the Coccinelle software.
* Replace the specification of a data type by a pointer dereference
to make the corresponding size determination a bit safer according to
the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Markus Elfring [Tue, 18 Apr 2017 07:25:47 +0000 (09:25 +0200)]
clk: hisilicon: Use kcalloc() in hisi_clk_init()
* A multiplication for the size determination of a memory allocation
indicated that an array data structure should be processed.
Thus use the corresponding function "kcalloc".
This issue was detected by using the Coccinelle software.
* Replace the specification of a data type by a pointer dereference
to make the corresponding size determination a bit safer according to
the Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kuninori Morimoto [Tue, 18 Apr 2017 02:20:03 +0000 (02:20 +0000)]
clk: cs2000: select 12.20 High Accuracy on LFRatioCfg
cs2000 can select Static/Dynamic ratio based Frequency Synthesizer
Mode, it can select 20.12 High Multiplier interpret for 32-bit
User Defined Ratio if Dynamic ratio mode. Otherwise it should select
12.20 High Accuracy mode.
Current cs2000 is supporting Static ratio mode only, so it should
select 12.20 High Accuracy mode, not 20.12 High Multiplier mode.
This patch fixes it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kuninori Morimoto [Tue, 18 Apr 2017 02:19:37 +0000 (02:19 +0000)]
clk: cs2000: tidyup DEVICE_CFG2 settings
DEVICE_CFG2 can select ratio from user defined ratio and LOCKCLK is
for it. But current driver sets fixed 0 value. This patch fixes it.
Note is that current cs2000 driver is using/supporting only ratio0
(= ch0) now.
DEVICE_CFG2 can select STATIC/DYNAMIC ratio mode, and current cs2000
driver is selecting STATIC mode, but it was not understandable on
current code. This patch also solve this issue.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kuninori Morimoto [Tue, 18 Apr 2017 02:18:19 +0000 (02:18 +0000)]
clk: cs2000: enable clock skipping mode
CLK_IN skipping mode allows the PLL to maintain lock even when the
CLK_IN signal has missing pulses for up to 20 ms (t CS) at a time.
This patch enables it
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stanimir Varbanov [Thu, 9 Feb 2017 15:20:30 +0000 (17:20 +0200)]
clk: qcom: add parent for venus core0 and core1 gdsc's
Make venus_gdsc parent of venus gdsc core0 and core1.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pierre-Louis Bossart [Mon, 20 Feb 2017 20:23:56 +0000 (14:23 -0600)]
clk: x86: add "mclk" alias for Baytrail/Cherrytrail
Due to timing requirements, TI and Conexant manage the audio
reference clock from their ASoC codec drivers using the "mclk"
string. This patch adds another lookup for the "pmc_plt_clk_3"
clock to avoid Intel-specific tests in those codec drivers and
use code as-is.
To avoid a leak, clk_add_alias() is not used in this patch.
Instead the lookup is created manually as part of the .probe()
step and dropped in the .remove() step.
"pmc_plt_clk_3" is used exclusively for audio on all known
Baytrail/CherryTrail designs and is e.g. routed on the MCLK
(pin 26) of the MinnowBoardMAX Turbot LSE connector.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Bharat Kumar Reddy Gooty [Mon, 20 Mar 2017 22:12:14 +0000 (18:12 -0400)]
clk: ns2: Correct SDIO bits
Corrected the bits for power and iso.
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes:
f7225a83 ("clk: ns2: add clock support for Broadcom Northstar 2 SoC")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Srinivas Kandagatla [Tue, 21 Mar 2017 10:12:59 +0000 (10:12 +0000)]
clk: qcom: clk-smd-rpm: fix rate for branch clks during handoff
rpm branch clk rate should requested as either 0 or 1 but not INT_MAX.
This patch fixes rate request for branch clocks during clk handoff.
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stefan Agner [Mon, 10 Apr 2017 21:00:14 +0000 (14:00 -0700)]
clk: imx7d: fix USDHC NAND clock
The USDHC NAND root clock is not gated by any CCM clock gate. Remove
the bogus gate definition.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Thomas Petazzoni [Mon, 17 Apr 2017 12:46:45 +0000 (14:46 +0200)]
clk: spear: fix ADC clock definition on SPEAr600
There is no SPEAr600 device named "adc". Instead, the description of the
ADC was recently added to the Device Tree, and the device name is
"
d820b000.adc", so we should associate the ADC gatable clock to this
device name.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kevin-CW Chen [Sat, 8 Apr 2017 01:20:30 +0000 (09:20 +0800)]
clk: mediatek: add clk support for MT6797
Add MT6797 clock support, include topckgen, apmixedsys, infracfg
and subsystem clocks
Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kevin-CW Chen [Sat, 8 Apr 2017 01:20:28 +0000 (09:20 +0800)]
dt-bindings: arm: mediatek: document clk bindings for MT6797
This patch adds the binding documentation for apmixedsys, imgsys,
infracfg, mmsys, topckgen, vdecsys and vencsys for MT6797.
Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 19 Apr 2017 16:16:59 +0000 (09:16 -0700)]
Merge branch 'clk-mt6797' into clk-next
* clk-mt6797:
clk: mediatek: add mt6797 clock IDs
Mars Cheng [Sat, 8 Apr 2017 01:20:29 +0000 (09:20 +0800)]
clk: mediatek: add mt6797 clock IDs
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Dong Aisheng [Tue, 11 Apr 2017 02:37:49 +0000 (10:37 +0800)]
clk: imx7d: add the missing ipg_root_clk
Add the missing ipg_root_clk which actually is already used by many
orphan clks in current tree.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Dong Aisheng [Tue, 11 Apr 2017 02:37:48 +0000 (10:37 +0800)]
clk: clk-imx7d: fix ahb clk definition
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200
used actually is for adc, not ahb. After fix, correct ocram_s_clk
parent accordingly as well.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Alexey Firago [Fri, 7 Apr 2017 09:12:24 +0000 (12:12 +0300)]
clk: vc5: Add support for IDT VersaClock 5P49V5935
Update IDT VersaClock 5 driver to support 5P49V5935. This chip has
two clock inputs (internal XTAL or external CLKIN), four fractional
dividers (FODs) and five clock outputs (four universal clock outputs
and one reference clock output at OUT0_SELB_I2C).
Current driver supports up to 2 FODs and up to 3 clock outputs. This
patch sets max number of supported FODs to 4 and max number of supported
clock outputs to 5.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Alexey Firago [Fri, 7 Apr 2017 09:12:23 +0000 (12:12 +0300)]
clk: vc5: Add bindings for IDT VersaClock 5P49V5935
IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either integrated crystal or from
external reference clock.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Alexey Firago [Fri, 7 Apr 2017 09:12:22 +0000 (12:12 +0300)]
clk: vc5: Add structure to describe particular chip features
Introduce vc5_chip_info structure to describe features of a particular
VC5 chip (id, number of FODs, number of outputs, flags).
For now flags are only used to indicate if chip has internal XTAL.
vc5_chip_info is set on probe from the matched of_device_id->data.
Also add defines to specify maximum number of FODs and clock outputs
supported by the driver.
With these changes it should be easier to extend driver to support
more VC5 models.
Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 19 Apr 2017 16:02:00 +0000 (09:02 -0700)]
Merge tag 'sunxi-clk-for-4.12' of https://git./linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches for 4.12 from Maxime Ripard:
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Display index when clock registration fails
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
clk: sunxi-ng: mult: Support PLL lock detection
clk: sunxi-ng: add support for PRCM CCUs
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: sun5i: Fix mux width for csi clock
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
clk: sunxi-ng: gate: Support common pre-dividers
Stephen Boyd [Mon, 17 Apr 2017 18:29:18 +0000 (11:29 -0700)]
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
Stephen Boyd [Mon, 17 Apr 2017 18:04:12 +0000 (11:04 -0700)]
Merge tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git./linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clock fixes for 4.11 from Maxime Ripard:
Two build errors fixes for the sunxi-ng drivers.
The two other patches fix random CPU crashes happening on the A33 since
CPUFreq has been enabled in 4.11.
* tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
Chen-Yu Tsai [Fri, 24 Mar 2017 08:33:07 +0000 (16:33 +0800)]
clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
We ignore the d1 and d2 dividers in the audio PLL, and force them to
1 (register value 0) at probe time. However the comment preceding the
audio PLL definition says we enforce the default value, which is not
the same.
Fix the preceding comment to match what we do in code.
Fixes:
b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Fri, 24 Mar 2017 08:33:06 +0000 (16:33 +0800)]
clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
In commit
2beaa601c849 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.
This patch fixes them to match their round_rate callbacks.
Fixes:
2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Fri, 24 Mar 2017 08:33:05 +0000 (16:33 +0800)]
clk: sunxi-ng: use 1 as fallback for minimum multiplier
A zero multiplier does not make sense for clocks.
Use 1 as the minimum when a multiplier minimum isn't specified.
Fixes:
2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Thu, 13 Apr 2017 02:13:53 +0000 (10:13 +0800)]
clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should mitigate the system
hangs observed after the introduction of cpufreq for the A33.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Thu, 13 Apr 2017 02:13:52 +0000 (10:13 +0800)]
clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
In common PLL designs, changes to the dividers take effect almost
immediately, while changes to the multipliers (implemented as
dividers in the feedback loop) take a few cycles to work into
the feedback loop for the PLL to stablize.
Sometimes when the PLL clock rate is changed, the decrease in the
divider is too much for the decrease in the multiplier to catch up.
The PLL clock rate will spike, and in some cases, might lock up
completely. This is especially the case if the divider changed is
the pre-divider, which affects the reference frequency.
This patch introduces a clk notifier callback that will gate and
then ungate a clk after a rate change, effectively resetting it,
so it continues to work, despite any possible lockups. Care must
be taken to reparent any consumers to other temporary clocks during
the rate change, and that this notifier callback must be the first
to be registered.
This is intended to fix occasional lockups with cpufreq on newer
Allwinner SoCs, such as the A33 and the H3. Previously it was
thought that reparenting the cpu clock away from the PLL while
it stabilized was enough, as this worked quite well on the A31.
On the A33, hangs have been observed after cpufreq was recently
introduced. With the H3, a more thorough test [1] showed that
reparenting alone isn't enough. The system still locks up unless
the dividers are limited to 1.
A hunch was if the PLL was stuck in some unknown state, perhaps
gating then ungating it would bring it back to normal. Tests
done by Icenowy Zheng using Ondrej's test firmware shows this
to be a valid solution.
[1] http://www.spinics.net/lists/arm-kernel/msg552501.html
Reported-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tobias Regnery [Mon, 10 Apr 2017 12:15:44 +0000 (14:15 +0200)]
clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
The ccu-sun9i-a80 driver uses the ccu_mult_ops struct, but unlike the other
users it doesen't select the corresponding Kconfig symbol under which the
struct is compiled in.
This results in the following link error with CONFIG_SUN9I_A80_CCU=y and
CONFIG_SUNXI_CCU_MULT=n:
drivers/built-in.o:(.data+0x2d638): undefined reference to 'ccu_mult_ops'
Fix this by explicitly selecting CONFIG_SUNXI_CCU_MULT like the other
users of the struct.
Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tobias Regnery [Mon, 27 Mar 2017 09:57:53 +0000 (11:57 +0200)]
clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
With CONFIG_RESET_CONTROLLER=n we get the following link error in the
sunxi-ng clk driver:
drivers/built-in.o: In function `sunxi_ccu_probe':
mux-core.c:(.text+0x12fe68): undefined reference to 'reset_controller_register'
mux-core.c:(.text+0x12fe68): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol 'reset_controller_register'
Fix this by adding the appropriate select statement.
Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Kuninori Morimoto [Tue, 11 Apr 2017 00:35:49 +0000 (00:35 +0000)]
clk: cs2000: use existing priv_to_dev() to getting struct device
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Michael Turquette [Wed, 12 Apr 2017 16:53:16 +0000 (18:53 +0200)]
Merge tag 'meson-clk-for-4.12' of git://github.com/BayLibre/clk-meson into clk-next
Pull AmLogic clk driver updates from Jerome Brunet:
2nd Amlogic clock driver update for 4.12:
* Protect against holes in onecell_data
* Fix divison by zero and overflow in the mpll driver
* Add audio clock divider driver for i2s clocks
* Add i2s and spdif master clocks
Michael Turquette [Wed, 12 Apr 2017 16:51:43 +0000 (18:51 +0200)]
Merge tag 'amlogic-clk' of git://git./linux/kernel/git/khilman/linux-amlogic into clk-next
Same great taste as the previous pull request, but now with 50% less DT
bikeshedding!
Amlogic clock driver updates for v4.12
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
Peter De Schrijver [Tue, 21 Mar 2017 10:16:26 +0000 (12:16 +0200)]
clk: aggregate return codes of notify chains
In case there are multiple notify chains for the same clocks (because they
were registered by different users), we need to propagate potential failure
of any single one of them to the caller. Otherwise we eg risk violating the
V/f curve when a notifier is used for DVFS.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Peter De Schrijver [Tue, 21 Mar 2017 13:20:31 +0000 (15:20 +0200)]
clk: add clk_possible_parents debugfs file
For validation purposes, it's often useful to be able to retrieve the list
of possible parents in userspace. Add a debugfs file for every clock which
has more than 1 possible parent.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
[sboyd@codeaurora.org: Remove useless cast from void and extra
newline]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Robin van der Gracht [Mon, 6 Mar 2017 08:13:43 +0000 (09:13 +0100)]
clk: imx: correct uart4_serial clock name in driver for i.MX6UL
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Stephen Boyd [Fri, 7 Apr 2017 19:21:33 +0000 (12:21 -0700)]
clk: zte: Mark pll config tables as const
These should be const.
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Shawn Guo [Tue, 21 Mar 2017 08:38:23 +0000 (16:38 +0800)]
clk: zte: add pll_vga clock for zx296718
It adds zx296718 pll_vga clock for VGA support, so that VGA device can
get required pixel rate from clock driver for different display mode.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Shawn Guo [Tue, 21 Mar 2017 08:38:22 +0000 (16:38 +0800)]
clk: zte: pd_bit is not 0 on zx296718
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field. The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Shawn Guo [Tue, 21 Mar 2017 08:38:21 +0000 (16:38 +0800)]
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.
While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Robin van der Gracht [Fri, 3 Mar 2017 14:14:05 +0000 (15:14 +0100)]
clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock
The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register.
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Robin van der Gracht <robin@protonic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Michael Turquette [Wed, 12 Apr 2017 16:51:01 +0000 (18:51 +0200)]
Merge tag 'tegra-for-4.12-clk' of git://git./linux/kernel/git/tegra/linux into clk-next
Pull Tegra clk driver updates from Thierry Reding:
This contains a bunch of fixes and cleanups, mostly to the Tegra210
clock driver.
* tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits)
clk: tegra: Don't reset PLL-CX if it is already enabled
clk: tegra: Add missing Tegra210 clocks
clk: tegra: Propagate clk_out_x rate to parent
clk: tegra: Fix build warnings on Tegra20/Tegra30
clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
clk: tegra: Add SATA seq input control
clk: tegra: Add Tegra210 special resets
clk: tegra: Rework pll_u
clk: tegra: Implement reset control reset
clk: tegra: Fix disable unused for clocks sharing enable bit
clk: tegra: Handle UTMIPLL IDDQ
clk: tegra: Add aclk
clk: tegra: Add super clock mux/divider
clk: tegra: Define Tegra210 DMIC clocks
clk: tegra: Fix constness for peripheral clocks
clk: tegra: Define Tegra210 DMIC sync clocks
clk: tegra: Add CEC clock
clk: tegra: Fix type for m field
clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation
clk: tegra: Don't warn for PLL defaults unnecessarily
...
Kuninori Morimoto [Wed, 5 Apr 2017 05:27:21 +0000 (14:27 +0900)]
cs-2000-cp: keep Reserved bit on each register
Thus CS2000 datasheet is indicating below, this patch
follows it.
WARNING: All "Reserved" registers must maintain their default
state to ensure proper functional operation.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Rajendra Nayak [Thu, 23 Mar 2017 07:43:40 +0000 (13:13 +0530)]
clk: qcom: msm8996: Fix the vfe1 powerdomain name
Fix a typo which caused both vfe0 and vfe1 powerdomains to be
named as vfe0.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Fixes:
7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Gabriel Fernandez [Thu, 16 Mar 2017 08:16:41 +0000 (09:16 +0100)]
clk: stm32f4: fix timeout management for pll and ready gate
Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.
Fixes:
861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Ray Jui [Wed, 5 Apr 2017 19:53:37 +0000 (12:53 -0700)]
clk: iproc: Remove redundant check
Remove the redundant check of 'rate' in the if statement of the
'pll_set_rate' function
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Fixes:
5fe225c105fd ("clk: iproc: add initial common clock support")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Michael Turquette [Wed, 12 Apr 2017 16:50:34 +0000 (18:50 +0200)]
Merge tag 'v4.12-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add pll_wait_lock for pll_enable
clk: rockchip: rename RK1108 to RV1108
dt-bindings: rk1108-cru: rename RK1108 to RV1108
clk: rockchip: mark some rk3368 core-clks as critical
clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
clk: rockchip: fix up rk3368 timer-ids
clk: rockchip: add rk3328 clk_mac2io_ext ID
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
Michael Turquette [Wed, 12 Apr 2017 16:49:36 +0000 (18:49 +0200)]
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
- Add IMR clocks for R-Car H3 and M3-W,
- Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add support for fixing up clock tables
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
clk: renesas: r8a7796: Reformat core clock table
clk: renesas: r8a7795: Reformat core clock table
clk: renesas: r8a7796: Correct name of watchdog clock
clk: renesas: r8a7795: Correct name of watchdog clock
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
clk: renesas: r8a7796: Add IMR clocks
clk: renesas: r8a7795: Add IMR clocks
Stephen Boyd [Wed, 5 Apr 2017 01:35:51 +0000 (18:35 -0700)]
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
Gabriel Fernandez [Thu, 16 Mar 2017 08:16:40 +0000 (09:16 +0100)]
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
...
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 1
Use divider table to exclude 0 and 1 values.
Fixes:
83135ad3c517 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Stephen Boyd [Tue, 4 Apr 2017 22:33:18 +0000 (15:33 -0700)]
Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-next
* 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm:
clk: ti: convert to use proper register definition for all accesses
clk: ti: dpll44xx: fix clksel register initialization
clk: ti: gate: export gate_clk_ops locally
clk: ti: divider: add driver internal API for parsing divider data
clk: ti: divider: convert TI divider clock to use its own data representation
clk: ti: mux: convert TI mux clock to use its internal data representation
clk: ti: drop unnecessary MEMMAP_ADDRESSING flag
clk: ti: omap4: cleanup unnecessary clock aliases
clk: ti: enforce const types on string arrays
clk: ti: move omap2_init_clk_clkdm under TI clock driver
clk: ti: add clkdm_lookup to the exported functions
clk: ti: use automatic clock alias generation framework
clk: ti: add API for creating aliases automatically for simple clock types
clk: ti: add support for automatic clock alias generation
clk: ti: remove un-used definitions from public clk_hw_omap struct
Leo Yan [Sat, 25 Mar 2017 18:23:15 +0000 (02:23 +0800)]
clk: hi6220: add debug APB clock
The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Icenowy Zheng [Fri, 7 Apr 2017 16:19:04 +0000 (00:19 +0800)]
clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value
The CLK_NUMBER value of PRCM CCU is wrongly set to (CLK_APB0_PWD + 1),
which prevented the IR mod clock from being set up.
Change it to (CLK_IR + 1) in order to correctly get IR mod set up.
Fixes:
cdb8b80b6093 ("clk: sunxi-ng: add support for PRCM CCUs")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Fri, 7 Apr 2017 16:19:03 +0000 (00:19 +0800)]
clk: sunxi-ng: fix PRCM CCU ir clk parent
The first parent of ir clk in PRCM CCU is wrongly written as "osc32K"
instead of "osc32k".
Change it to "osc32k".
Fixes:
cdb8b80b6093 ("clk: sunxi-ng: add support for PRCM CCUs")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Martin Blumenstingl [Sat, 1 Apr 2017 13:02:25 +0000 (15:02 +0200)]
clk: meson: mpll: use 64bit math in rate_from_params
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.
While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.
Fixes:
1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Martin Blumenstingl [Sat, 1 Apr 2017 13:02:24 +0000 (15:02 +0200)]
clk: meson: mpll: fix division by zero in rate_from_params
According to the public datasheet all register bits in HHI_MPLL_CNTL7,
HHI_MPLL_CNTL8 and HHI_MPLL_CNTL9 default to zero. On all GX SoCs these
seem to be initialized by the bootloader to some default value.
However, on my Meson8 board they are not initialized, leading to a
division by zero in rate_from_params as the math is:
(parent_rate * SDM_DEN) / ((SDM_DEN * 0) + 0)
According to the datasheet, the minimum n2 value is 4. The rate provided
by the clock when n2 is less than this minimum is unpredictable. In such
case, we report an error.
Although the rate_from_params function was only introduced recently the
original bug has been there for much longer. It was only exposed
recently when the MPLL clocks were added to the Meson8b clock driver.
Fixes:
1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Fri, 3 Mar 2017 11:40:15 +0000 (12:40 +0100)]
clk: meson: gxbb: add cts_i958 clock
This adds the cts_i958 clock to control the clock source of the spdif
output block. This mux is not explicitly mentionned in the documentation
but it is critical to the spdif dai. It is used to select whether the clock
source of the spdif output is cts_amclk (when data are taken from i2s
buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer)
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Mon, 20 Feb 2017 17:02:34 +0000 (18:02 +0100)]
clk: meson: gxbb: add cts_mclk_i958
Add the spdif master clock also referred as cts_mclk_i958
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Tue, 24 Jan 2017 17:35:23 +0000 (18:35 +0100)]
clk: meson: gxbb: add cts_amclk
Add the i2s master clock also referred as cts_amclk
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Mon, 13 Feb 2017 23:13:55 +0000 (00:13 +0100)]
clk: meson: add audio clock divider support
The audio divider needs a specific clock divider driver.
With am mpll parent clock, which is able to provide a fairly precise rate,
the generic divider tends to select low value of the divider. In such case
the quality of the clock is very poor. For the same final rate, maximizing
the audio clock divider value and selecting the corresponding mpll rate
gives better results. This is what this driver aims to acheive. So far, so
good.
Cc: Hendrik v. Raven <hendrik@consetetur.de>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Tue, 28 Mar 2017 08:47:22 +0000 (10:47 +0200)]
clk: meson: gxbb: protect against holes in the onecell_data array
The clock controller is getting more complex and it might be possible, in
the future, to have holes in the clk_hw_onecell_data array. Just make sure
we skip those holes if it ever happens.
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Fri, 31 Mar 2017 10:14:17 +0000 (12:14 +0200)]
MAINTAINERS: Add maintainers for the meson clock driver
Suggested-by: Michael Turquette <mturquette@baylibre.com>
Cc: Kevin Hilman <khilman@baylibre.com>,
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Priit Laes [Wed, 5 Apr 2017 16:52:27 +0000 (19:52 +0300)]
clk: sunxi-ng: Display index when clock registration fails
Add clock index to clock registration failure message. Clock name
is sometimes not available, when things go really wrong.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Wed, 5 Apr 2017 06:37:44 +0000 (14:37 +0800)]
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks.
It is a clock multiplier, with the effective multiplier in the
range of 12 ~ 255 and no offset between the multiplier value and
the value programmed into the register.
Implement the zero offset and minimum value of 12 for this clock.
Fixes:
d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Wed, 5 Apr 2017 06:37:43 +0000 (14:37 +0800)]
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
The CPU cluster PLLs on the A80 are NP clocks that are atypical in two ways:
- The P factor is 1 bit wide, and translates to a /1 or /4 divider.
- The P factor should only be used for output frequencies lower than
288 MHz. The N factor has a lower limit of 12, which likely contributed
to this extra divider.
According to the user manual, the clocks can only go as low as 200 MHz.
The vendor BSP kernel does not even define operating points below 360
MHz for these clocks. The lower end for cpufreq in the vendor kernel is
even higher. The mainline Linux kernel doesn't support cpufreq for the
A80 at the moment. This means the lower frequencies are untested, and
will likely remain unused.
The new sunxi-ng style clocks don't support the quirks listed above.
Instead of trying to work the quirks in for something of little usage,
we re-model the clocks into N-type multipler clocks, with P fixed at 1.
At probe time we check if P is set to 4, and fix it up if needed. This
is highly unlikely though.
Fixes:
b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Wed, 5 Apr 2017 06:37:42 +0000 (14:37 +0800)]
clk: sunxi-ng: mult: Support PLL lock detection
Some PLL clocks are N (multiplier) type clocks, or can be simplified
as such. An example of the former is the DDR1 PLL clock on the A33.
An example of the latter is the CPU PLL clock on the A80, in which
the P divider is only used for low frequencies that are of little
use. Both clocks support PLL lock detection.
The mult clock macro implies support for this, but that is not true.
The field is simply discarded. This patch adds proper support for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Kevin Hilman [Tue, 4 Apr 2017 22:58:11 +0000 (15:58 -0700)]
Merge branch 'v4.12/clk-drivers' into v4.12/clk
* v4.12/clk-drivers:
clk: meson-gxbb: Add GXL/GXM GP0 Variant
clk: meson-gxbb: Add GP0 PLL init parameters
clk: meson: Add support for parameters for specific PLLs
clk: meson-gxbb: Add MALI clocks
clk: meson: mpll: correct N2 maximum value
clk: meson8b: add the mplls clocks 0, 1 and 2
clk: meson: gxbb: mpll: use rw operation
clk: meson: mpll: add rw operation
clk: gxbb: put dividers and muxes in tables
clk: meson8b: put dividers and muxes in tables
clk: meson: add missing const qualifiers on gate arrays
clk: meson: fix SET_PARM macro
Neil Armstrong [Wed, 22 Mar 2017 10:32:25 +0000 (11:32 +0100)]
clk: meson-gxbb: Add GXL/GXM GP0 Variant
The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM
SoCs embeds a different GP0 PLL, and needs different parameters with a vendor
provided reduced rate table.
This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order
to use the GXL GP0 PLL instead of the GXBB specific one.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-4-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:32:24 +0000 (11:32 +0100)]
clk: meson-gxbb: Add GP0 PLL init parameters
Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be
initializated in the the GP0 control registers before configuring the rate
with the rate table provided parameters.
GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-3-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:32:23 +0000 (11:32 +0100)]
clk: meson: Add support for parameters for specific PLLs
In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific
parameters in order to initialize and lock correctly.
This patch adds an optional PARAM table used to initialize the PLL to a
default value with it's parameters in order to achieve to desired frequency.
The GP0 PLL in GXBB, GXL/GXM also needs some tweaks in the initialization
steps, and these are exposed along the PARAM table.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-2-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:18:54 +0000 (11:18 +0100)]
clk: meson-gxbb: Add MALI clocks
The Mali is clocked by two identical clock paths behind a glitch free mux
to safely change frequency while running.
The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate.
Expose these two clocks trees using generic clocks.
Finally the glitch free mux is added as "mali" clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490177935-9646-3-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:32:27 +0000 (11:32 +0100)]
dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-6-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:32:26 +0000 (11:32 +0100)]
clk: meson-gxbb: Expose GP0 dt-bindings clock id
This patch exposes the GP0 PLL clock id in the dt bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490178747-14837-5-git-send-email-narmstrong@baylibre.com
Neil Armstrong [Wed, 22 Mar 2017 10:18:53 +0000 (11:18 +0100)]
clk: meson-gxbb: Add MALI clock IDS
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
1490177935-9646-2-git-send-email-narmstrong@baylibre.com
Jerome Brunet [Thu, 9 Mar 2017 10:41:54 +0000 (11:41 +0100)]
dt-bindings: clk: gxbb: expose i2s output clock gates
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
20170309104154.28295-10-jbrunet@baylibre.com
Icenowy Zheng [Tue, 4 Apr 2017 09:50:57 +0000 (17:50 +0800)]
clk: sunxi-ng: add support for PRCM CCUs
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H3/5 and A64 now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Icenowy Zheng [Tue, 4 Apr 2017 09:50:56 +0000 (17:50 +0800)]
dt-bindings: update device tree binding for Allwinner PRCM CCUs
Many Allwinner SoCs after A31 have a CCU in PRCM block.
Give the ones on H3 and A64 compatible strings.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Jon Hunter [Mon, 27 Mar 2017 11:01:05 +0000 (12:01 +0100)]
clk: tegra: Don't reset PLL-CX if it is already enabled
Commit
8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults
unnecessarily") changed the tegra210_pllcx_set_defaults() function
causing the PLL to always be reset regardless of whether it is in-use.
This function was changed so that resetting of the PLL will only be
skipped if the PLL is enabled AND 'pllcx->params->defaults_set' is not
true. However, the 'pllcx->params->defaults_set' is always true and
hence, the PLL is now always reset. This causes the boot to fail on the
Tegra210 Smaug where the PLL is already enabled and in-use. Fix this by
only resetting the PLL if not in-use and only printing the warning that
the defaults are not set after we have checked the default settings.
Fixes:
8dce89a1c2cf ("clk: tegra: Don't warn for PLL defaults unnecessarily")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Peter De Schrijver [Wed, 22 Mar 2017 14:23:16 +0000 (16:23 +0200)]
clk: tegra: Add missing Tegra210 clocks
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp
and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Alex Frid [Wed, 22 Mar 2017 13:38:19 +0000 (15:38 +0200)]
clk: tegra: Propagate clk_out_x rate to parent
Given that externx can only be used as a parent for clk_out_x, it makes
sense to propagate requests to make clk_out_x easier to handle.
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Gabriel Fernandez [Thu, 16 Mar 2017 08:16:40 +0000 (09:16 +0100)]
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
...
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 1
Use divider table to exclude 0 and 1 values.
Fixes:
83135ad3c517 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Geert Uytterhoeven [Fri, 10 Mar 2017 11:13:37 +0000 (12:13 +0100)]
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28.
Add support for that, but retain the old behavior for R-Car H3 ES1.x and
M3-W ES1.0 using a quirk.
Inspired by a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Geert Uytterhoeven [Thu, 29 Sep 2016 12:36:11 +0000 (14:36 +0200)]
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Thu, 29 Sep 2016 11:06:15 +0000 (13:06 +0200)]
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as
listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3
Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Thu, 29 Sep 2016 12:47:58 +0000 (14:47 +0200)]
clk: renesas: cpg-mssr: Add support for fixing up clock tables
The same SoC may have different clocks and/or module clock parents,
depending on SoC revision. One option is to use different sets of clock
tables for each SoC revision. However, if the differences are small, it
is much more space-efficient to have a single set of clock tables, and
fix those up at runtime instead.
Hence provide three helpers:
- Two helpers to NULLify core and module clocks that do not exist on
some revisions (NULLified clocks are skipped during the registration
phase),
- One helper to reparent module clocks that have different clock
parents.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jerome Brunet [Thu, 9 Mar 2017 10:41:53 +0000 (11:41 +0100)]
clk: meson: mpll: correct N2 maximum value
Gxbb datasheet says N2 maximum value is 127 but the register field is
9 bits wide, the maximum value should 511.
Test shows value greater than 127, all the way to 511, works well
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
20170309104154.28295-9-jbrunet@baylibre.com
Jerome Brunet [Thu, 9 Mar 2017 10:41:52 +0000 (11:41 +0100)]
clk: meson8b: add the mplls clocks 0, 1 and 2
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/
20170309104154.28295-8-jbrunet@baylibre.com