Dave Airlie [Mon, 16 May 2011 01:53:27 +0000 (11:53 +1000)]
Merge remote branch 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next into drm-core-next
* 'nouveau/drm-nouveau-next' of /ssd/git/drm-nouveau-next: (55 commits)
drm/nouveau: make cursor_set implementation consistent with other drivers
drm/nva3/clk: better pll calculation when no fractional fb div available
drm/nouveau/pm: translate ramcfg strap through ram restrict table
drm/nva3/pm: allow use of divisor 16
drm/nvc0/pm: parse clock for pll 0x0a (0x137020) from perf table
drm/nvc0/pm: correct core/mem/shader perflvl parsing
drm/nouveau/pm: remove memtiming support check when assigning to perflvl
drm/nva3: support for memory timing map table
drm/nouveau: Associate memtimings with performance levels on cards <= nv98
drm/nva3/pm: initial pass at set_clock() hook
drm/nvc0/gr: calculate some more of our magic numbers
drm/nv50: respect LVDS link count from EDID on SPWG panels
drm/nouveau: recognise DCB connector type 0x41 as LVDS
drm/nouveau: fix uninitialised variable warning
drm/nouveau: Fix a crash at card takedown for NV40 and older cards
drm/nouveau: Free nv04 instmem ramin heap at card takedown
drm/nva3: somewhat improve clock reporting
drm/nouveau: pull refclk from vbios on limits 0x40 boards
drm/nv40/gr: oops, fix random bits getting set in engine obj
drm/nv50: improve nv50_pm_get_clock()
...
Marcin Slusarz [Sun, 1 May 2011 21:49:04 +0000 (23:49 +0200)]
drm/nouveau: make cursor_set implementation consistent with other drivers
When xorg state tracker wants to hide the cursor it calls set_cursor
with NULL buffer_handle and size=0x0, but nouveau refuses to hide it
because size is not 64x64... which is a bit odd. Both radeon and intel
check buffer_handle before validating size of cursor, so make nouveau
implementation consistent with them.
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 27 Apr 2011 16:34:21 +0000 (02:34 +1000)]
drm/nva3/clk: better pll calculation when no fractional fb div available
The core/mem/shader clocks don't support the fractional feedback divider,
causing our calculated clocks to be off by quite a lot in some cases. To
solve this we will switch to a search-based algorithm when fN is NULL.
For my NVA8 at PL3, this actually generates identical cooefficients to
the binary driver. Hopefully that's a good sign, and that does not
break VPLL calculation for someone..
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 20 Apr 2011 04:36:13 +0000 (14:36 +1000)]
drm/nouveau/pm: translate ramcfg strap through ram restrict table
Hopefully this is how we're supposed to correctly handle when the RAMCFG
strap is above the number of entries in timing-related tables.
It's rather difficult to confirm without finding a configuration where
the ram restrict table doesn't map 8-15 back onto 0-7 anyway. There's
not a single vbios in the repo which is configured differently..
In any case, this is probably still better than potentially reading
outside of the bounds of various tables..
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 20 Apr 2011 04:15:49 +0000 (14:15 +1000)]
drm/nva3/pm: allow use of divisor 16
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 20 Apr 2011 03:21:40 +0000 (13:21 +1000)]
drm/nvc0/pm: parse clock for pll 0x0a (0x137020) from perf table
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 20 Apr 2011 03:15:02 +0000 (13:15 +1000)]
drm/nvc0/pm: correct core/mem/shader perflvl parsing
We need to parse some of these other entries still, but I've yet to
determine exactly which PLLs the rest map to.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 20 Apr 2011 01:34:39 +0000 (11:34 +1000)]
drm/nouveau/pm: remove memtiming support check when assigning to perflvl
Really not necessary here, we want to be able to see if/how we managed to
match a timingset to a performance level, even if we can't currently
program it.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 20 Apr 2011 01:31:04 +0000 (11:31 +1000)]
drm/nva3: support for memory timing map table
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Martin Peres [Wed, 13 Apr 2011 22:46:19 +0000 (00:46 +0200)]
drm/nouveau: Associate memtimings with performance levels on cards <= nv98
v2 (Ben Skeggs): fix ramcfg strap, and remove bogus handling of perf 0x40
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 15 Apr 2011 01:16:55 +0000 (11:16 +1000)]
drm/nva3/pm: initial pass at set_clock() hook
I still discourage anyone from actually doing this yet.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 18 Apr 2011 02:52:47 +0000 (12:52 +1000)]
drm/nvc0/gr: calculate some more of our magic numbers
Again, doesn't quite match NVIDIA's, but not sure it really matters. This
will however, match the same rules we use to calculate the other related
grctx magics.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 18 Apr 2011 00:49:03 +0000 (10:49 +1000)]
drm/nv50: respect LVDS link count from EDID on SPWG panels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Sun, 17 Apr 2011 23:57:48 +0000 (09:57 +1000)]
drm/nouveau: recognise DCB connector type 0x41 as LVDS
After looking at a number of different logs, it appears 0x41 likely
indicates the presense of an LVDS panel following the SPWG spec
(http://www.spwg.org/)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Sun, 17 Apr 2011 22:57:51 +0000 (08:57 +1000)]
drm/nouveau: fix uninitialised variable warning
Looks like a false positive to me, but, anyways!
Reported-by: Jimmy Rentz <jb17bsome@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Jimmy Rentz [Sun, 17 Apr 2011 20:15:09 +0000 (16:15 -0400)]
drm/nouveau: Fix a crash at card takedown for NV40 and older cards
NV40 and older cards (pre NV50) reserve a vram bo for the vga memory at
card init. This bo is then freed at card shutdown. The problem is that
the ttm bo vram manager was already freed. So a crash occurs when the
vga bo is freed. The fix is to free the vga bo prior to freeing the ttm
bo vram manager. There might be other solutions but this seemed the
simplest to me.
Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Jimmy Rentz [Sun, 17 Apr 2011 20:15:03 +0000 (16:15 -0400)]
drm/nouveau: Free nv04 instmem ramin heap at card takedown
Add a missing nv04 instmem ramin heap shutdown call.
Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 14 Apr 2011 05:02:03 +0000 (15:02 +1000)]
drm/nva3: somewhat improve clock reporting
Definitely not 100% correct, but, for the configurations I've seen used
it'll read back the correct clocks now.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 14 Apr 2011 01:25:26 +0000 (11:25 +1000)]
drm/nouveau: pull refclk from vbios on limits 0x40 boards
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 13 Apr 2011 08:33:15 +0000 (18:33 +1000)]
drm/nv40/gr: oops, fix random bits getting set in engine obj
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Emil Velikov [Mon, 11 Apr 2011 19:43:23 +0000 (20:43 +0100)]
drm/nv50: improve nv50_pm_get_clock()
Many of the nv50 cards have their shader and/or memory pll
disabled at some stage.
This patch addresses those cases, so that the function
returns the correct frequency.
When the shader pll is disabled, the blob reports 2*core clock
Whereas for memory, the data stored in the vbios. This action
is incorrect as some vbioses store a clock value that is less
than the refference clock of the pll.
Thus we are reporting the reff_clk as it is the frequency the
pll actually operates
v2 - Convert NV_INFO() messages to NV_DEBUG()
Provide more information in the actuall message
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Martin Peres [Mon, 11 Apr 2011 22:55:44 +0000 (00:55 +0200)]
drm/nouveau/pm: fix compilation failure when CONFIG_POWER_SUPPLY is not set
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Reported-by: Stratos Psomadakis <psomas@ece.ntua.gr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 13 Apr 2011 03:55:17 +0000 (13:55 +1000)]
drm/nvc0/fifo: stick user area into a gpuobj rather than a bo
Contents will now be preserved across a suspend, unlike a pinned bo
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 13 Apr 2011 02:55:36 +0000 (12:55 +1000)]
drm/nvc0/gr: no need to store context in graph_fini()
PFIFO kickoff should have handled this for us.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Tue, 12 Apr 2011 09:38:06 +0000 (19:38 +1000)]
drm/nvc0/fifo: restore context table on resume
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Tue, 12 Apr 2011 08:51:39 +0000 (18:51 +1000)]
drm/nvc0/fifo: kick channels off during suspend
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Tue, 12 Apr 2011 08:50:36 +0000 (18:50 +1000)]
drm/nvc0/gr: better handling of fuc firmware
Allows per-chipset firmware to be installed, and keeps a copy in memory
for suspend/resume purposes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Tue, 12 Apr 2011 05:20:22 +0000 (15:20 +1000)]
drm/nv50: support PMPEG on original nv50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Tue, 12 Apr 2011 05:19:54 +0000 (15:19 +1000)]
drm/nv50: rename nv84_mpeg to nv50_mpeg
In preparation for adding 0x50 support.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 4 Apr 2011 06:10:00 +0000 (16:10 +1000)]
drm/nv84: add support for PMPEG
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 4 Apr 2011 06:08:24 +0000 (16:08 +1000)]
drm/nv40/vpe: add support for PMPEG
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 06:10:08 +0000 (16:10 +1000)]
drm/nvc0: implement support for copy engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 18 Mar 2011 00:25:59 +0000 (10:25 +1000)]
drm/nva3: implement support for copy engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 03:56:05 +0000 (13:56 +1000)]
drm/nouveau: remove remnants of nouveau_pgraph_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 03:26:35 +0000 (13:26 +1000)]
drm/nouveau: fix suspend failure path to reinitialise all engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 03:17:25 +0000 (13:17 +1000)]
drm/nouveau: remove remnants of nouveau_pgraph_engine from nouveau_channel
The nouveau_wait_for_idle() call should hopefully not have been actually
necessary, we *do* wait for the channel to go idle already. If it's
an issue somehow, the chipset-specific hooks can wait for idle themselves
before taking the lock.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 03:10:45 +0000 (13:10 +1000)]
drm/nouveau: move set_tile_region to nouveau_exec_engine
In the very least VPE (PMPEG and friends) also has this style of tile
region regs, lets make them just work if/when they get added.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 03:03:56 +0000 (13:03 +1000)]
drm/nv04/gr: move to exec engine interfaces
Like nv10-nv50, needs cleanup.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 02:50:55 +0000 (12:50 +1000)]
drm/nv10/gr: move to exec engine interfaces
Like nv20-nv50, needs cleanup.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 02:32:03 +0000 (12:32 +1000)]
drm/nv20-nv30/gr: move to exec engine interface
A bit of cleanup done along the way, but, like nv40/nv50, needs more.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 01:33:21 +0000 (11:33 +1000)]
drm/nv40/gr: move to exec engine interfaces
Like nv50, this needs a good cleanup.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Fri, 1 Apr 2011 00:59:53 +0000 (10:59 +1000)]
drm/nvc0/gr: move to exec engine interfaces
Much nicer to do that nv50, the code was pretty much written to expect
such a change in the future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 31 Mar 2011 23:50:18 +0000 (09:50 +1000)]
drm/nv50/gr: move to exec engine interfaces
This needs a massive cleanup, but to catch bugs from the interface changes
vs the engine code cleanup, this will be done later.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 31 Mar 2011 05:40:43 +0000 (15:40 +1000)]
drm/nouveau: working towards a common way to represent engines
There's lots of more-or-less independant engines present on NVIDIA GPUs
these days, and we generally want to perform the same operations on them.
Implementing new ones requires hooking into lots of different places,
the aim of this work is to make this simpler and cleaner.
NV84:NV98 PCRYPT moved over as a test.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 31 Mar 2011 03:55:49 +0000 (13:55 +1000)]
drm/nouveau: remove some unused members from dev_priv
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 31 Mar 2011 03:44:16 +0000 (13:44 +1000)]
drm/nouveau: move engine object creation into per-engine hooks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 31 Mar 2011 00:39:44 +0000 (10:39 +1000)]
drm/nouveau: use static vidshift of 2 on volt 0x30 tables
Explanation is in the commit. If anyone has an example of where this is
*not* the case, please report it!
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Roy Spliet [Sun, 27 Mar 2011 16:13:11 +0000 (18:13 +0200)]
drm/nouveau: improve memtiming table parsing
Improves the parsing of the memory timing table on NV50-NV98revA1 chipsets.
Added stepping to drm_nouveau_private to make sure newer NV98 (105M) is
zero rather than incorrect.
Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 28 Mar 2011 23:28:24 +0000 (09:28 +1000)]
drm/nvc0: decode gpc/hubclient on vm fault
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 28 Mar 2011 22:57:34 +0000 (08:57 +1000)]
drm/nvc0: more vm fault reasons
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Mon, 28 Mar 2011 14:52:59 +0000 (00:52 +1000)]
drm/nvc0: more vm fault engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Emil Velikov [Sat, 19 Mar 2011 23:31:54 +0000 (23:31 +0000)]
drm/nouveau: Fix missing whitespace checkpatch.pl errors.
This patch fixes messages such as
ERROR: space required after that ','
ERROR: spaces required around that '='
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Emil Velikov [Sat, 19 Mar 2011 23:31:53 +0000 (23:31 +0000)]
drm/nouveau: Fix brace placement checkpatch.pl errors.
Fix 'ERROR: that open brace { should be on the previous line'
Fix 'ERROR: else should follow close brace }'
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Emil Velikov [Sat, 19 Mar 2011 23:31:52 +0000 (23:31 +0000)]
drm/nouveau: Clean up trailing whitespace and C99-style comments.
Fix 'ERROR: trailing whitespace',
Fix 'ERROR: do not use C99 // comments'
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Emil Velikov [Sat, 19 Mar 2011 23:31:51 +0000 (23:31 +0000)]
drm/nouveau: Fix indentation-related checkpatch.pl error messages.
Fix 'ERROR: code indent should use tabs where possible'
Fix 'ERROR: space required before the open parenthesis ('
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Martin Peres [Sat, 19 Mar 2011 21:44:35 +0000 (22:44 +0100)]
drm/nouveau: name the boot perflvl "boot"
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Dave Airlie [Mon, 16 May 2011 00:45:40 +0000 (10:45 +1000)]
Merge remote branch 'keithp/drm-intel-next' of /ssd/git/drm-next into drm-core-next
* 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits)
drm/i915: split PCH clock gating init
drm/i915: add Ivybridge clock gating init function
drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.
drm/i915: Add support for fence registers on Ivybridge.
drm/i915: Use existing function instead of open-coding fence reg clear.
drm/i915: split clock gating init into per-chipset functions
drm/i915: set IBX pch type explicitly
drm/i915: add Ivy Bridge PCI IDs and driver feature structs
drm/i915: add PantherPoint PCH ID
agp/intel: add Ivy Bridge support
drm/i915: ring support for Ivy Bridge
drm/i915: page flip support for Ivy Bridge
drm/i915: interrupt & vblank support for Ivy Bridge
drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
drm/i915: manual FDI training for Ivy Bridge
drm/i915: add swizzle/tiling support for Ivy Bridge
drm/i915: Ivy Bridge has split display and pipe control
drm/i915: add IS_IVYBRIDGE macro for checks
drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
drm/i915: split enable/disable vblank code into chipset specific functions
...
Jesse Barnes [Wed, 11 May 2011 16:49:31 +0000 (09:49 -0700)]
drm/i915: split PCH clock gating init
Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 11 May 2011 16:42:30 +0000 (09:42 -0700)]
drm/i915: add Ivybridge clock gating init function
Some of the bits have changed, including one we were setting that enables
a VGA test mode, preventing pipe B from working at all. So add a new
IVB specific function with the right bits.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Eric Anholt [Sat, 7 May 2011 00:12:35 +0000 (17:12 -0700)]
drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.
They have been moved from the ringbuffer groups to their own group it
looks like. Fixes GPU hangs on gnome startup.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Eric Anholt [Fri, 6 May 2011 20:55:53 +0000 (13:55 -0700)]
drm/i915: Add support for fence registers on Ivybridge.
The registers are the same as on Sandybridge. Fixes scrambled display
in X when it does software drawing to the GTT, and scans the results
out as tiled.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Eric Anholt [Fri, 6 May 2011 20:53:49 +0000 (13:53 -0700)]
drm/i915: Use existing function instead of open-coding fence reg clear.
This is once less place to miss a new INTEL_INFO(dev)->gen update now.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 22:04:31 +0000 (15:04 -0700)]
drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 21:48:02 +0000 (14:48 -0700)]
drm/i915: set IBX pch type explicitly
This is a little less confusing than relying on the implicit zeroing of
the dev_priv.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 21:32:07 +0000 (14:32 -0700)]
drm/i915: add Ivy Bridge PCI IDs and driver feature structs
There are several variants, set feature bits appropriately for both
mobile and desktop parts.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 7 Apr 2011 19:33:56 +0000 (12:33 -0700)]
drm/i915: add PantherPoint PCH ID
We can treat PantherPoint as CougarPoint as far as display goes.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 17 Feb 2011 19:50:19 +0000 (11:50 -0800)]
agp/intel: add Ivy Bridge support
Just use the Sandy Bridge routines.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 6 Apr 2011 21:54:44 +0000 (14:54 -0700)]
drm/i915: ring support for Ivy Bridge
Use Sandy Bridge paths in a few places.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 6 Apr 2011 19:28:05 +0000 (12:28 -0700)]
drm/i915: page flip support for Ivy Bridge
Treat Ivy Bridge like previous chips as far as flip submission is
concerned.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 6 Apr 2011 19:13:38 +0000 (12:13 -0700)]
drm/i915: interrupt & vblank support for Ivy Bridge
Add new interrupt handling functions for Ivy Bridge.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 21:29:45 +0000 (14:29 -0700)]
drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
Not fully tested.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 22:09:55 +0000 (15:09 -0700)]
drm/i915: manual FDI training for Ivy Bridge
A0 stepping chips need to use manual training, but the bits have all
moved. So fix things up so we can at least train FDI for VGA links.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 6 Apr 2011 19:16:16 +0000 (12:16 -0700)]
drm/i915: add swizzle/tiling support for Ivy Bridge
Treat it like Ironlake and Sandy Bridge.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 6 Apr 2011 19:15:08 +0000 (12:15 -0700)]
drm/i915: Ivy Bridge has split display and pipe control
Ivy Bridge has a similar split display controller to Sandy Bridge, so
use HAS_PCH_SPLIT. And gen7 also has the pipe control instruction, so
use HAS_PIPE_CONTROL as well.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 21:33:09 +0000 (14:33 -0700)]
drm/i915: add IS_IVYBRIDGE macro for checks
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 6 Apr 2011 19:11:14 +0000 (12:11 -0700)]
drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
Note: IS_GEN* are for render related checks. Display and other checks
should use IS_MOBILE, IS_$CHIPSET or test for specific features.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 7 Apr 2011 20:58:17 +0000 (13:58 -0700)]
drm/i915: split enable/disable vblank code into chipset specific functions
This makes the Ironlake+ code trivial and generally simplifies things.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 7 Apr 2011 20:53:55 +0000 (13:53 -0700)]
drm/i915: split irq handling into per-chipset functions
Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Thu, 28 Apr 2011 21:27:04 +0000 (14:27 -0700)]
drm/i915: make FDI training a display function
Rather than branching in ironlake_pch_enable, add a new train_fdi
function to the display function pointer struct and use it instead.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Wed, 11 May 2011 22:10:58 +0000 (15:10 -0700)]
drm/i915: forcewake debugfs fix
Forcewake needs to register itself with drm to use the remove function.
The file also should be read only.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
Keith Packard [Wed, 11 May 2011 14:58:08 +0000 (07:58 -0700)]
MAINTAINERS: Switch maintainer for drm/i915 to Keith Packard
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Mon, 25 Apr 2011 18:25:56 +0000 (11:25 -0700)]
drm/i915: debugfs interface for forcewake reference count
forcewake is controlled by the open and close of the debugfs file. This
assures that buggy applications cannot cause the GT to stay on forever.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Mon, 25 Apr 2011 18:25:20 +0000 (11:25 -0700)]
drm/i915: move gen6 rps handling to workqueue
The render P-state handling code requires reading from a GT register.
This means that FORCEWAKE must be written to, a resource which is shared
and should be protected by struct_mutex. Hence we can not manipulate
that register from within the interrupt handling and so must delegate
the task to a workqueue.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Mon, 25 Apr 2011 19:11:50 +0000 (20:11 +0100)]
drm/i915: forcewake struct mutex locking fixes
Found by the new strict checking for the mutex being held whilst
manipulating the forcewake status.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Mon, 25 Apr 2011 18:23:07 +0000 (11:23 -0700)]
drm/i915: reference counted forcewake
Provide a reference count to track the forcewake state of the GPU and
give a safe mechanism for userspace to wake the GT. This also potentially
saves a UC read if the GT is known to be awake already.
The reference count is atomic, but the register access and hardware wake
sequence is protected by struct_mutex.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Ben Widawsky [Mon, 25 Apr 2011 18:22:22 +0000 (11:22 -0700)]
drm/i915: proper use of forcewake
Moved the macros around to properly do reads and writes for the given
GPU. This is to address special requirements for gen6 (SNB) reads and
writes.
Registers in the range 0-0x40000 on gen6 platforms require special
handling. Instead of relying on the callers to pick the registers
correctly, move the logic into the read and write functions.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Tue, 29 Mar 2011 09:40:27 +0000 (10:40 +0100)]
drm/i915: Disable all outputs early, before KMS takeover
If the outputs are active and continuing to access the GATT when we
teardown the PTEs, then there is a potential for us to hang the GPU.
The hang tends to be a PGTBL_ER with either an invalid host access or
an invalid display plane fetch.
v2: Reorder IRQ initialisation to defer until after GEM is setup.
Reported-by: Pekka Enberg <penberg@kernel.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> (855GM)
Tested-by: Pekka Enberg <penberg@kernel.org>
# note that this doesn't fix the underlying problem of the
PGTBL_ER and pipe underruns being reported immediately upon
init on his 965GM MacBook
Reported-and-tested-by: Rick Bramley <richard.bramley@hp.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35635
Reported-and-tested-by: Zdenek Kabelac <zdenek.kabelac@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36048
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Chris Wilson [Tue, 29 Mar 2011 23:59:52 +0000 (16:59 -0700)]
drm/i915: Do not clflush snooped objects
Rely on the GPU snooping into the CPU cache for appropriately bound
objects on MI_FLUSH. Or perhaps one day we will have a cache-coherent
CPU/GPU package...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
Chris Wilson [Tue, 29 Mar 2011 23:59:50 +0000 (16:59 -0700)]
drm/i915: Rename agp_type to cache_level
... to clarify just how we use it inside the driver and remove the
confusion of the poorly matching agp_type names. We still need to
translate through agp_type for interface into the fake AGP driver.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Sun, 20 Mar 2011 01:14:29 +0000 (18:14 -0700)]
drm/i915: debugfs for context information
Currently this is only useful for the rc6 stuff. But this would also be
useful when I finally get around to the logical context + ppgtt stuff.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
Jesse Barnes [Wed, 30 Mar 2011 21:08:56 +0000 (14:08 -0700)]
drm/i915: use i915_enable_rc6 on SNB too
For debug & testing.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Ben Widawsky [Sun, 20 Mar 2011 01:14:28 +0000 (18:14 -0700)]
drm/i915: fix rc6 initialization on Ironlake
There is a race condition between setting PWRCTXA and executing
MI_SET_CONTEXT. PWRCTXA must not be set until a valid context has been
written (or else the GPU could possible go into rc6, and return to an
invalid context).
Reported-and-Tested-by: Gu Rui <chaos.proton@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
Ben Widawsky [Sun, 20 Mar 2011 01:14:27 +0000 (18:14 -0700)]
drm/1915: ringbuffer wait for idle function
Added a new function which waits for the ringbuffer space to be equal to
(total - 8). This is the empty condition of the ringbuffer, and
equivalent to head==tail.
Also modified two users of this functionality elsewhere in the code.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Ben Widawsky [Sun, 20 Mar 2011 01:14:26 +0000 (18:14 -0700)]
drm/i915: fix ilk rc6 teardown locking
In the failure cases during rc6 initialization, both the power context
and render context may get !refcount without holding struct_mutex.
However, on rc6 disabling, the lock is held by the caller.
Rearranged the locking so that it's safe in both cases.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Eric Anholt [Wed, 30 Mar 2011 20:01:10 +0000 (13:01 -0700)]
drm/i915: Fold the DPLL limit defines into the structs that use them.
They're used in one place, and not providing any descriptive value,
with their names just being approximately the conjunction of the
struct name and the struct field.
This diff was produced with gcc -E, copying the new struct definitions
out, moving a couple of the old comments into place in the new
structs, and reindenting.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Eric Anholt [Wed, 30 Mar 2011 20:01:09 +0000 (13:01 -0700)]
drm/i915: Clean up leftover DPLL and LVDS register choice from pch split.
We used to have these from the product of (pch, non-pch) * (pipe a,
pipe b). Now we can just use the nice per-pipe reg macros in the
split out crtc_mode_sets.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Eric Anholt [Wed, 30 Mar 2011 20:01:08 +0000 (13:01 -0700)]
drm/i915: Drop remaining pre-Ironlake code from ironlake_crtc_mode_set().
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Eric Anholt [Wed, 30 Mar 2011 20:01:07 +0000 (13:01 -0700)]
drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set().
Ironlake is where the PCH split started.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Eric Anholt [Wed, 30 Mar 2011 20:01:06 +0000 (13:01 -0700)]
drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set().
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Eric Anholt [Wed, 30 Mar 2011 20:01:05 +0000 (13:01 -0700)]
drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set.
While g4x had DP, eDP came with Ironlake, so we don't need that code here.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / log