Bjorn Helgaas [Fri, 28 Apr 2017 15:38:13 +0000 (10:38 -0500)]
Merge branch 'pci/remove' into next
* pci/remove:
PCI: Don't allow unbinding host controllers that aren't prepared
Brian Norris [Thu, 20 Apr 2017 20:36:25 +0000 (15:36 -0500)]
PCI: Don't allow unbinding host controllers that aren't prepared
Many PCI host controller drivers aren't prepared to have their devices
unbound from them forcefully (e.g., through /sys/.../<driver>/unbind), as
they don't provide any driver .remove callback, where they'd detach the
root bus, release resources, etc. Keeping the driver built in (i.e., not a
loadable module) is not enough; and providing no .remove callback just
means we don't do any teardown.
To rule out the possibility of unbinding a device via sysfs, we need to set
the ".suppress_bind_attrs" field.
I found the suspect drivers via the following search:
git grep -l platform_driver $(git grep -L -e '\.remove' -e suppress_bind_attrs drivers/pci/)
Then I inspected them to ensure that
(a) they set up a PCI bus in their probe() and
(b) they don't have a remove() callback for undoing the setup
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Fri, 28 Apr 2017 15:36:12 +0000 (10:36 -0500)]
Merge branch 'pci/virtualization' into next
* pci/virtualization:
ixgbe: Use pcie_flr() instead of duplicating it
IB/hfi1: Use pcie_flr() instead of duplicating it
PCI: Call pcie_flr() from reset_chelsio_generic_dev()
PCI: Call pcie_flr() from reset_intel_82599_sfp_virtfn()
PCI: Export pcie_flr()
PCI: Add sysfs sriov_drivers_autoprobe to control VF driver binding
PCI: Avoid FLR for Intel 82579 NICs
Conflicts:
include/linux/pci.h
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:34 +0000 (10:34 -0500)]
Merge branch 'pci/resource-mmap' into next
* pci/resource-mmap:
ia64: Use generic pci_mmap_resource_range()
ia64: Remove redundant checks for WC in pci_mmap_page_range()
ia64: Remove redundant valid_mmap_phys_addr_range() from pci_mmap_page_range()
PCI: Add I/O BAR support to generic pci_mmap_resource_range()
x86/PCI: Use generic pci_mmap_resource_range()
unicore32/PCI: Use generic pci_mmap_resource_range()
sh/PCI: Use generic pci_mmap_resource_range()
parisc: Use generic pci_mmap_resource_range()
mn10300/PCI: Use generic pci_mmap_resource_range()
MIPS: PCI: Use generic pci_mmap_resource_range()
cris/PCI: Use generic pci_mmap_resource_range()
ARM/PCI: Use generic pci_mmap_resource_range()
PCI: Add pci_mmap_resource_range() and use it for ARM64
PCI: Add BAR index argument to pci_mmap_page_range()
PCI: Use BAR index in sysfs attr->private instead of resource pointer
PCI: Add arch_can_pci_mmap_io() on architectures which can mmap() I/O space
PCI: Move multiple declarations of pci_mmap_page_range() to <linux/pci.h>
PCI: Add arch_can_pci_mmap_wc() macro
xtensa/PCI: Do not mmap PCI BARs to userspace as write-through
PCI: Only allow WC mmap on prefetchable resources
PCI: Fix another sanity check bug in /proc/pci mmap
PCI: Fix pci_mmap_fits() for HAVE_PCI_RESOURCE_TO_USER platforms
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:29 +0000 (10:34 -0500)]
Merge branch 'pci/resource' into next
* pci/resource:
PCI: Don't resize resources when realigning all devices in system
PCI: Don't reassign resources that are already aligned
PCI: Factor pci_reassigndev_resource_alignment()
powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned
PCI: Add pcibios_default_alignment() for arch-specific alignment control
PCI: Fix calculation of bridge window's size and alignment
PCI: Ignore requested alignment for IOV BARs
PCI: Make PCI_ROM_ADDRESS_MASK a 32-bit constant
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:24 +0000 (10:34 -0500)]
Merge branch 'pci/pm' into next
* pci/pm:
PCI: Freeze PME scan before suspending devices
PCI/PM: Don't sleep at all when d3_delay or d3cold_delay is zero
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:19 +0000 (10:34 -0500)]
Merge branch 'pci/msi' into next
* pci/msi:
PCI/MSI: Use dev_printk() when possible
of/pci: Remove unused MSI controller helpers
PCI: mvebu: Remove useless MSI enabling code
PCI: aardvark: Move to MSI handling using generic MSI support
PCI/MSI: Make pci_msi_shutdown() and pci_msix_shutdown() static
PCI/MSI: Stop disabling MSI/MSI-X in pci_device_shutdown()
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:14 +0000 (10:34 -0500)]
Merge branch 'pci/misc' into next
* pci/misc:
PCI: Change pci_host_common_probe() visibility
PCI: Fix typo pci_cfg_access_lock() comment
PCI: Include pci.h for struct pci_ops definition
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:10 +0000 (10:34 -0500)]
Merge branch 'pci/irq' into next
* pci/irq:
PCI: Disable boot interrupt quirk for ASUS M2N-LR
nvme/pci: Switch to pci_request_irq()
PCI/irq: Add pci_request_irq() and pci_free_irq() helpers
genirq: Return the IRQ name from free_irq()
genirq: Fix indentation in remove_irq()
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:05 +0000 (10:34 -0500)]
Merge branch 'pci/ioremap' into next
* pci/ioremap:
PCI: versatile: Update PCI config space remap function
PCI: keystone-dw: Update PCI config space remap function
PCI: layerscape: Update PCI config space remap function
PCI: hisi: Update PCI config space remap function
PCI: tegra: Update PCI config space remap function
PCI: xgene: Update PCI config space remap function
PCI: armada8k: Update PCI config space remap function
PCI: designware: Update PCI config space remap function
PCI: iproc-platform: Update PCI config space remap function
PCI: qcom: Update PCI config space remap function
PCI: rockchip: Update PCI config space remap function
PCI: spear13xx: Update PCI config space remap function
PCI: xilinx-nwl: Update PCI config space remap function
PCI: xilinx: Update PCI config space remap function
PCI: ECAM: Map config region with pci_remap_cfgspace()
PCI: Implement devm_pci_remap_cfgspace()
devres: fix devm_ioremap_*() offset parameter kerneldoc description
ARM: Implement pci_remap_cfgspace() interface
ARM64: Implement pci_remap_cfgspace() interface
linux/io.h: Add pci_remap_cfgspace() interface
PCI: Remove __weak tag from pci_remap_iospace()
Bjorn Helgaas [Fri, 28 Apr 2017 15:34:00 +0000 (10:34 -0500)]
Merge branch 'pci/iommu' into next
* pci/iommu:
PCI: Add bridge DMA alias quirk for ITE 8893 bridge
Bjorn Helgaas [Fri, 28 Apr 2017 15:33:55 +0000 (10:33 -0500)]
Merge branch 'pci/enumeration' into next
* pci/enumeration:
PCI: Include PCI-to-PCIe bridges as "Downstream Ports"
PCI: Improve __pci_read_base() robustness
PCI: Short-circuit pci_device_is_present() for disconnected devices
PCI/MSI: Skip disabling disconnected devices
PCI: Don't attempt config access to disconnected devices
PCI: Add device disconnected state
PCI: Export PCI device config accessors
Bjorn Helgaas [Fri, 28 Apr 2017 15:33:41 +0000 (10:33 -0500)]
Merge branch 'pci/switchtec' into next
* pci/switchtec:
switchtec: Add IOCTLs to the Switchtec driver
switchtec: Add sysfs attributes to the Switchtec driver
switchtec: Add user interface documentation
MicroSemi Switchtec management interface driver
Conflicts:
drivers/pci/Kconfig
Bjorn Helgaas [Fri, 28 Apr 2017 15:33:15 +0000 (10:33 -0500)]
Merge branch 'pci/host-thunder' into next
* pci/host-thunder:
PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirk
PCI/ACPI: Tidy up MCFG quirk whitespace
PCI: Avoid generating invalid ThunderX2 DMA aliases
PCI: Add device flag PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
PCI: Apply Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices
Bjorn Helgaas [Fri, 28 Apr 2017 15:33:10 +0000 (10:33 -0500)]
Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip:
PCI: rockchip: Modularize
PCI: Export pci_remap_iospace() and pci_unmap_iospace()
PCI: rockchip: Add remove() support
PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port
PCI: rockchip: Advertise 128-byte Read Completion Boundary support
PCI: rockchip: Make 'return 0' more obvious in probe()
PCI: rockchip: Unindent rockchip_pcie_set_power_limit()
PCI: rockchip: Handle regulator_get_current_limit() failure correctly
Bjorn Helgaas [Fri, 28 Apr 2017 15:33:05 +0000 (10:33 -0500)]
Merge branch 'pci/host-mvebu' into next
* pci/host-mvebu:
PCI: mvebu: Avoid changing the SCC bit in the Link Status register
Bjorn Helgaas [Fri, 28 Apr 2017 15:33:00 +0000 (10:33 -0500)]
Merge branch 'pci/host-iproc' into next
* pci/host-iproc:
PCI: iproc: Add PCI_DOMAIN dependency to PCI Kconfig
Bjorn Helgaas [Fri, 28 Apr 2017 15:32:54 +0000 (10:32 -0500)]
Merge branch 'pci/host-imx6' into next
* pci/host-imx6:
PCI: imx6: Fix spelling mistake: "contol" -> "control"
PCI: imx6: Do not switch speed if Gen2 is disabled
PCI: imx6: Do not wait for speed change on i.MX7
PCI: imx6: Allow probe deferral by reset GPIO
PCI: imx6: Add code to support i.MX7D
Bjorn Helgaas [Fri, 28 Apr 2017 15:32:50 +0000 (10:32 -0500)]
Merge branch 'pci/host-hv' into next
* pci/host-hv:
PCI: hv: Convert hv_pci_dev.refs from atomic_t to refcount_t
PCI: hv: Allocate interrupt descriptors with GFP_ATOMIC
PCI: hv: Specify CPU_AFFINITY_ALL for MSI affinity when >= 32 CPUs
PCI: hv: Lock PCI bus on device eject
PCI: hv: Properly handle PCI bus remove
Bjorn Helgaas [Fri, 28 Apr 2017 15:32:44 +0000 (10:32 -0500)]
Merge branch 'pci/host-faraday' into next
* pci/host-faraday:
PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver
PCI: Add DT bindings for Faraday Technology PCI Host Bridge
Bjorn Helgaas [Fri, 28 Apr 2017 15:32:33 +0000 (10:32 -0500)]
Merge branch 'pci/host-designware' into next
* pci/host-designware:
ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP
MAINTAINERS: Add PCI Endpoint maintainer
Documentation: PCI: Add userguide for PCI endpoint test function
tools: PCI: Add sample test script to invoke pcitest
tools: PCI: Add a userspace tool to test PCI endpoint
Documentation: misc-devices: Add Documentation for pci-endpoint-test driver
misc: Add host side PCI driver for PCI test function device
PCI: Add device IDs for DRA74x and DRA72x
dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access
PCI: dwc: dra7xx: Workaround for errata id i870
dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode
PCI: dwc: dra7xx: Add EP mode support
PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently
dt-bindings: PCI: Add DT bindings for PCI designware EP mode
PCI: dwc: designware: Add EP mode support
Documentation: PCI: Add binding documentation for pci-test endpoint function
PCI: endpoint: functions: Add an EP function to test PCI
Documentation: PCI: Add specification for the *PCI test* function device
PCI: endpoint: Create configfs entry for EPC device and EPF driver
Documentation: PCI: Guide to use PCI endpoint configfs
PCI: endpoint: Introduce configfs entry for configuring EP functions
Documentation: PCI: Guide to use PCI Endpoint Core Layer
PCI: endpoint: Add EP core layer to enable EP controller and EP functions
PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe
PCI: dwc: designware: Move _unroll configurations to a separate function
PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
PCI: dwc: all: Modify dbi accessors to take dbi_base as argument
PCI: dwc: artpec6: Populate cpu_addr_fixup ops
PCI: dwc: dra7xx: Populate cpu_addr_fixup ops
PCI: dwc: designware: Add new *ops* for CPU addr fixup
PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()
PCI: dwc: Unindent dw_handle_msi_irq() loop
PCI: dwc: Fix dw_pcie_ops NULL pointer dereference
PCI: dwc: Select PCI_HOST_COMMON for hisi
PCI: thunder-pem: Fix legacy firmware PEM-specific resources
PCI: thunder-pem: Add legacy firmware support for Cavium ThunderX host controller
PCI: thunder-pem: Use Cavium assigned hardware ID for ThunderX host controller
PCI: iproc: Save host bridge window resource in struct iproc_pcie
PCI/ASPM: Always set link->downstream to avoid NULL dereference on remove
PCI: Prevent VPD access for QLogic ISP2722
PCI: exynos: Initialize elbi_base even when using PHY framework
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:20 +0000 (15:15 +0530)]
ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP
The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should be
set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO in RC
mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:19 +0000 (15:15 +0530)]
MAINTAINERS: Add PCI Endpoint maintainer
Add maintainer for the newly introduced PCI Endpoint framework.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:18 +0000 (15:15 +0530)]
Documentation: PCI: Add userguide for PCI endpoint test function
Add documentation to help users use pci-epf-test function driver and
pci_endpoint_test host driver for testing PCI.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:17 +0000 (15:15 +0530)]
tools: PCI: Add sample test script to invoke pcitest
Add a simple test script that invokes the pcitest userspace tool to perform
all the PCI endpoint tests (BAR tests, interrupt tests, read tests, write
tests and copy tests).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:16 +0000 (15:15 +0530)]
tools: PCI: Add a userspace tool to test PCI endpoint
Add a userspace tool to invoke the ioctls exposed by the PCI endpoint test
driver to perform various PCI tests.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:15 +0000 (15:15 +0530)]
Documentation: misc-devices: Add Documentation for pci-endpoint-test driver
Add Documentation for pci-endpoint-test driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:14 +0000 (15:15 +0530)]
misc: Add host side PCI driver for PCI test function device
Add PCI endpoint test driver that can verify base address register, legacy
interrupt/MSI interrupt and read/write/copy buffers between host and
device. The corresponding pci-epf-test function driver should be used on
the EP side.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:13 +0000 (15:15 +0530)]
PCI: Add device IDs for DRA74x and DRA72x
Add device IDs for DRA74x and DRA72x devices. These devices have
configurable PCI endpoint.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:12 +0000 (15:15 +0530)]
dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access
Update device tree binding documentation of TI's dra7xx PCI controller to
include property for enabling unaligned mem access.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:11 +0000 (15:15 +0530)]
PCI: dwc: dra7xx: Workaround for errata id i870
According to errata i870, access to the PCIe slave port that are not 32-bit
aligned will result in incorrect mapping to TLP Address and Byte enable
fields.
Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this errata here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:09 +0000 (15:15 +0530)]
dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode
Add device tree binding documentation for PCI dra7xx EP mode.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:08 +0000 (15:15 +0530)]
PCI: dwc: dra7xx: Add EP mode support
The PCIe controller integrated in dra7xx SoCs is capable of operating in
endpoint mode. Add endpoint mode support to dra7xx driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:07 +0000 (15:15 +0530)]
PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently
No functional change. Split dra7xx_pcie_enable_interrupts() into
dra7xx_pcie_enable_wrapper_interrupts() and
dra7xx_pcie_enable_msi_interrupts() so that wrapper interrupts and MSI
interrupts can be enabled independently. This is in preparation for adding
EP mode support to dra7xx driver since EP mode doesn't have to enable
msi_interrupts.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:06 +0000 (15:15 +0530)]
dt-bindings: PCI: Add DT bindings for PCI designware EP mode
Add device tree binding documentation for PCI designware EP mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:05 +0000 (15:15 +0530)]
PCI: dwc: designware: Add EP mode support
Add endpoint mode support to designware driver. This uses the EP Core layer
introduced recently to add endpoint mode support. *Any* function driver
can now use this designware device in order to achieve the EP
functionality.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Mon, 27 Mar 2017 09:45:04 +0000 (15:15 +0530)]
Documentation: PCI: Add binding documentation for pci-test endpoint function
Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Christoph Hellwig [Fri, 14 Apr 2017 19:11:28 +0000 (21:11 +0200)]
ixgbe: Use pcie_flr() instead of duplicating it
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Christoph Hellwig [Tue, 25 Apr 2017 19:36:19 +0000 (14:36 -0500)]
IB/hfi1: Use pcie_flr() instead of duplicating it
Tested-by: Jakub Byczkowski <jakub.byczkowski@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Doug Ledford <dledford@redhat.com>
Colin Ian King [Fri, 21 Apr 2017 07:02:30 +0000 (08:02 +0100)]
PCI: imx6: Fix spelling mistake: "contol" -> "control"
Trivial fix to spelling mistake in dev_err message
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <hongxing.Zhu@nxp.com>
Stefan Assmann [Wed, 19 Apr 2017 07:22:45 +0000 (09:22 +0200)]
PCI: Disable boot interrupt quirk for ASUS M2N-LR
The ASUS M2N-LR should not trigger boot interrupt quirks although it
carries an Intel 6702PXH. On this board the boot interrupt quirks cause
incorrect IRQ assignments and should be disabled.
Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=43074
Tested-by: Solomon Peachy <pizza@shaftnet.org>
Signed-off-by: Stefan Assmann <sassmann@kpanic.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:10 +0000 (17:49 +0100)]
PCI: versatile: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Rob Herring <robh@kernel.org>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:09 +0000 (17:49 +0100)]
PCI: keystone-dw: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:08 +0000 (17:49 +0100)]
PCI: layerscape: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Mingkai Hu <mingkai.hu@freescale.com>
Cc: Minghuan Lian <minghuan.Lian@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:07 +0000 (17:49 +0100)]
PCI: hisi: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:06 +0000 (17:49 +0100)]
PCI: tegra: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use correct memory mapping attributes to map config space
regions to enforce configuration space non-posted writes behaviour.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:05 +0000 (17:49 +0100)]
PCI: xgene: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tanmay Inamdar <tinamdar@apm.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:04 +0000 (17:49 +0100)]
PCI: armada8k: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:03 +0000 (17:49 +0100)]
PCI: designware: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:02 +0000 (17:49 +0100)]
PCI: iproc-platform: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:01 +0000 (17:49 +0100)]
PCI: qcom: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:49:00 +0000 (17:49 +0100)]
PCI: rockchip: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wenrui Li <wenrui.li@rock-chips.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:59 +0000 (17:48 +0100)]
PCI: spear13xx: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generate on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:58 +0000 (17:48 +0100)]
PCI: xilinx-nwl: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:57 +0000 (17:48 +0100)]
PCI: xilinx: Update PCI config space remap function
PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_pci_remap_cfg* interface to make sure the correct
memory mappings for PCI configuration space are used.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:56 +0000 (17:48 +0100)]
PCI: ECAM: Map config region with pci_remap_cfgspace()
The current ECAM kernel implementation uses ioremap() to map the ECAM
configuration space memory region; this is not safe in that on some
architectures the ioremap interface provides mappings that allow posted
write transactions. This, as highlighted in the PCIe specifications (4.0 -
Rev0.3, "Ordering Considerations for the Enhanced Configuration Address
Mechanism"), can create ordering issues for software because posted writes
transactions on the CPU host bus are non posted in the PCI express fabric.
Update the ioremap() interface to use pci_remap_cfgspace() whose mapping
attributes guarantee that non-posted writes transactions are issued for
memory writes within the ECAM memory mapped address region.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jayachandran C <jnair@caviumnetworks.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:55 +0000 (17:48 +0100)]
PCI: Implement devm_pci_remap_cfgspace()
The introduction of the pci_remap_cfgspace() interface allows PCI host
controller drivers to map PCI config space through a dedicated kernel
interface. Current PCI host controller drivers use the devm_ioremap_*()
devres interfaces to map PCI configuration space regions so in order to
update them to the new pci_remap_cfgspace() mapping interface a new set of
devres interfaces should be implemented so that PCI host controller drivers
can make use of them.
Introduce two new functions in the PCI kernel layer and Devres
documentation:
- devm_pci_remap_cfgspace()
- devm_pci_remap_cfg_resource()
so that PCI host controller drivers can make use of them to map PCI
configuration space regions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:54 +0000 (17:48 +0100)]
devres: fix devm_ioremap_*() offset parameter kerneldoc description
The offset parameter in the devres devm_ioremap_*() functions kerneldoc
entries is erroneously defined as BUS offset whereas it is actually a
resource address.
Since it is actually misleading, fix the devres devm_ioremap_* offset
parameter kerneldoc entry by replacing BUS offset with a more suitable
description (ie Resource address).
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tejun Heo <tj@kernel.org>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:53 +0000 (17:48 +0100)]
ARM: Implement pci_remap_cfgspace() interface
The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes have to be non-posted
transactions.
Current ioremap interface on ARM provides mapping functions that provide
"bufferable" writes transactions (ie ioremap uses MT_DEVICE memory type)
aka posted writes, so PCI host controller drivers have no arch interface to
remap PCI configuration space with memory attributes that comply with the
PCI specifications for configuration space.
Implement an ARM specific pci_remap_cfgspace() interface that allows to map
PCI config memory regions with MT_UNCACHED memory type (ie strongly ordered
- non-posted writes), providing a remap function that complies with PCI
specifications for config space transactions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:52 +0000 (17:48 +0100)]
ARM64: Implement pci_remap_cfgspace() interface
The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes are non-posted
transactions.
This rule is reinforced by the ARM v8 architecture reference manual (issue
A.k, Early Write Acknowledgment) that explicitly recommends that No Early
Write Acknowledgment attribute should be used to map PCI configuration
(write) transactions.
Current ioremap interface on ARM64 implements mapping functions where the
Early Write Acknowledgment hint is enabled, so they cannot be used to map
PCI configuration space in a PCI specs compliant way.
Implement an ARM64 specific pci_remap_cfgspace() interface that allows to
map PCI config region with nGnRnE attributes, providing a remap function
that complies with PCI specifications and the ARMv8 architecture reference
manual recommendations.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Tomasz Nowicki [Wed, 29 Mar 2017 12:16:13 +0000 (14:16 +0200)]
PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirk
Currently SoCs pass2.x do not emulate EA headers for ACPI boot method at
all. However, for pass2.x some devices (like EDAC) advertise incorrect
base addresses in their BARs which results in driver probe failure during
resource request. Since all problematic blocks are on 2nd NUMA node under
domain 10 add necessary quirk entry to obtain BAR addresses correction
using EA header emulation.
Fixes:
44f22bd91e88 ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller")
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Robert Richter <rrichter@cavium.com>
CC: stable@vger.kernel.org # v4.10+
Bjorn Helgaas [Fri, 21 Apr 2017 16:42:54 +0000 (11:42 -0500)]
PCI/ACPI: Tidy up MCFG quirk whitespace
With no blank lines, it's not obvious where the macro definitions end and
the uses begin. Add some blank lines and reorder the ThunderX definitions.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v4.10+
Brian Norris [Fri, 10 Mar 2017 02:46:17 +0000 (18:46 -0800)]
PCI: rockchip: Modularize
Now that we've exported pci_remap_iospace() and added proper remove()
support, there's no reason this can't be a loadable module.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Brian Norris [Fri, 10 Mar 2017 02:46:16 +0000 (18:46 -0800)]
PCI: Export pci_remap_iospace() and pci_unmap_iospace()
These are useful for PCIe host drivers, and those drivers can be modules.
[bhelgaas: don't remove __weak; it's removed elsewhere]
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Brian Norris [Fri, 10 Mar 2017 02:46:15 +0000 (18:46 -0800)]
PCI: rockchip: Add remove() support
Currently, if we try to unbind the platform device, the remove will
succeed, but the removal won't undo most of the registration, leaving
partially-configured PCI devices in the system.
This allows, for example, a simple 'lspci' to crash the system, as it will
try to touch the freed (via devm_*) driver structures, e.g., on RK3399:
# echo
f8000000.pcie > /sys/bus/platform/drivers/rockchip-pcie/unbind
# lspci
So let's implement device remove().
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Christoph Hellwig [Fri, 14 Apr 2017 19:11:27 +0000 (21:11 +0200)]
PCI: Call pcie_flr() from reset_chelsio_generic_dev()
Instead of copy & pasting and old version of the code.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Christoph Hellwig [Fri, 14 Apr 2017 19:11:26 +0000 (21:11 +0200)]
PCI: Call pcie_flr() from reset_intel_82599_sfp_virtfn()
The 82599 quirk contained an outdated copy of the FLR code.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Christoph Hellwig [Fri, 14 Apr 2017 19:11:25 +0000 (21:11 +0200)]
PCI: Export pcie_flr()
Currently we opencode the FLR sequence in lots of place; export a core
helper instead. We split out the probing for FLR support as all the
non-core callers already know their hardware.
Note that in the new pci_has_flr() function the quirk check has been moved
before the capability check as there is no point in reading the capability
in this case.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bodong Wang [Wed, 12 Apr 2017 22:51:40 +0000 (01:51 +0300)]
PCI: Add sysfs sriov_drivers_autoprobe to control VF driver binding
Sometimes it is not desirable to bind SR-IOV VFs to drivers. This can save
host side resource usage by VF instances that will be assigned to VMs.
Add a new PCI sysfs interface "sriov_drivers_autoprobe" to control that
from the PF. To modify it, echo 0/n/N (disable probe) or 1/y/Y (enable
probe) to:
/sys/bus/pci/devices/<DOMAIN:BUS:DEVICE.FUNCTION>/sriov_drivers_autoprobe
Note that this must be done before enabling VFs. The change will not take
effect if VFs are already enabled. Simply, one can disable VFs by setting
sriov_numvfs to 0, choose whether to probe or not, and then re-enable the
VFs by restoring sriov_numvfs.
[bhelgaas: changelog, ABI doc]
Signed-off-by: Bodong Wang <bodong@mellanox.com>
Signed-off-by: Eli Cohen <eli@mellanox.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
David Woodhouse [Fri, 7 Apr 2017 10:10:53 +0000 (12:10 +0200)]
ia64: Use generic pci_mmap_resource_range()
Now that we eliminated the different behaviour in separately-reviewable
commits, we can switch IA64 to the generic implementation.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Tested-by: Tony Luck <tony.luck@intel.com>
David Woodhouse [Fri, 7 Apr 2017 10:01:00 +0000 (12:01 +0200)]
ia64: Remove redundant checks for WC in pci_mmap_page_range()
For a PCI MMIO BAR, phys_mem_access_prot() should always return UC or WC.
And while a mixture of cached and uncached mappings is forbidden, we were
already mixing WC and UC, which is OK. Just do as we're asked.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Tested-by: Tony Luck <tony.luck@intel.com>
David Woodhouse [Fri, 7 Apr 2017 09:22:42 +0000 (11:22 +0200)]
ia64: Remove redundant valid_mmap_phys_addr_range() from pci_mmap_page_range()
We know we are within a valid MMIO BAR by the time this function gets
called; there's no need to check.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Tested-by: Tony Luck <tony.luck@intel.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:08 +0000 (13:26 +0100)]
PCI: Add I/O BAR support to generic pci_mmap_resource_range()
This will need to call into an arch-provided pci_iobar_pfn() function.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:07 +0000 (13:26 +0100)]
x86/PCI: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:06 +0000 (13:26 +0100)]
unicore32/PCI: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:05 +0000 (13:26 +0100)]
sh/PCI: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:04 +0000 (13:26 +0100)]
parisc: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:03 +0000 (13:26 +0100)]
mn10300/PCI: Use generic pci_mmap_resource_range()
This was setting vma->vm_flags |= VM_LOCKED. Not sure why...
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: David Howells <dhowells@redhat.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:02 +0000 (13:26 +0100)]
MIPS: PCI: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:01 +0000 (13:26 +0100)]
cris/PCI: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
David Woodhouse [Wed, 12 Apr 2017 12:26:00 +0000 (13:26 +0100)]
ARM/PCI: Use generic pci_mmap_resource_range()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:25:59 +0000 (13:25 +0100)]
PCI: Add pci_mmap_resource_range() and use it for ARM64
Starting to leave behind the legacy of the pci_mmap_page_range() interface
which takes "user-visible" BAR addresses. This takes just the resource and
offset.
For now, both APIs coexist and depending on the platform, one is
implemented as a wrapper around the other.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:25:58 +0000 (13:25 +0100)]
PCI: Add BAR index argument to pci_mmap_page_range()
In all cases we know which BAR it is. Passing it in means that arch code
(or generic code; watch this space) won't have to go looking for it again.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
David Woodhouse [Wed, 12 Apr 2017 12:25:57 +0000 (13:25 +0100)]
PCI: Use BAR index in sysfs attr->private instead of resource pointer
We store the pointer, and then on *every* use of it we loop over the
device's resources to find out the index. That's kind of silly.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:51 +0000 (17:48 +0100)]
linux/io.h: Add pci_remap_cfgspace() interface
The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting")
mandate non-posted configuration transactions. As further highlighted in
the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the
Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative
configuration mechanism, the memory mapped transactions from the host CPU
into Configuration Requests on the PCI express fabric may create ordering
problems for software because writes to memory address are typically posted
transactions (unless the architecture can enforce through virtual address
mapping non-posted write transactions behaviour) but writes to
Configuration Space are not posted on the PCI express fabric.
Current DT and ACPI host bridge controllers map PCI configuration space
(ECAM and ECAM-derivative) into the virtual address space through ioremap()
calls, that are non-cacheable device accesses on most architectures, but
may provide "bufferable" or "posted" write semantics in architecture like
eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus
connecting the host CPU to the PCI fabric; this behaviour, as underlined in
the PCIe specifications, may trigger transactions ordering rules and must
be prevented.
Introduce a new generic and explicit API to create a memory mapping for
ECAM and ECAM-derivative config space area that defaults to
ioremap_nocache() (which should provide a sane default behaviour) but still
allowing architectures on which ioremap_nocache() results in posted write
transactions to override the function call with an arch specific
implementation that complies with the PCI specifications for configuration
transactions.
[bhelgaas: fold in #ifdef CONFIG_PCI wrapper]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Lorenzo Pieralisi [Wed, 19 Apr 2017 16:48:50 +0000 (17:48 +0100)]
PCI: Remove __weak tag from pci_remap_iospace()
pci_remap_iospace() is marked as a weak symbol even though no architecture
is currently overriding it; given that its implementation internals have
already code paths that are arch specific (ie PCI_IOBASE and
ioremap_page_range() attributes) there is no need to leave the weak symbol
in the kernel since the same functionality can be achieved by customizing
per-arch the corresponding functionality.
Remove the __weak symbol from pci_remap_iospace().
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Yongji Xie [Mon, 10 Apr 2017 11:58:14 +0000 (19:58 +0800)]
PCI: Don't resize resources when realigning all devices in system
The "pci=resource_alignment" argument aligns BARs of designated devices by
artificially increasing their size. Increasing the size increases the
alignment and prevents other resources from being assigned in the same
alignment region, e.g., in the same page, but it can break drivers that use
the BAR size to locate things, e.g., ilo_map_device() does this:
off = pci_resource_len(pdev, bar) - 0x2000;
The new pcibios_default_alignment() interface allows an arch to request
that *all* BARs in the system be aligned to a larger size. In this case,
we don't need to artificially increase the resource size because we know
every BAR of every device will be realigned, so nothing will share the same
alignment region.
Use IORESOURCE_STARTALIGN to request realignment of PCI BARs when we know
we're realigning all BARs in the system.
[bhelgaas: comment, changelog]
Signed-off-by: Yongji Xie <elohimes@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Mon, 17 Apr 2017 20:20:58 +0000 (15:20 -0500)]
PCI: Don't reassign resources that are already aligned
The "pci=resource_alignment=" kernel argument designates devices for which
we want alignment greater than is required by the PCI specs. Previously we
set IORESOURCE_UNSET for every MEM resource of those devices, even if the
resource was *already* sufficiently aligned.
If a resource is already sufficiently aligned, leave it alone and don't try
to reassign it.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Fri, 14 Apr 2017 19:12:06 +0000 (14:12 -0500)]
PCI: Factor pci_reassigndev_resource_alignment()
Pull the BAR size adjustment out into a new function,
pci_request_resource_alignment(), and add a comment about how and why we
increase the resource size and alignment.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Yongji Xie [Mon, 10 Apr 2017 11:58:13 +0000 (19:58 +0800)]
powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned
Override pcibios_default_alignment() to set default alignment to PAGE_SIZE
for all PCI devices on PowerNV platform. Thus sub-page BARs would not
share a page and could be mapped into guest when VFIO passthrough them.
Signed-off-by: Yongji Xie <elohimes@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Yongji Xie [Mon, 10 Apr 2017 11:58:12 +0000 (19:58 +0800)]
PCI: Add pcibios_default_alignment() for arch-specific alignment control
When VFIO passes through a PCI device to a guest, it does not allow the
guest to mmap BARs that are smaller than PAGE_SIZE unless it can reserve
the rest of the page (see vfio_pci_probe_mmaps()). This is because a page
might contain several small BARs for unrelated devices and a guest should
not be able to access all of them.
VFIO emulates guest accesses to non-mappable BARs, which is functional but
slow. On systems with large page sizes, e.g., PowerNV with 64K pages, BARs
are more likely to share a page and performance is more likely to be a
problem.
Add a weak function to set default alignment for all PCI devices. An arch
can override it to force the PCI core to place memory BARs on their own
pages.
Signed-off-by: Yongji Xie <elohimes@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Wed, 19 Apr 2017 12:44:51 +0000 (07:44 -0500)]
PCI: Include PCI-to-PCIe bridges as "Downstream Ports"
A PCI/PCI-X to PCI Express bridge, sometimes referred to as a "reverse
bridge", is a bridge with conventional PCI or PCI-X on its primary side and
a PCI Express Port on its secondary (downstream) side.
That PCIe Port is a Downstream Port and could be connected to a slot, just
like a Root Port or a Switch Downstream Port. Make pcie_downstream_port()
return true for them, so we can access the Slot registers in the PCIe
capability.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lukas Wunner [Tue, 18 Apr 2017 18:44:30 +0000 (20:44 +0200)]
PCI: Freeze PME scan before suspending devices
Laurent Pinchart reported that the Renesas R-Car H2 Lager board (r8a7790)
crashes during suspend tests. Geert Uytterhoeven managed to reproduce the
issue on an M2-W Koelsch board (r8a7791):
It occurs when the PME scan runs, once per second. During PME scan, the
PCI host bridge (rcar-pci) registers are accessed while its module clock
has already been disabled, leading to the crash.
One reproducer is to configure s2ram to use "s2idle" instead of "deep"
suspend:
# echo 0 > /sys/module/printk/parameters/console_suspend
# echo s2idle > /sys/power/mem_sleep
# echo mem > /sys/power/state
Another reproducer is to write either "platform" or "processors" to
/sys/power/pm_test. It does not (or is less likely) to happen during full
system suspend ("core" or "none") because system suspend also disables
timers, and thus the workqueue handling PME scans no longer runs. Geert
believes the issue may still happen in the small window between disabling
module clocks and disabling timers:
# echo 0 > /sys/module/printk/parameters/console_suspend
# echo platform > /sys/power/pm_test # Or "processors"
# echo mem > /sys/power/state
(Make sure CONFIG_PCI_RCAR_GEN2 and CONFIG_USB_OHCI_HCD_PCI are enabled.)
Rafael Wysocki agrees that PME scans should be suspended before the host
bridge registers become inaccessible. To that end, queue the task on a
workqueue that gets frozen before devices suspend.
Rafael notes however that as a result, some wakeup events may be missed if
they are delivered via PME from a device without working IRQ (which hence
must be polled) and occur after the workqueue has been frozen. If that
turns out to be an issue in practice, it may be possible to solve it by
calling pci_pme_list_scan() once directly from one of the host bridge's
pm_ops callbacks.
Stacktrace for posterity:
PM: Syncing filesystems ... [ 38.566237] done.
PM: Preparing system for sleep (mem)
Freezing user space processes ... [ 38.579813] (elapsed 0.001 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
PM: Suspending system (mem)
PM: suspend of devices complete after 152.456 msecs
PM: late suspend of devices complete after 2.809 msecs
PM: noirq suspend of devices complete after 29.863 msecs
suspend debug: Waiting for 5 second(s).
Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
pgd =
c0003000
[
00000000] *pgd=
80000040004003, *pmd=
00000000
Internal error: : 1211 [#1] SMP ARM
Modules linked in:
CPU: 1 PID: 20 Comm: kworker/1:1 Not tainted
4.9.0-rc1-koelsch-00011-g68db9bc814362e7f #3383
Hardware name: Generic R8A7791 (Flattened Device Tree)
Workqueue: events pci_pme_list_scan
task:
eb56e140 task.stack:
eb58e000
PC is at pci_generic_config_read+0x64/0x6c
LR is at rcar_pci_cfg_base+0x64/0x84
pc : [<
c041d7b4>] lr : [<
c04309a0>] psr:
600d0093
sp :
eb58fe98 ip :
c041d750 fp :
00000008
r10:
c0e2283c r9 :
00000000 r8 :
600d0013
r7 :
00000008 r6 :
eb58fed6 r5 :
00000002 r4 :
eb58feb4
r3 :
00000000 r2 :
00000044 r1 :
00000008 r0 :
00000000
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
Control:
30c5387d Table:
6a9f6c80 DAC:
55555555
Process kworker/1:1 (pid: 20, stack limit = 0xeb58e210)
Stack: (0xeb58fe98 to 0xeb590000)
fe80:
00000002 00000044
fea0:
eb6f5800 c041d9b0 eb58feb4 00000008 00000044 00000000 eb78a000 eb78a000
fec0:
00000044 00000000 eb9aff00 c0424bf0 eb78a000 00000000 eb78a000 c0e22830
fee0:
ea8a6fc0 c0424c5c eaae79c0 c0424ce0 eb55f380 c0e22838 eb9a9800 c0235fbc
ff00:
eb55f380 c0e22838 eb55f380 eb9a9800 eb9a9800 eb58e000 eb9a9824 c0e02100
ff20:
eb55f398 c02366c4 eb56e140 eb5631c0 00000000 eb55f380 c023641c 00000000
ff40:
00000000 00000000 00000000 c023a928 cd105598 00000000 40506a34 eb55f380
ff60:
00000000 00000000 dead4ead ffffffff ffffffff eb58ff74 eb58ff74 00000000
ff80:
00000000 dead4ead ffffffff ffffffff eb58ff90 eb58ff90 eb58ffac eb5631c0
ffa0:
c023a844 00000000 00000000 c0206d68 00000000 00000000 00000000 00000000
ffc0:
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
ffe0:
00000000 00000000 00000000 00000000 00000013 00000000 3a81336c 10ccd1dd
[<
c041d7b4>] (pci_generic_config_read) from [<
c041d9b0>]
(pci_bus_read_config_word+0x58/0x80)
[<
c041d9b0>] (pci_bus_read_config_word) from [<
c0424bf0>]
(pci_check_pme_status+0x34/0x78)
[<
c0424bf0>] (pci_check_pme_status) from [<
c0424c5c>] (pci_pme_wakeup+0x28/0x54)
[<
c0424c5c>] (pci_pme_wakeup) from [<
c0424ce0>] (pci_pme_list_scan+0x58/0xb4)
[<
c0424ce0>] (pci_pme_list_scan) from [<
c0235fbc>]
(process_one_work+0x1bc/0x308)
[<
c0235fbc>] (process_one_work) from [<
c02366c4>] (worker_thread+0x2a8/0x3e0)
[<
c02366c4>] (worker_thread) from [<
c023a928>] (kthread+0xe4/0xfc)
[<
c023a928>] (kthread) from [<
c0206d68>] (ret_from_fork+0x14/0x2c)
Code:
ea000000 e5903000 f57ff04f e3a00000 (
e5843000)
---[ end trace
667d43ba3aa9e589 ]---
Fixes:
df17e62e5bff ("PCI: Add support for polling PME state on suspended legacy PCI devices")
Reported-and-tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reported-and-tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: stable@vger.kernel.org # 2.6.37+
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Matthew Garrett <mjg59@srcf.ucam.org>
Yongji Xie [Mon, 10 Apr 2017 11:58:11 +0000 (19:58 +0800)]
PCI: Fix calculation of bridge window's size and alignment
In case that one device's alignment is greater than its size, we may
get an incorrect size and alignment for its bus's memory window in
pbus_size_mem(). Fix this case.
Signed-off-by: Yongji Xie <elohimes@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Yongji Xie [Wed, 15 Feb 2017 06:50:22 +0000 (14:50 +0800)]
PCI: Ignore requested alignment for IOV BARs
We would call pci_reassigndev_resource_alignment() before
pci_init_capabilities(). So the requested alignment would never work for
IOV BARs.
Furthermore, it's meaningless to request additional alignment for IOV BARs,
the IOV BAR alignment is only determined by the VF BAR size.
Signed-off-by: Yongji Xie <xyjxie@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Matthias Kaehlcke [Fri, 14 Apr 2017 20:38:02 +0000 (13:38 -0700)]
PCI: Make PCI_ROM_ADDRESS_MASK a 32-bit constant
A 64-bit value is not needed since a PCI ROM address consists in 32 bits.
This fixes a clang warning about "implicit conversion from 'unsigned long'
to 'u32'".
Also remove now unnecessary casts to u32 from __pci_read_base() and
pci_std_update_resource().
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Marc Gonzalez [Tue, 18 Apr 2017 19:21:04 +0000 (14:21 -0500)]
PCI: Change pci_host_common_probe() visibility
pci_host_common_probe() is defined when CONFIG_PCI_HOST_COMMON=y;
therefore the function declaration should match that.
drivers/pci/host/pcie-tango.c:300:9: error:
implicit declaration of function 'pci_host_common_probe'
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Marc Gonzalez [Mon, 10 Apr 2017 17:46:54 +0000 (19:46 +0200)]
PCI: Improve __pci_read_base() robustness
Local variables 'l' and 'sz' are uninitialized. Normally, they would
be initialized by pci_read_config_dword() but when an error occurs,
some drivers immediately return an error code, which leaves the
argument uninitialized.
Provide a safe initial value to make the code more robust.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Christoph Hellwig [Thu, 13 Apr 2017 07:06:43 +0000 (09:06 +0200)]
nvme/pci: Switch to pci_request_irq()
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Christoph Hellwig [Thu, 13 Apr 2017 07:06:42 +0000 (09:06 +0200)]
PCI/irq: Add pci_request_irq() and pci_free_irq() helpers
These are small wrappers around request_threaded_irq() and free_irq(),
which dynamically allocate space for the device name so that drivers don't
need to keep static buffers for these around. Additionally it works with
device-relative vector numbers to make the usage easier, and force the
IRQF_SHARED flag on given that it has no runtime overhead and should be
supported by all PCI devices.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / log