GitHub/moto-9609/android_kernel_motorola_exynos9610.git
10 years agodrm/i915/chv: Handle video DIP registers on CHV
Ville Syrjälä [Wed, 9 Apr 2014 10:29:09 +0000 (13:29 +0300)]
drm/i915/chv: Handle video DIP registers on CHV

The DIP registers are a mess on VLV and CHV. The register block on pipe
A is different than the register block on pipes B and C. In order to
handle that using the pipe offsets, we'd need a new pipe offset per
register, which seems wasteful. So instead just use the _PIPE3() macro
to handle these registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Don't use pipe_offset stuff for DPLL registers
Ville Syrjälä [Wed, 9 Apr 2014 10:29:08 +0000 (13:29 +0300)]
drm/i915: Don't use pipe_offset stuff for DPLL registers

These are just single registers so wasting space for the pipe offsets
seems a bit pointless. So just use the _PIPE3() macro instead.

Also rewrite the _PIPE3() macro to be more obvious, and protect the
arguments properly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Frob conflict.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Force PHY clock buffers off after PLL disable
Ville Syrjälä [Tue, 27 May 2014 13:32:55 +0000 (16:32 +0300)]
drm/i915/chv: Force PHY clock buffers off after PLL disable

Now that we forced the clock buffers on in .pre_pll_enable() we
should probably undo the damage after we've turned the PLL off.

We do the clock buffer force enable in the .pre_pll_enable() hook
as we need to know which port is going to be used, but in the disable
case we don't need the port since we just disable the clock buffers
to both channels. So we can do this in chv_disable_pll() instead
of having to add any kind of .post_pll_disable() hook.

v2: Improve the commit message

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Force clock buffer enables
Ville Syrjälä [Tue, 27 May 2014 13:30:18 +0000 (16:30 +0300)]
drm/i915/chv: Force clock buffer enables

Try to force the PHY clock buffer enables to make the clock routing
work.

v2: Fix the pipe B case to actually enable CH0 clock buffers

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Try to program the PHY used clock channel overrides
Ville Syrjälä [Wed, 9 Apr 2014 10:29:05 +0000 (13:29 +0300)]
drm/i915/chv: Try to program the PHY used clock channel overrides

These should make it possible to feed port C from pipe A or port B from
pipe B. Didn't quite seem to work though.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Freq(opcode) request for CHV.
Deepak S [Fri, 23 May 2014 15:30:21 +0000 (21:00 +0530)]
drm/i915/chv: Freq(opcode) request for CHV.

On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.

v2: Avoid vairable for freq request (ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
Ville Syrjälä [Fri, 23 May 2014 15:30:19 +0000 (21:00 +0530)]
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.

This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
Ville Syrjälä [Fri, 23 May 2014 15:30:18 +0000 (21:00 +0530)]
drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0

Skip __gen6_gt_wait_for_thread_c0() on CHV.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Enable RPS (Turbo) for Cherryview
Deepak S [Tue, 27 May 2014 10:29:30 +0000 (15:59 +0530)]
drm/i915/chv: Enable RPS (Turbo) for Cherryview

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

v6: Rename the variables to match the spec (Mika)

v7: change min/max freq variable naming to match spec (Mika)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: Keep vblank interrupts enabled while enabling/disabling planes
Ville Syrjälä [Thu, 22 May 2014 14:48:06 +0000 (17:48 +0300)]
drm/i915: Keep vblank interrupts enabled while enabling/disabling planes

Because of the upcoming vblank interrupt driven watermark update
mechanism we will have use for vblank interrupts during plane
enabling/disabling. So don't call drm_vblank_off() until planes
are off, and call drm_vblank_on() just before we start to enable
the planes.

v2: Pimp commit message (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake...
Deepak S [Fri, 23 May 2014 15:30:16 +0000 (21:00 +0530)]
drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff

Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.

Streamline the CHV forcewake functions just like was done for VLV.

This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register access, with
FORCEFAKE_ALL both times.

v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
    Re-factor CHV/VLV Forcewake offsets (Ben)

v3: Fix for decrementing fw count in chv read/write. (Deepak)

v4: Squash the patches (Mika)

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[vsyrjala: Move the register range macros into intel_uncore.c]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915/chv: Enable Render Standby (RC6) for Cherryview
Deepak S [Fri, 23 May 2014 15:30:15 +0000 (21:00 +0530)]
drm/i915/chv: Enable Render Standby (RC6) for Cherryview

v2: Configure PCBR if BIOS fails allocate pcbr (deepak)

v3: Fix PCBR condition check during CHV RC6 Enable flag set

v4: Fixup PCBR comment msg. (Chris)
    Rebase against latest code (Deak)
    Fixup Spurious hunk (Ben)

v5: Fix PCBR and commentis msg (mika)

v6: Rebase patch on latest nightly (Deepak)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agodrm/i915: move psr_setup_done to psr struct
Rodrigo Vivi [Fri, 23 May 2014 20:45:51 +0000 (13:45 -0700)]
drm/i915: move psr_setup_done to psr struct

"Because our driver assumes only one panel is PSR capable, and we
already have other PSR information on dev_priv instead of intel_dp. If
we ever support multiple PSR panels, we'll have to move struct
i915_psr to intel_dp anyway." (by Paulo)

v2: Avoid more than one setup. Removing initialization
    and trusting allocation. (By Paulo Zanoni).
v3: rebase.
v4: Adding comment.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
10 years agoMerge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux...
Dave Airlie [Wed, 11 Jun 2014 06:28:10 +0000 (16:28 +1000)]
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

display rework fixes lots of displayport issues.

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (43 commits)
  drm/nouveau/disp/dp: fix tmds passthrough on dp connector
  drm/nouveau/dp: probe dpcd to determine connectedness
  drm/nv50-: trigger update after all connectors disabled
  drm/nv50-: prepare for attaching a SOR to multiple heads
  drm/gf119-/disp: fix debug output on update failure
  drm/nouveau/disp/dp: make use of postcursor when its available
  drm/g94-/disp/dp: take max pullup value across all lanes
  drm/nouveau/bios/dp: parse lane postcursor data
  drm/nouveau/dp: fix support for dpms
  drm/nouveau: register a drm_dp_aux channel for each dp connector
  drm/g94-/disp: add method to power-off dp lanes
  drm/nouveau/disp/dp: maintain link in response to hpd signal
  drm/g94-/disp: bash and wait for something after changing lane power regs
  drm/nouveau/disp/dp: split link config/power into two steps
  drm/nv50/disp: train PIOR-attached DP from second supervisor
  drm/nouveau/disp/dp: make use of existing output data for link training
  drm/gf119/disp: start removing direct vbios parsing from supervisor
  drm/nv50/disp: start removing direct vbios parsing from supervisor
  drm/nouveau/disp/dp: maintain receiver caps in response to hpd signal
  drm/nouveau/disp/dp: create subclass for dp outputs
  ...

10 years agodrm/nouveau/disp/dp: fix tmds passthrough on dp connector
Ben Skeggs [Wed, 11 Jun 2014 03:06:48 +0000 (13:06 +1000)]
drm/nouveau/disp/dp: fix tmds passthrough on dp connector

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/dp: probe dpcd to determine connectedness
Ben Skeggs [Fri, 6 Jun 2014 08:09:55 +0000 (18:09 +1000)]
drm/nouveau/dp: probe dpcd to determine connectedness

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nv50-: trigger update after all connectors disabled
Ben Skeggs [Thu, 5 Jun 2014 02:56:35 +0000 (12:56 +1000)]
drm/nv50-: trigger update after all connectors disabled

We were sending the necessary state changes to unset the mode, but
never actually hit the big GO button unless another modeset happens
afterwards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nv50-: prepare for attaching a SOR to multiple heads
Ben Skeggs [Thu, 5 Jun 2014 00:59:55 +0000 (10:59 +1000)]
drm/nv50-: prepare for attaching a SOR to multiple heads

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/gf119-/disp: fix debug output on update failure
Ben Skeggs [Wed, 4 Jun 2014 01:43:50 +0000 (11:43 +1000)]
drm/gf119-/disp: fix debug output on update failure

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: make use of postcursor when its available
Ben Skeggs [Tue, 3 Jun 2014 04:48:18 +0000 (14:48 +1000)]
drm/nouveau/disp/dp: make use of postcursor when its available

And at the same time, obey the spec better wrt out-of-range requests.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/g94-/disp/dp: take max pullup value across all lanes
Ben Skeggs [Tue, 3 Jun 2014 02:56:18 +0000 (12:56 +1000)]
drm/g94-/disp/dp: take max pullup value across all lanes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/bios/dp: parse lane postcursor data
Ben Skeggs [Tue, 3 Jun 2014 02:47:31 +0000 (12:47 +1000)]
drm/nouveau/bios/dp: parse lane postcursor data

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/dp: fix support for dpms
Ben Skeggs [Fri, 30 May 2014 15:48:06 +0000 (01:48 +1000)]
drm/nouveau/dp: fix support for dpms

SOR_PWR has no effect to power-off DP links, unlike other SOR protocols.

Instead, on the source side, we cut power to the lanes after having put
the sink into D3.  Link training takes care of everything required to
bring it back again.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau: register a drm_dp_aux channel for each dp connector
Ben Skeggs [Fri, 30 May 2014 06:20:58 +0000 (16:20 +1000)]
drm/nouveau: register a drm_dp_aux channel for each dp connector

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/g94-/disp: add method to power-off dp lanes
Ben Skeggs [Mon, 26 May 2014 02:09:06 +0000 (12:09 +1000)]
drm/g94-/disp: add method to power-off dp lanes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: maintain link in response to hpd signal
Ben Skeggs [Tue, 20 May 2014 00:18:03 +0000 (10:18 +1000)]
drm/nouveau/disp/dp: maintain link in response to hpd signal

This previously worked for the most part due to userspace doing a
modeset in response to HPD interrupts.  This will allow us to
properly handle cases where sync is lost for other reasons, or if
userspace isn't caring.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/g94-/disp: bash and wait for something after changing lane power regs
Ben Skeggs [Mon, 26 May 2014 02:00:07 +0000 (12:00 +1000)]
drm/g94-/disp: bash and wait for something after changing lane power regs

Some kind of update?  Needed to make the power-down take effect at least.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: split link config/power into two steps
Ben Skeggs [Mon, 26 May 2014 01:57:57 +0000 (11:57 +1000)]
drm/nouveau/disp/dp: split link config/power into two steps

We want to be able to power down the lanes for DPMS off.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nv50/disp: train PIOR-attached DP from second supervisor
Ben Skeggs [Tue, 27 May 2014 05:00:36 +0000 (15:00 +1000)]
drm/nv50/disp: train PIOR-attached DP from second supervisor

Same place as for SOR, between detach and attach phases.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: make use of existing output data for link training
Ben Skeggs [Mon, 19 May 2014 04:06:07 +0000 (14:06 +1000)]
drm/nouveau/disp/dp: make use of existing output data for link training

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/gf119/disp: start removing direct vbios parsing from supervisor
Ben Skeggs [Wed, 21 May 2014 01:39:07 +0000 (11:39 +1000)]
drm/gf119/disp: start removing direct vbios parsing from supervisor

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nv50/disp: start removing direct vbios parsing from supervisor
Ben Skeggs [Wed, 21 May 2014 01:24:43 +0000 (11:24 +1000)]
drm/nv50/disp: start removing direct vbios parsing from supervisor

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: maintain receiver caps in response to hpd signal
Ben Skeggs [Mon, 19 May 2014 01:54:09 +0000 (11:54 +1000)]
drm/nouveau/disp/dp: maintain receiver caps in response to hpd signal

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: create subclass for dp outputs
Ben Skeggs [Sat, 17 May 2014 01:19:54 +0000 (11:19 +1000)]
drm/nouveau/disp/dp: create subclass for dp outputs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau: use connector events for HPD instead of GPIO watching
Ben Skeggs [Fri, 30 May 2014 02:49:17 +0000 (12:49 +1000)]
drm/nouveau: use connector events for HPD instead of GPIO watching

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp: add internal representaion of output paths and connectors
Ben Skeggs [Fri, 16 May 2014 04:36:15 +0000 (14:36 +1000)]
drm/nouveau/disp: add internal representaion of output paths and connectors

This will, at some point, be used to replace various bits and pieces of
code doing direct bios parsing.  For now, it'll just be used for some
DP improvements.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/bios: extend connector table parsing
Ben Skeggs [Wed, 14 May 2014 01:10:02 +0000 (11:10 +1000)]
drm/nouveau/bios: extend connector table parsing

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp: nothing to see here
Ben Skeggs [Wed, 14 May 2014 00:26:02 +0000 (10:26 +1000)]
drm/nouveau/disp: nothing to see here

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c/anx9805: add debugging to aux transactions
Ben Skeggs [Wed, 11 Jun 2014 00:28:18 +0000 (10:28 +1000)]
drm/nouveau/i2c/anx9805: add debugging to aux transactions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: introduce locking at a per-port level
Ben Skeggs [Thu, 29 May 2014 01:35:10 +0000 (11:35 +1000)]
drm/nouveau/i2c: introduce locking at a per-port level

There's also provisions to allow a pad to be locked with a specific
routing, for an indefinite period of time.  This will be used in
future patches.

The G94+ pad driver will now also power-down pads when not required.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: balance port acquire/release
Ben Skeggs [Thu, 29 May 2014 01:07:16 +0000 (11:07 +1000)]
drm/nouveau/i2c: balance port acquire/release

This was a half-finished hack before, just enough to handle the shared
aux/i2c pad thing on G94 and up.

We got lucky with locking etc up until now, as this was (generally) all
protected by the DRM mode_config lock.  It's about to become a lot more
likely to hit the races.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/gk104/i2c: add aux channel interrupt driver
Ben Skeggs [Tue, 13 May 2014 04:53:34 +0000 (14:53 +1000)]
drm/gk104/i2c: add aux channel interrupt driver

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/g94/i2c: add aux channel interrupt driver
Ben Skeggs [Tue, 13 May 2014 04:50:25 +0000 (14:50 +1000)]
drm/g94/i2c: add aux channel interrupt driver

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: add interfaces to support handling aux channel interrupts
Ben Skeggs [Tue, 13 May 2014 04:47:36 +0000 (14:47 +1000)]
drm/nouveau/i2c: add interfaces to support handling aux channel interrupts

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: start hiding subdev-internal interfaces
Ben Skeggs [Tue, 13 May 2014 03:59:26 +0000 (13:59 +1000)]
drm/nouveau/i2c: start hiding subdev-internal interfaces

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: remove unnecessary i2c_set_adapdata()
Ben Skeggs [Wed, 7 May 2014 02:41:29 +0000 (12:41 +1000)]
drm/nouveau/i2c: remove unnecessary i2c_set_adapdata()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: properly hand aux reply back to caller, and only retry on defer
Ben Skeggs [Wed, 7 May 2014 05:13:45 +0000 (15:13 +1000)]
drm/nouveau/i2c: properly hand aux reply back to caller, and only retry on defer

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nv50-/mc: also pass PMGR interrupts onto I2C subdev
Ben Skeggs [Tue, 13 May 2014 04:36:49 +0000 (14:36 +1000)]
drm/nv50-/mc: also pass PMGR interrupts onto I2C subdev

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: send separate event types for high/low transitions
Ben Skeggs [Tue, 13 May 2014 05:54:17 +0000 (15:54 +1000)]
drm/nouveau/gpio: send separate event types for high/low transitions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: use base constructor for all implementations
Ben Skeggs [Tue, 13 May 2014 00:33:23 +0000 (10:33 +1000)]
drm/nouveau/gpio: use base constructor for all implementations

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: move on-reset intr disable-and-ack to common code
Ben Skeggs [Tue, 13 May 2014 00:17:35 +0000 (10:17 +1000)]
drm/nouveau/gpio: move on-reset intr disable-and-ack to common code

Re-uses the implementation's accessor functions rather than requiring
and init/fini implementation for each chipset.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: split "toggled" interrupt into "went high" / "went low"
Ben Skeggs [Mon, 12 May 2014 06:14:11 +0000 (16:14 +1000)]
drm/nouveau/gpio: split "toggled" interrupt into "went high" / "went low"

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: split g92 class from nv50
Ben Skeggs [Mon, 12 May 2014 05:22:42 +0000 (15:22 +1000)]
drm/nouveau/gpio: split g92 class from nv50

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/gpio: use indirect pointer to base class definition
Ben Skeggs [Mon, 12 May 2014 04:18:06 +0000 (14:18 +1000)]
drm/nouveau/gpio: use indirect pointer to base class definition

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support training to highest rate, rather than a target
Ben Skeggs [Fri, 16 May 2014 00:49:28 +0000 (10:49 +1000)]
drm/nouveau/disp/dp: support training to highest rate, rather than a target

We really want this for, at least, MST devices.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support postcursor in link training
Ben Skeggs [Thu, 15 May 2014 12:20:40 +0000 (22:20 +1000)]
drm/nouveau/disp/dp: support postcursor in link training

Not enabled at the backends yet, but will read status and send back max
reached at level 0.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/core: allow event source to handle multiple event types per index
Ben Skeggs [Tue, 13 May 2014 05:30:15 +0000 (15:30 +1000)]
drm/nouveau/core: allow event source to handle multiple event types per index

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agoMerge branch 'topic/ipu-destaging' of git://git.pengutronix.de/git/pza/linux into...
Dave Airlie [Wed, 11 Jun 2014 00:13:58 +0000 (10:13 +1000)]
Merge branch 'topic/ipu-destaging' of git://git.pengutronix.de/git/pza/linux into drm-next

Destage IPUv3

* 'topic/ipu-destaging' of git://git.pengutronix.de/git/pza/linux:
  gpu: ipu-v3: Register the CSI modules
  gpu: ipu-v3: Add CSI and SMFC module enable wrappers
  gpu: ipu-v3: Add ipu_idmac_get_current_buffer function
  gpu: ipu-v3: Add SMFC code
  gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging

10 years agoMerge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux...
Dave Airlie [Tue, 10 Jun 2014 06:39:21 +0000 (16:39 +1000)]
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

There's really not a great deal this time due to me spending most of this window on Maxwell.  But, here's the random bits and pieces that's currently queued.
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (25 commits)
  drm/gk208/gr: add missing registers to grctx init
  drm/nouveau/kms/nv04-nv40: fix pageflip events via special case.
  drm/nv50-/mc: fix kms pageflip events by reordering irq handling order.
  drm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.
  drm/nv50-/kms: wait for enough ring space in crtc_prepare()
  drm/nouveau/disp/dp: support training pattern 3
  drm/nouveau/disp/dp: support aux read interval during link training
  drm/gk104/gpio: fix incorrect interrupt register usage
  drm/nouveau/core: punt all object state change messages to trace level
  drm/nouveau/clk: allow end-user reclocking for nv40, nvaa, and nve0 clock types
  drm/nouveau/fb: default NvMemExec to on, turning it off is used for debugging only
  drm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function
  drm/nouveau/i2c: bump the i2c delay for the adt7473
  drm/nouveau/therm/fan/tach: default to 2 pulses per revolution
  drm/nvf0/device: enable video decoding engines on gk110/gk208
  drm/nvf1/device: add support for 0xf1 (gk110b)
  drm/nouveau/device: support for probing GK20A
  drm/nouveau/graph: add GK20A support
  drm/nouveau/graph: pad firmware code at load time
  drm/nouveau/graph: enable when using external fw
  ...

10 years agodrm/gk208/gr: add missing registers to grctx init
Ilia Mirkin [Sat, 7 Jun 2014 19:39:45 +0000 (15:39 -0400)]
drm/gk208/gr: add missing registers to grctx init

This fixes hangs on GK208 which happen instantaneously on trying to use a
geometry shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org # v3.14+
10 years agodrm/nouveau/kms/nv04-nv40: fix pageflip events via special case.
Mario Kleiner [Mon, 12 May 2014 22:42:08 +0000 (00:42 +0200)]
drm/nouveau/kms/nv04-nv40: fix pageflip events via special case.

Cards with nv04 display engine can't reliably use vblank
counts and timestamps computed via drm_handle_vblank(), as
the function gets invoked after sending the pageflip events.

Fix this by defaulting to the old crtcid = -1 fallback path
on <= NV-50 cards, and only using the precise path on NV-50
and later.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: <stable@vger.kernel.org> # 3.13+
10 years agodrm/nv50-/mc: fix kms pageflip events by reordering irq handling order.
Mario Kleiner [Wed, 19 Mar 2014 07:12:51 +0000 (08:12 +0100)]
drm/nv50-/mc: fix kms pageflip events by reordering irq handling order.

Whenever a single nouveau_mc_intr() main gpu irq-handler invocation was
responsible for calling both, the vblank-irq handler (display engine irq)
and kms-pageflip completion handler (from fifo irq), the order of
invocation was wrong. nouveau_finish_flip() was called before
drm_handle_vblank() for the vblank of pageflip completion, so the
emitted pageflip event contained stale vblank count and timestamp
from previous vblank. This caused failure in userspace to timestamp
properly.

Reorder order of invocation of engine irq handlers: Put
NVDEV_ENGINE_DISP always on top, and thereby before NVDEV_ENGINE_FIFO,
so that drm_handle_vblank() gets called to update vblank timestamps
and count before potential pageflip events make use of that
information.

This works on nv-50 and later, where kms-pageflip completion triggers
an irq either after a separate vblank irq, or both pageflip and vblank
trigger one common irq invocation, but never before vblank irqs.

v2 (Ben):
- removed mods for nv04-nv40, it doesn't help there anyway
- this is considered a hack, and a better solution should be found

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: <stable@vger.kernel.org> # 3.13+
10 years agodrm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.
Mario Kleiner [Wed, 28 May 2014 03:22:18 +0000 (05:22 +0200)]
drm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.

nv04_disp_scanoutpos() must abort to trigger simple timestamping
fallback if vtotal/htotal regs return zero. This happens if the
output isn't a digital output, but a vga analog output, as the
regs don't get initialized in that case.

Fixes timestamping failure on nv-40 and earlier with vga output.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: <stable@vger.kernel.org> # 3.14+
10 years agodrm/nv50-/kms: wait for enough ring space in crtc_prepare()
Ben Skeggs [Mon, 19 May 2014 04:54:33 +0000 (14:54 +1000)]
drm/nv50-/kms: wait for enough ring space in crtc_prepare()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support training pattern 3
Ben Skeggs [Thu, 15 May 2014 12:00:06 +0000 (22:00 +1000)]
drm/nouveau/disp/dp: support training pattern 3

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/disp/dp: support aux read interval during link training
Ben Skeggs [Thu, 15 May 2014 11:50:07 +0000 (21:50 +1000)]
drm/nouveau/disp/dp: support aux read interval during link training

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/gk104/gpio: fix incorrect interrupt register usage
Ben Skeggs [Mon, 12 May 2014 04:12:32 +0000 (14:12 +1000)]
drm/gk104/gpio: fix incorrect interrupt register usage

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/core: punt all object state change messages to trace level
Ben Skeggs [Fri, 16 May 2014 03:52:19 +0000 (13:52 +1000)]
drm/nouveau/core: punt all object state change messages to trace level

Leave debug for the more interesting bits of info.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/clk: allow end-user reclocking for nv40, nvaa, and nve0 clock types
Ilia Mirkin [Sun, 18 May 2014 05:04:16 +0000 (01:04 -0400)]
drm/nouveau/clk: allow end-user reclocking for nv40, nvaa, and nve0 clock types

Use with caution.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/fb: default NvMemExec to on, turning it off is used for debugging only
Ilia Mirkin [Sun, 18 May 2014 05:04:15 +0000 (01:04 -0400)]
drm/nouveau/fb: default NvMemExec to on, turning it off is used for debugging only

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function
Martin Peres [Thu, 3 Apr 2014 20:12:41 +0000 (22:12 +0200)]
drm/nouveau/bios: fix a potential NULL deref in the PROM shadowing function

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/i2c: bump the i2c delay for the adt7473
Martin Peres [Sun, 25 May 2014 22:42:13 +0000 (00:42 +0200)]
drm/nouveau/i2c: bump the i2c delay for the adt7473

Some adt7473 can't manage the 20µs delay we use for the bitbanging, bumping
it to 40µs seem to do the trick.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Tested-by: Marcel Dopita <mdop@seznam.cz>
10 years agodrm/nouveau/therm/fan/tach: default to 2 pulses per revolution
Martin Peres [Mon, 12 May 2014 21:19:07 +0000 (23:19 +0200)]
drm/nouveau/therm/fan/tach: default to 2 pulses per revolution

I spent some time this weekend trying to find in the vbios the number of
pulses per revolutions in the vbios but couldn't find it. It would seem
all my cards have 2 pulses per revolution so let's stick to that until
further notice.

Thermal table's id 0x48 may indicate this information but it would seem
that changing the value results in the blob power or clock gating the
RPM counter... We should ask NVIDIA about that, should be trivial-enough
for them to answer.

Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nvf0/device: enable video decoding engines on gk110/gk208
John Rowley [Mon, 12 May 2014 21:34:57 +0000 (21:34 +0000)]
drm/nvf0/device: enable video decoding engines on gk110/gk208

Only tested on nvf1, was advised to enable on all.

Signed-off-by: John Rowley <john.rowley08@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nvf1/device: add support for 0xf1 (gk110b)
John Rowley [Mon, 12 May 2014 21:34:56 +0000 (21:34 +0000)]
drm/nvf1/device: add support for 0xf1 (gk110b)

Signed-off-by: John Rowley <john.rowley08@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/device: support for probing GK20A
Alexandre Courbot [Fri, 2 May 2014 09:32:42 +0000 (18:32 +0900)]
drm/nouveau/device: support for probing GK20A

Set the correct subdev/engine classes when GK20A (0xea) is probed.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/graph: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:41 +0000 (18:32 +0900)]
drm/nouveau/graph: add GK20A support

Add a GR device for GK20A based on NVE4, with the correct classes
definitions (GK20A's 3D class is 0xa297).

Most of the NVE4 code can be used on GK20A, so make relevant bits of
NVE4 available to other chips as well.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/graph: pad firmware code at load time
Alexandre Courbot [Fri, 2 May 2014 09:32:40 +0000 (18:32 +0900)]
drm/nouveau/graph: pad firmware code at load time

Pad the microcode to a multiple of 0x40 words, otherwise firmware will
fail to run from non-prepadded firmware files.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/graph: enable when using external fw
Alexandre Courbot [Fri, 2 May 2014 09:32:39 +0000 (18:32 +0900)]
drm/nouveau/graph: enable when using external fw

nvc0_graph_ctor() would only let the graphics engine be enabled if its
oclass has a proper microcode linked to it. This prevents GR from being
enabled at all on chips that rely exclusively on external firmware, even
though such a use-case is valid.

Relax the conditions enabling the GR engine to also include the case
where an external firmware has also been loaded.

Also switch to external firmware if the graph class has no microcode
linked to it.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/fifo: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:38 +0000 (18:32 +0900)]
drm/nouveau/fifo: add GK20A support

GK20A's FIFO is compatible with NVE0, but only features 128 channels and
1 runlist.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/fb: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:37 +0000 (18:32 +0900)]
drm/nouveau/fb: add GK20A support

Add a simple FB device for GK20A, as well as a RAM implementation
suitable for chips that use system memory as video RAM.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/ibus: add GK20A support
Alexandre Courbot [Fri, 2 May 2014 09:32:36 +0000 (18:32 +0900)]
drm/nouveau/ibus: add GK20A support

Add support for initializing the priv ring of GK20A. This is done by the
BIOS on desktop GPUs, but needs to be done by hand on Tegra.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nvc0/bar: support chips without BAR3
Alexandre Courbot [Fri, 2 May 2014 09:32:35 +0000 (18:32 +0900)]
drm/nvc0/bar: support chips without BAR3

Adapt the NVC0 BAR driver to make it able to support chips that do not
expose a BAR3. When this happens, BAR1 is then used for USERD mapping
and the BAR alloc() functions is disabled, making GPU objects unable
to rely on BAR for data access and falling back to PRAMIN.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agodrm/nouveau/bar: only ioremap BAR3 if it exists
Alexandre Courbot [Fri, 2 May 2014 09:32:34 +0000 (18:32 +0900)]
drm/nouveau/bar: only ioremap BAR3 if it exists

Some chips that use system memory exclusively (e.g. GK20A) do not
expose 2 BAR regions. For them only BAR1 exists, and it should be used
for USERD mapping. Do not map BAR3 if its resource does not exist.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
10 years agoMerge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm...
Dave Airlie [Tue, 10 Jun 2014 03:09:01 +0000 (13:09 +1000)]
Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next

Some additional patches for radeon for 3.16 now that -fixes has been merged.

- Gart fix for all asics r6xx+
- Add some VM tuning parameters
- misc fixes

* 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip
  drm/radeon/dpm: powertune updates for SI
  Revert "drm/radeon: use variable UVD clocks"
  drm/radeon: add query for number of active CUs
  drm/radeon: add debugfs file to trigger GPU reset
  drm/radeon: make vm_block_size a module parameter
  drm/radeon: make VM size a module parameter (v2)
  drm/radeon: rename alt_domain to allowed_domains
  drm/radeon: use the SDMA on for buffer moves on CIK again
  drm/radeon: remove range check from *_gart_set_page
  drm/radeon: stop poisoning the GART TLB
  drm/radeon: hdmi deep color modes must obey clock limit of sink.
  drm/edid: Store all supported hdmi deep color modes in drm_display_info
  drm/radeon: add missing vce init case for hawaii
  drm/radeon: use lower_32_bits where appropriate

10 years agodrm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip
Michel Dänzer [Tue, 10 Jun 2014 01:21:57 +0000 (10:21 +0900)]
drm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip

Fixes WARN()s from the DRM core since the page flip rework.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=77521
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon/dpm: powertune updates for SI
Alex Deucher [Fri, 6 Jun 2014 22:58:10 +0000 (18:58 -0400)]
drm/radeon/dpm: powertune updates for SI

Updated powertune settings for certain SI asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agoRevert "drm/radeon: use variable UVD clocks"
Alex Deucher [Sat, 7 Jun 2014 15:31:25 +0000 (11:31 -0400)]
Revert "drm/radeon: use variable UVD clocks"

This caused reduced performance for some users with advanced post
processing enabled.  We need a better method to pick the
UVD state based on the amount of post processing required or tune
the advanced post processing to fit within the lower power state
envelope.

This reverts commit 14a9579ddbf15dd1992a9481a4ec80b0b91656d5.
Cc: "3.15" <stable@vger.kernel.org>
10 years agodrm/radeon: add query for number of active CUs
Alex Deucher [Mon, 2 Jun 2014 20:13:21 +0000 (16:13 -0400)]
drm/radeon: add query for number of active CUs

Query to find out how many compute units on a GPU.
Useful for OpenCL usermode drivers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: add debugfs file to trigger GPU reset
Christian König [Mon, 2 Jun 2014 15:33:10 +0000 (17:33 +0200)]
drm/radeon: add debugfs file to trigger GPU reset

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: make vm_block_size a module parameter
Christian König [Fri, 6 Jun 2014 03:56:50 +0000 (23:56 -0400)]
drm/radeon: make vm_block_size a module parameter

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: make VM size a module parameter (v2)
Christian König [Fri, 6 Jun 2014 03:47:32 +0000 (23:47 -0400)]
drm/radeon: make VM size a module parameter (v2)

v2: agd5f: simplify patch

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: rename alt_domain to allowed_domains
Christian König [Mon, 2 Jun 2014 15:33:07 +0000 (17:33 +0200)]
drm/radeon: rename alt_domain to allowed_domains

And also domain to prefered_domains. That matches better
what those values represent.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: use the SDMA on for buffer moves on CIK again
Christian König [Wed, 4 Jun 2014 13:29:58 +0000 (15:29 +0200)]
drm/radeon: use the SDMA on for buffer moves on CIK again

The underlying reason for the crashes seems to be fixed now.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: remove range check from *_gart_set_page
Christian König [Wed, 4 Jun 2014 13:29:57 +0000 (15:29 +0200)]
drm/radeon: remove range check from *_gart_set_page

We never check the return value anyway and if the
index isn't valid would crash way before calling
the functions.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: stop poisoning the GART TLB
Christian König [Wed, 4 Jun 2014 13:29:56 +0000 (15:29 +0200)]
drm/radeon: stop poisoning the GART TLB

When we set the valid bit on invalid GART entries they are
loaded into the TLB when an adjacent entry is loaded. This
poisons the TLB with invalid entries which are sometimes
not correctly removed on TLB flush.

For stable inclusion the patch probably needs to be modified a bit.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: hdmi deep color modes must obey clock limit of sink.
Mario Kleiner [Thu, 5 Jun 2014 13:58:24 +0000 (09:58 -0400)]
drm/radeon: hdmi deep color modes must obey clock limit of sink.

Make sure that a hdmi deep color mode can't exceed the max tmds
clock limit of a hdmi sink if such a limit is defined by edid.

If requested deep color bpc would exceed the limit given the mode
to be set, try to degrade gracefully to lower supported deep color
bpc or to standard 8 bpc if needed.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/edid: Store all supported hdmi deep color modes in drm_display_info
Mario Kleiner [Thu, 5 Jun 2014 13:52:10 +0000 (09:52 -0400)]
drm/edid: Store all supported hdmi deep color modes in drm_display_info

HDMI deep color setup must know which modes are supported if
it needs to degrade gracefully, as only 12 bpc / dc_36 is
guaranteed, but 10 bpc / dc_30 is optional. The maximum bpc
is not sufficient for this.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
10 years agodrm/radeon: add missing vce init case for hawaii
Alex Deucher [Fri, 6 Jun 2014 03:01:03 +0000 (23:01 -0400)]
drm/radeon: add missing vce init case for hawaii

Hawaii has the same version of VCE as other CIK parts.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
10 years agodrm/radeon: use lower_32_bits where appropriate
Christian König [Tue, 3 Jun 2014 18:51:46 +0000 (20:51 +0200)]
drm/radeon: use lower_32_bits where appropriate

Replace occurrences of "v & 0xffffffff" with lower_32_bits(v)
when it's next to an upper_32_bits(v). Also remove unnecessary
"upper_32_bits(v) & 0xffffffff" code snippets.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>