Huang Rui [Fri, 3 Mar 2017 21:20:35 +0000 (16:20 -0500)]
drm/amdgpu: rework common ucode handling for vega10
Handle ucode differences in vega10.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Fri, 3 Mar 2017 21:03:15 +0000 (16:03 -0500)]
drm/amdgpu: don't validate TILE_SPLIT on GFX9
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Mar 2017 21:00:11 +0000 (16:00 -0500)]
drm/amdgpu: add tiling flags for GFX9 (v2)
v2: Marek: allow shifts >32 in AMDGPU_TILING_SET/GET
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Mar 2017 20:54:06 +0000 (15:54 -0500)]
drm/amdgpu: Add asic family for vega10
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 28 Mar 2017 16:52:08 +0000 (12:52 -0400)]
drm/amdgpu: add NGG parameters
NGG (Next Generation Graphics) is a new feature in GFX9.0. This
adds the relevant parameters.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Mar 2017 20:23:14 +0000 (15:23 -0500)]
drm/amdgpu: add PTE defines for MTYPE
New on SOC-15 asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 6 Dec 2016 08:41:55 +0000 (03:41 -0500)]
drm/amdgpu: add IV trace point
This allows us to grab IVs without spamming the log.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Mar 2017 20:08:30 +0000 (15:08 -0500)]
drm/amdgpu: update IH IV ring entry for soc-15
Reflect the new format on soc-15 asics.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Mar 2017 19:26:51 +0000 (14:26 -0500)]
drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
If the board is atomfirmware based.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Tue, 14 Feb 2017 17:04:52 +0000 (12:04 -0500)]
drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ken Wang [Fri, 18 Mar 2016 07:41:42 +0000 (15:41 +0800)]
drm/amdgpu: add 64bit doorbell assignments
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Mon, 12 Dec 2016 18:40:37 +0000 (13:40 -0500)]
drm/amdgpu: gb_addr_config struct
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 1 Nov 2016 07:35:38 +0000 (15:35 +0800)]
drm/amdgpu: use new flag to handle different firmware loading method
This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ken [Thu, 9 Mar 2017 16:34:42 +0000 (11:34 -0500)]
drm/amdgpu: add clinetid definition for vega10
Signed-off-by: ken <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ken Wang [Wed, 9 Mar 2016 01:28:32 +0000 (09:28 +0800)]
drm/amdgpu: add vega10 chip name
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ken Wang [Mon, 6 Mar 2017 17:41:22 +0000 (12:41 -0500)]
drm/amdgpu: add common soc15 headers
These are used by various IP modules.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 22:49:04 +0000 (17:49 -0500)]
drm/amdgpu: add SDMA 4.0 packet header
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 22:48:14 +0000 (17:48 -0500)]
drm/amdgpu: add gfx9 clearstate header
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Thu, 2 Mar 2017 21:57:08 +0000 (16:57 -0500)]
drm/amd: Add MQD structs for GFX V9
This header defines the gfx v9 MEC structures.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:43:33 +0000 (16:43 -0500)]
drm/amdgpu: add the VCE 4.0 register headers
These are the Video Compression Engine registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:42:58 +0000 (16:42 -0500)]
drm/amdgpu: add the UVD 7.0 register headers
These are the Unifed Video Decoder registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:42:12 +0000 (16:42 -0500)]
drm/amdgpu: add THM 9.0 register headers
These are the THerMal control registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:41:21 +0000 (16:41 -0500)]
drm/amdgpu: add SMUIO 9.0 register headers
These are the System Managment Unit IO registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:40:41 +0000 (16:40 -0500)]
drm/amdgpu: add SDMA 4.0 register headers
These are the System DMA register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:39:12 +0000 (16:39 -0500)]
drm/amdgpu: add OSSSYS 4.0 register headers
These are the OS Services register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:38:26 +0000 (16:38 -0500)]
drm/amdgpu: add NBIO 6.1 register headers
These are the Bus IO registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:37:25 +0000 (16:37 -0500)]
drm/amdgpu: add NBIF 6.1 register headers
These are the Bus InterFace registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:36:07 +0000 (16:36 -0500)]
drm/amdgpu: add MP 9.0 register headers
MP is the system management controller on vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:34:19 +0000 (16:34 -0500)]
drm/amdgpu: add the MMHUB 1.0 register headers
Add the MultiMedia Hub registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:33:31 +0000 (16:33 -0500)]
drm/amdgpu: add the HDP 4.0 register headers
These are the Host Data Path registers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:32:16 +0000 (16:32 -0500)]
drm/amdgpu: add the GC 9.0 register headers
Add the Graphics Core register headers for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:31:08 +0000 (16:31 -0500)]
drm/amdgpu: Add the DCE 12.0 register headers
These are the register headers for the Display
and Composition Engine on vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:30:06 +0000 (16:30 -0500)]
drm/amdgpu: Add ATHUB 1.0 register headers
ATHUB is part of the memory controller on soc15 asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:29:09 +0000 (16:29 -0500)]
drm/amdgpu: add vega10_enum.h
This adds the register bitfield enums for vega10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:28:29 +0000 (16:28 -0500)]
drm/amdgpu: add soc15ip.h
This header defines the IP layout for soc15 based SoCs.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 23 Sep 2016 20:23:41 +0000 (16:23 -0400)]
drm/amdgpu: add basic support for atomfirmware.h (v3)
This adds basic support for asics that use atomfirmware.h
to define their vbios tables.
v2: rebase
v3: squash in num scratch reg fix
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 23 Sep 2016 17:10:49 +0000 (13:10 -0400)]
drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
There will be a slightly different version for atomfirmware.
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 13 Feb 2017 21:01:58 +0000 (16:01 -0500)]
amdgpu: detect if we are using atomfirmware or atombios for vbios (v2)
Supposedly atomfirmware rom header is 3.3 atombios is 1.1.
v2: rebased on newer kernel
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 Mar 2017 21:55:42 +0000 (16:55 -0500)]
drm/amdgpu: add the new atomfirmware interface header
soc15 asics have a new vbios interface. These headers
define that interface.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicolai Hähnle [Thu, 23 Mar 2017 18:36:31 +0000 (19:36 +0100)]
drm/amdgpu: add optional fence out-parameter to amdgpu_vm_clear_freed
We will add the fence to freed buffer objects in a later commit, to ensure
that the underlying memory can only be re-used after all references in
page tables have been cleared.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Mon, 13 Mar 2017 18:15:48 +0000 (14:15 -0400)]
drm/amd/powerplay: restore disabling power containment on Fiji (v2)
Power containment will degrade performance in some compute tests.
Restore disabling it as before code refining in powerplay.
v2: only in the compute profile
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 17:00:20 +0000 (13:00 -0400)]
drm/amdgpu/gfx8: further KIQ parameter cleanup
The ring structure already has what we need.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 06:16:07 +0000 (02:16 -0400)]
drm/amdgpu/gfx8: store the eop gpu addr in the ring structure
Avoids passing around additional parameters during setup.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 06:06:04 +0000 (02:06 -0400)]
drm/amdgpu/gfx8: reduce the functon params for mpq setup
Everything we need is in the ring structure. No need to
pass all the bits explicitly.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 05:51:53 +0000 (01:51 -0400)]
drm/amdgpu/gfx8: reserve kiq eop object before unmapping it
It's required.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 05:40:19 +0000 (01:40 -0400)]
drm/amdgpu/gfx8: fold loops in kiq_resume()
No need to loop through the compute queues twice.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 05:38:11 +0000 (01:38 -0400)]
drm/amdgpu/gfx8: test KIQ before compute rings
If KIQ isn't working, the compute rings won't work either.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 05:35:44 +0000 (01:35 -0400)]
drm/amdgpu/gfx8: reserve mqd objects before mapping them
It's required.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 28 Mar 2017 16:50:32 +0000 (12:50 -0400)]
drm/amdgpu/gfx8: rename some functions
To better match where they are used. Called from sw_init
and sw_fini.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 23 Mar 2017 05:05:08 +0000 (01:05 -0400)]
drm/amdgpu/gfx8: whitespace cleanup
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 21 Mar 2017 04:51:48 +0000 (12:51 +0800)]
drm/amdgpu: load mc firware in driver for Polaris.
load mc ucode in driver if VBIOS not loaded
a full version of MC ucode,
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: jimqu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Tue, 21 Mar 2017 02:09:33 +0000 (10:09 +0800)]
drm/amdgpu: fix duplicated code
it could come from branch merge.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 17 Mar 2017 11:04:55 +0000 (19:04 +0800)]
drm/amdgpu: enable gfx/system/vce clockgating on Polars12.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 17 Mar 2017 08:21:55 +0000 (16:21 +0800)]
drm/amd/powerplay: add a new register define for APU in VI.
the ixcurrent_pg_status addr is different between APU and DGPU.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Fri, 12 Aug 2016 17:47:08 +0000 (13:47 -0400)]
drm/amdgpu: enable GFX/UVD/VCE PG for Bristol
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Tue, 9 Aug 2016 22:01:55 +0000 (18:01 -0400)]
drm/amd/amdgpu: Set VCE/UVD off during late init
Forces VCE/UVD off during late init to ensure they're powered off
correctly during boot.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 17 Mar 2017 14:37:22 +0000 (14:37 +0000)]
drm/amdgpu: remove redundant outer loop and remove commented out code
The outer loop is redundant and can be removed as it is doing nothing
useful. Also remove some commented out code that is not being used.
Detected by CoverityScan, CID#
1402073
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 16 Mar 2017 03:44:49 +0000 (11:44 +0800)]
drm/amd/sched: revise priority number
big number is to high priority.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 16 Mar 2017 14:45:58 +0000 (10:45 -0400)]
drm/amdgpu: bump version for PRT support
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Thu, 16 Mar 2017 08:09:24 +0000 (16:09 +0800)]
drm/amdgpu: fix before and after mapping judgement for replace mapping
If the before mapping is 1 page size, so its start and last will be same.
Thus below condition will become false, then to free the before mapping.
> if (before->it.start != before->it.last)
But in this case, we need the before mapping of 1 page size.
So does after mapping.
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 13 Mar 2017 09:13:39 +0000 (10:13 +0100)]
drm/amdgpu: add a VM mapping replace operation v2
Add a new operation to replace mappings in a VM with a new one.
v2: Fix Jerry's comment, separate out clear operation.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 13 Mar 2017 09:13:38 +0000 (10:13 +0100)]
drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2
A new VM operation to remove all mappings in a range.
v2: limit unmapped area as noted by Jerry
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 13 Mar 2017 09:13:37 +0000 (10:13 +0100)]
drm/amdgpu: separate page table allocation from mapping
This makes it easier to implement a replace operation.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 13 Mar 2017 09:13:36 +0000 (10:13 +0100)]
drm/amdgpu: make set_prt callback optional and fix error handling
PRT support is completely implemented now and we left it
turned on accidentially in the error path.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 16 Mar 2017 02:05:20 +0000 (22:05 -0400)]
drm/amdgpu/vi: add missing error handling when setting uvd dclk
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 16 Mar 2017 02:03:08 +0000 (22:03 -0400)]
drm/amdgpu/vi: remove duplicate CG flags
GFX_MGLS was added twice.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrew F. Davis [Wed, 15 Mar 2017 16:20:24 +0000 (11:20 -0500)]
drm/amd/powerplay: remove unneeded conversions to bool
Found with scripts/coccinelle/misc/boolconv.cocci.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrew F. Davis [Wed, 15 Mar 2017 16:20:23 +0000 (11:20 -0500)]
drm/amdgpu: remove unneeded conversions to bool
Found with scripts/coccinelle/misc/boolconv.cocci.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andres Rodriguez [Sat, 11 Mar 2017 15:50:34 +0000 (10:50 -0500)]
drm/amdgpu: add macro to retrieve timeline name v2
This helps de-duplicate a long expression and removes overly long lines.
v2: Rename macro and undef it
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andres Rodriguez [Fri, 10 Mar 2017 02:25:54 +0000 (21:25 -0500)]
drm/amdgpu: replace fence pointer with fence data in traces
Fence data is easier to read and allows us to correlate to identify
corresponding dma_fence ftrace events.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andres Rodriguez [Fri, 10 Mar 2017 02:25:53 +0000 (21:25 -0500)]
drm/amdgpu: remove useless pointers from traces
Remove pointers which provide redundant information which is already
easier to deduce from other fields.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andres Rodriguez [Fri, 10 Mar 2017 02:25:52 +0000 (21:25 -0500)]
drm/amdgpu: use sched_job id instead of pointer for tracing
Pointers get reallocated and they are hard to read for humans. Use ids
instead.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andres Rodriguez [Fri, 10 Mar 2017 02:25:51 +0000 (21:25 -0500)]
drm/amdgpu: more ftrace formatting consistency fixes
Consistent formatting makes it easier to read the logs and apply simple
awk oneliners.
I missed some of these on my last patch.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andres Rodriguez [Fri, 10 Mar 2017 02:25:50 +0000 (21:25 -0500)]
drm/amd/sched: add a unique job id to amd_sched_job
A unique id is useful for debugging and tracing. Intended to replace
pointers in ftrace output.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger.He [Tue, 14 Mar 2017 08:47:30 +0000 (16:47 +0800)]
drm/amdgpu: increase IH ring buffer size to avoid overflow
We originally limited the IH to 4k on tonga since it
uses bus addresses directly rather than GPU MC addresses,
so it needs contigous physical memory. This brings it
inline with other asics.
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 15 Mar 2017 13:45:48 +0000 (09:45 -0400)]
drm/amdgpu: don't init GDS pool if GDS size is 0 (v2)
SI cards don't expose GDS as a separate pool. The CP manages
GDS and the UMDs use special CP packets to allocate GDS memory.
v2: drop extra whitespace change
bug: https://bugzilla.kernel.org/show_bug.cgi?id=194867
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 15 Mar 2017 13:42:03 +0000 (09:42 -0400)]
drm/amdgpu/gfx6: drop gds unrefs
Leftover from gfx7 code. gfx6 never sets up the gds buffers
in the first place.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 13 Mar 2017 08:05:32 +0000 (16:05 +0800)]
drm/amdgpu: refine vce_3.0 code.
fix logic error in hw_fini and
set_clockgating_state functions.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 6 Mar 2017 03:29:26 +0000 (11:29 +0800)]
drm/amdgpu: refine vce2.0 dpm sequence
start vce first then enable vce dpm.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Mar 2017 20:41:54 +0000 (15:41 -0500)]
drm/radeon: add new ATIF ACPI method
Used for fetching external GPU information.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Mar 2017 20:34:34 +0000 (15:34 -0500)]
drm/amdgpu: add new ATIF ACPI method
Used for fetching external GPU information.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 10 Jan 2017 16:57:24 +0000 (11:57 -0500)]
drm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 10 Jan 2017 16:50:08 +0000 (11:50 -0500)]
drm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 10 Jan 2017 16:49:08 +0000 (11:49 -0500)]
uapi/drm: add AMDGPU_HW_IP_UVD_ENC
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 12 Jan 2017 18:19:46 +0000 (13:19 -0500)]
drm/amdgpu: add uvd enc ring type and functions
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 12 Jan 2017 18:15:37 +0000 (13:15 -0500)]
drm/amdgpu: add uvd enc run queue
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 10 Jan 2017 16:23:23 +0000 (11:23 -0500)]
drm/amdgpu: add uvd enc rings
And initialize them
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 10 Jan 2017 16:02:58 +0000 (11:02 -0500)]
drm/amdgpu: move amdgpu_vce structure to vce header
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 2 Jan 2017 15:07:33 +0000 (10:07 -0500)]
drm/amdgpu: move amdgpu_uvd structure to uvd header
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 14 Dec 2016 20:05:00 +0000 (15:05 -0500)]
drm/amdgpu: add a ring func for end command
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 17 Jan 2017 02:18:31 +0000 (10:18 +0800)]
drm/amdgpu: add DF MGCG flag
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 18 Jan 2017 08:53:16 +0000 (16:53 +0800)]
drm/amdgpu: add DRM MGCG header
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Mar 2017 22:26:10 +0000 (17:26 -0500)]
drm/amdgpu: add asic callback to get memsize register
Newer asics use different registers so abstract it.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 22 Feb 2017 07:33:46 +0000 (15:33 +0800)]
drm/amdgpu: check function points valid before use. (v3)
v2: agd: integrate Christian's comments.
v3: print error message if call fails
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Tue, 14 Feb 2017 17:22:57 +0000 (12:22 -0500)]
drm/amdgpu: add a callback to set vm mapping flags
This lets each asic set whichever flags it supports.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Tue, 14 Feb 2017 17:31:36 +0000 (12:31 -0500)]
drm/amdgpu: set GART PTE asic specific flags
Set asic specific gart pte flags in the gmc IP module for
each asic.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 10 Oct 2016 07:19:06 +0000 (15:19 +0800)]
drm/amdgpu: add a ucode size member into firmware info
This will be used for newer asics.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Wed, 21 Sep 2016 08:19:19 +0000 (16:19 +0800)]
drm/amdgpu: expand pte flags to uint64_t
Necessary for new asics.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 29 Nov 2016 23:02:12 +0000 (18:02 -0500)]
drm/amdgpu/ih: store the full context id
The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics. Expand the
src_id field to handle this.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 29 Mar 2016 22:28:50 +0000 (18:28 -0400)]
drm/amdgpu: switch ih handling to two levels (v3)
Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP
v2: integrated Christian's comments.
v3: fix rebase fail in SI and CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / log