Arnd Bergmann [Thu, 18 Apr 2013 21:57:26 +0000 (23:57 +0200)]
irqchip: exynos: look up irq using irq_find_mapping
Since we want to move to using the linear IRQ domain in the
future, we cannot rely on the irq numbers to be contiguous
and need to look up the irq from the hwirq using the domain.
This also turns the bogus comparison with NR_IRQ into a
more meaningful check to see if the number has a valid mapping.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Fri, 12 Apr 2013 13:27:09 +0000 (15:27 +0200)]
irqchip: exynos: pass irq_base from platform
The platform code knows the IRQ base, while the irqchip driver
should really not. This is a littly hacky because we still
hardwire the IRQ base to 160 for the combiner in the DT case,
when we should really use -1. Removing that line will cause
a linear IRQ domain to be use, as we should.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Arnd Bergmann [Wed, 10 Apr 2013 13:59:58 +0000 (15:59 +0200)]
irqchip: exynos: localize irq lookup for ATAGS
The IRQ_SPI() macro is not available in the driver when building with sparse
IRQs or multiplatform, so let's move all users of this into one function
that we can leave out when building DT-only.
Signed-off-by: Arnd Bergmann <arnd@arnd.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Arnd Bergmann [Wed, 10 Apr 2013 13:31:11 +0000 (15:31 +0200)]
irqchip: exynos: allocate combiner_data dynamically
The number of combiners on a given SoC is a platform specific
constant, and we cannot encode this number on a multiplatform
kernel since the header file defining it is not available.
Allocating the structure dynamically ends up cleaner anyway
since we keep all the data local.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Arnd Bergmann [Wed, 10 Apr 2013 13:17:47 +0000 (15:17 +0200)]
irqchip: exynos: pass max combiner number to combiner_init
We can find out the number of combined IRQs from the device
tree, but in case of ATAGS boot, the driver currently uses
hardcoded values based on the SoC type. We can't do that
in general for a multiplatform kernel, so let's instead pass
this information from platform code directly in case of
ATAGS boot.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Arnd Bergmann [Fri, 12 Apr 2013 13:15:58 +0000 (15:15 +0200)]
ARM: exynos: add missing properties for combiner IRQs
The exynos combiner irqchip needs to find the parent interrupts
and needs to know their number, so add the missing properties
for exynos4 as they were already present for exynos5.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 10 Apr 2013 09:35:29 +0000 (11:35 +0200)]
clocksource: exynos_mct: remove platform header dependency
For the non-DT case, the mct_init() function requires access
to a couple of platform specific constants, but cannot include
the header files in case we are building for multiplatform.
This changes the interface to the platform so we pass all
the necessary data as arguments to mct_init.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: John Stultz <john.stultz@linaro.org>
Arnd Bergmann [Wed, 10 Apr 2013 09:31:44 +0000 (11:31 +0200)]
clk: exynos: prepare for multiplatform
The new common clock drivers for exynos are using compile
time constants and soc_is_exynos* macros to provide backwards
compatibility for pre-DT systems, which is not possible with
multiplatform kernels. This moves all the necessary
information back into platform code and removes the mach/*
header inclusions.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Mike Turquette <mturquette@linaro.org>
Arnd Bergmann [Fri, 19 Apr 2013 20:00:04 +0000 (22:00 +0200)]
clocksource: exynos_mct: fix build error on non-DT
There is currently no alternative implementation for of_irq_count
when the function is not defined, and the declaration is hidden,
so this works around calling an undeclared function. It should
really not be needed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Axel Lin [Tue, 9 Apr 2013 15:59:58 +0000 (23:59 +0800)]
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
pinctrl_register() returns NULL on error.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Arnd Bergmann [Fri, 19 Apr 2013 12:34:05 +0000 (14:34 +0200)]
Merge branch 'samsung/exynos-multiplatform' into next/drivers
Merging this into the next/drivers branch avoids a number of
pointless conflicts with code changed here.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Wed, 10 Apr 2013 12:57:15 +0000 (14:57 +0200)]
ARM: exynos: enable multiplatform support
This makes it possible to enable the exynos platform as part of a
multiplatform kernel, in addition to keeping the single-platform
exynos support.
The multiplatform variant has a number of limitations at the moment:
* It only supports DT-enabled machines. This is not a problem in
the long run, as non-DT machines for exynos are going away.
The main problem here is that the gpio code and the exynos_eint
irqchip are not multiplatform capable but still required for
ATAGS based boot.
* The watchdog driver is still missing a conversion.
* sparsemem and memory_holes are currently not supported in
multiplatform.
The the multiplatform aware ARCH_EXYNOS Kconfig symbol is disabled
for now, as dependent patches are still pending in other
subsystem trees. We will enable it once everything comes together.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 5 Mar 2013 11:04:37 +0000 (12:04 +0100)]
rtc: s3c: make header file local
Nothing outside of the rtc driver includes plat/regs-rtc.h,
so we can simply move the file into the same directory,
which allows us to build the file as platform-independent
code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: rtc-linux@googlegroups.com
Cc: Alessandro Zummo <a.zummo@towertech.it>
Arnd Bergmann [Tue, 5 Mar 2013 11:14:17 +0000 (12:14 +0100)]
mtd: onenand/samsung: make regs-onenand.h file local
Nothing uses the NAND register definitions other than the
actual driver, so we can move the header file into the
same local directory, which lets us build it in a multiplatform
configuration.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: linux-mtd@lists.infradead.org
Cc: David Woodhouse <dwmw2@infradead.org>
Arnd Bergmann [Tue, 5 Mar 2013 09:44:54 +0000 (10:44 +0100)]
thermal/exynos: remove unnecessary header inclusions
In multiplatform configurations, we cannot include headers
provided by only the exynos platform. Fortunately a number
of drivers that include those headers do not actually need
them, so we can just remove the inclusions.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Eduardo Valentin <eduardo.valentin@ti.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Arnd Bergmann [Mon, 4 Mar 2013 17:28:21 +0000 (18:28 +0100)]
mmc: sdhci-s3c: remove platform dependencies
plat/regs-sdhci.h is not used anywhere but in the sdhci-s3c
driver, so it can become a local file there and all other
inclusions removed.
plat/sdhci.h is used only to define the platform devices,
and with the exception of the platform_data structure not
needed by the driver, so we can split out the platform_data
definition instead and leave the rest to platform code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Chris Ball <cjb@laptop.org>
Arnd Bergmann [Wed, 10 Apr 2013 12:49:03 +0000 (14:49 +0200)]
ARM: samsung: move mfc device definition to s5p-dev-mfc.c
For a DT-only build we don't want to compile devs.c, but we do need
the mfc device, which is also referenced by the DT based platforms,
so move it all into one place.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 4 Mar 2013 17:03:10 +0000 (18:03 +0100)]
ARM: exynos: move debug-macro.S to include/debug/
The move is necessary to support early debug output on exynos
with multiplatform configurations. This implies also moving the
plat/debug-macro.S file, but we are leaving the remaining users of that
file in place, to avoid adding large numbers of extra configuration
options to Kconfig.debug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 5 Mar 2013 10:28:29 +0000 (11:28 +0100)]
ARM: exynos: prepare for sparse IRQ
When we enable CONFIG_SPARSE_IRQ, we have to set the value of NR_IRQS in
the machine_desc for legacy IRQ domains, and any file referring to the
number of interrupts or a specific number must include the mach/irqs.h
header file explicitly.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 11 Apr 2013 21:13:27 +0000 (23:13 +0200)]
ARM: exynos: introduce EXYNOS_ATAGS symbol
As a preparation for multiplatform support, this introduces
a new Kconfig symbol to split the ATAGS based EXYNOS platforms
from the DT based ones. Turning off CONFIG_EXYNOS_ATAGS disables
all platforms that are not yet converted to DT, and we can
have code that relies on DT checking for this symbol being
disabled.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Olof Johansson [Sat, 13 Apr 2013 06:06:37 +0000 (23:06 -0700)]
Merge branch 'reset/for_v3.10' of git://git.pengutronix.de/git/pza/linux into next/drivers
From Philipp Zabel, this is a series that adds a simple API for devices
to request being reset by a separate reset controller hardware, and
it implements reset signal device tree bindings.
* 'reset/for_v3.10' of git://git.pengutronix.de/git/pza/linux:
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
Signed-off-by: Olof Johansson <olof@lixom.net>
Tony Prisk [Sun, 24 Mar 2013 01:12:25 +0000 (01:12 +0000)]
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
This patch moves the arch-vt8500 irq code to drivers/irqchip and converts
it to use the new IRQCHIP_DECLARE and irqchip_init. This allows the removal
of some more functions from common.h
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Olof Johansson <olof@lixom.net>
Dan Carpenter [Wed, 3 Apr 2013 05:02:53 +0000 (08:02 +0300)]
reset: NULL deref on allocation failure
"rstc" is NULL here and we should use "rcdev" instead of "rstc->rcdev".
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Philipp Zabel [Mon, 19 Nov 2012 16:23:13 +0000 (17:23 +0100)]
reset: Add reset controller API
This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Stephen Warren [Tue, 23 Oct 2012 21:45:56 +0000 (15:45 -0600)]
dt: describe base reset signal binding
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
It consists of a binding for a reset controller device (provider), and a
pair of properties, "resets" and "reset-names", to link a device node
(consumer) to its reset controller via phandle, similarly to the clock
and interrupt bindings.
The reset controller has all information necessary to reset the consumer
device. That could be provided via device tree, or it could be implemented
in hardware.
The aim is to enable device drivers to request a framework API to issue a
reset simply by providing their struct device pointer as the most common
case.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Arnd Bergmann [Tue, 9 Apr 2013 20:47:38 +0000 (22:47 +0200)]
Merge tag 'timer-samsung-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
including fix for GENERIC_GPIO based on previous pull-request for timer-samsung
* tag 'timer-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: change GENERIC_GPIO to ARCH_REQUIRE_GPIOLIB
Signed-off-by: Arnd Bergmann <arnd@anrdb.de>
Arnd Bergmann [Tue, 9 Apr 2013 20:46:16 +0000 (22:46 +0200)]
Merge tag 'pmu-exynos-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add support arm-pmu for exynos4 and exynos5250
* tag 'pmu-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 20:24:06 +0000 (22:24 +0200)]
Merge tag 'clk-exynos-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add suppport common clock framework for exynos
* tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits)
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: exynos5250: register display block gate clocks to common clock framework
clk: exynos4: Add support for SoC-specific register save list
clk: exynos4: Add missing registers to suspend save list
clk: exynos4: Remove E4X12 prefix from SRC_DMC register
clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
clk: exynos4: Add E4210 prefix to LCD1 clock registers
clk: exynos4: Remove SoC-specific registers from save list
clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
clk: exynos4: Define {E,V}PLL registers
clk: exynos4: Add missing mout_sata on Exynos4210
clk: exynos4: Add missing CMU_TOP and ISP clocks
clk: exynos4: Add G3D clocks
clk: exynos4: Add camera related clock definitions
clk: exynos4: Export mout_core clock of Exynos4210
clk: samsung: Remove unimplemented ops for pll
clk: exynos4: Export clocks used by exynos cpufreq drivers
...
[arnd: add missing #address-cells property in mshc DT node]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 20:07:37 +0000 (22:07 +0200)]
Merge tag 'mct-exynos-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add support exynos mct device tree and move into drivers/clocksource
* tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: mct: Add terminating entry for exynos_mct_ids table
clocksource: mct: Add missing semicolons in exynos_mct.c
ARM: EXYNOS: move mct driver to drivers/clocksource
ARM: EXYNOS: remove static io-remapping of mct registers for Exynos5
ARM: dts: add mct device tree node for all supported Exynos SoC's
ARM: EXYNOS: allow dt based discovery of mct controller using clocksource_of_init
ARM: EXYNOS: add device tree support for MCT controller driver
ARM: EXYNOS: prepare an array of MCT interrupt numbers and use it
ARM: EXYNOS: add a register base address variable in mct controller driver
Conflicts:
drivers/clocksource/Makefile
drivers/clocksource/exynos_mct.c
[arnd: adapt to CLOCKSOURCE_OF_DECLARE interface change]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 20:05:50 +0000 (22:05 +0200)]
Merge tag 'irq-s3c24xx-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
s3c24xx irq cleanup and move into drivers/irqchip
* tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
irqchip: s3c24xx: add devicetree support
irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
irqchip: s3c24xx: globally keep track of the created intc instances
irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
irqchip: s3c24xx: fix irqlist of second s3c2416 controller
irqchip: s3c24xx: fix comments on some camera interrupts
ARM: S3C24XX: move irq driver to drivers/irqchip
ARM: S3C24XX: add handle_irq function
ARM: S3C24XX: make s3c24xx_init_intc static
ARM: S3C24XX: move s3c24xx_init_irq to s3c2410_init_irq
ARM: S3C24XX: fix irq parent check
ARM: S3C24XX: fix redundant checks in the irq mapping function
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:57:39 +0000 (17:57 +0200)]
Merge tag 'ux500-pinctrl' of git://git./linux/kernel/git/linusw/linux-stericsson into next/drivers
From Linus Walleij <linus.walleij@linaro.org>:
ux500 pinctrl updates for the ARM SoC tree.
* tag 'ux500-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: 8500: add ab8500-musb pinctrl support
ARM: ux500: remove redundant DB8500_PIN_SLEEP definition
ARM: ux500: Add Snowball pin configuration for user LED
ARM: ux500: u8500: fix pinctrl IDLE state definition for SPI2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:10:31 +0000 (17:10 +0200)]
Merge tag 'tegra-for-3.10-clk' of git://git./linux/kernel/git/swarren/linux-tegra into next/drivers
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: clock driver development
This branch contains most fixes and enhancements to the Tegra common
clock driver. The main new feature is a driver for Tegra114, which
coupled with later device tree changes enables many devices on that
chip, such as MMC, I2C, etc.
This branch depends on a patch in:
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
Mike has stated that this branch is stable, and is aware of this
dependency and merge.
Mike's branch is based on v3.9-rc3, which includes a USB change which
causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence,
this branch pulls in v3.9-rc4 to ensure bisectability as much as
possible.
This branch is based on v3.9-rc4, followed by a merge of previous Tegra
"soc" pull request, followed by a merge of clk-for-3.10.
* tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
clk: tegra: fix enum tegra114_clk to match binding
clk: tegra: Remove forced clk_enable of uartd
ARM: dt: Add references to tegra_car clocks
clk: tegra: devicetree match for nvidia,tegra114-car
clk: tegra: Implement clocks for Tegra114
ARM: tegra: Define Tegra114 CAR binding
clk: tegra: Workaround for Tegra114 MSENC problem
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: move from a lock bit idx to a lock mask
clk: tegra: Add PLL post divider table
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: Refactor PLL programming code
clk: tegra: provide dummy cpu car ops
clk: tegra: defer application of init table
clk: tegra: Fix cdev1 and cdev2 IDs
clk: tegra: Make gr2d and gr3d clocks children of pll_c
clk: tegra: Export peripheral reset functions
clk: tegra: Fix periph_clk_to_bit macro
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:09:35 +0000 (17:09 +0200)]
Merge branch 'depends/clk' into next/drivers
This is a snapshot of the stable clk branch at
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
which is a dependency for the tegra clock changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:07:36 +0000 (17:07 +0200)]
Merge branch 'tegra/soc' into next/drivers
This is a dependency for the tegra/clk branch.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conflicts:
drivers/clocksource/tegra20_timer.c
Arnd Bergmann [Mon, 8 Apr 2013 17:40:57 +0000 (19:40 +0200)]
Merge tag 'omap-for-v3.10/gpmc-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
GPMC updates from Jon Hunter <jon-hunter@ti.com>:
Adds GPMC (General Purpose Memory Controller) DT support for
NOR flash and Ethernet and includes various GPMC cleans-up
and fixes.
This series is dependent on commit
7185684 (ARM: OMAP: use
consistent error checking) from RMK's clean-up branch and commit
31d9adc (ARM: OMAP2+: Fix broken gpmc support).
* tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits)
ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes
ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child()
ARM: OMAP2+: return -ENODEV if GPMC child device creation fails
ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails
ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable
ARM: OMAP2+: Detect incorrectly aligned GPMC base address
ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT
ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT
ARM: OMAP2+: Add device-tree support for NOR flash
ARM: OMAP2+: Add additional GPMC timing parameters
ARM: OMAP2+: Add function to read GPMC settings from device-tree
ARM: OMAP2+: Don't configure of chip-select options in gpmc_cs_configure()
ARM: OMAP2+: Convert TUSB to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert SMC91x to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert NAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert ONENAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Add function for configuring GPMC settings
ARM: OMAP2+: Add structure for storing GPMC settings
ARM: OMAP2+: Add variable to store number of GPMC waitpins
ARM: OMAP2+: Simplify code configuring ONENAND devices
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 17:30:48 +0000 (19:30 +0200)]
Merge tag 'omap-for-v3.10/timer-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>:
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on
7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and
960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of
7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
* tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Fix sparse warning in system timers
ARM: OMAP2+: Store ID of system timers in timer structure
ARM: OMAP3: Update clocksource timer selection
ARM: OMAP2+: Simplify system timers definitions
ARM: OMAP2+: Simplify system timer clock definitions
ARM: OMAP2+: Remove hard-coded test on timer ID
ARM: OMAP2+: Display correct system timer name
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 17:06:51 +0000 (19:06 +0200)]
Merge tag 'omap-for-v3.10/usb-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
EHCI platform data related changes for v3.10 merge window.
These are needed for the USB PHY support, and are based on
commit
1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
* tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-beagle: Add USB Host support
ARM: dts: OMAP3: Add HS USB Host IP nodes
ARM: dts: OMAP4: Add HS USB Host IP nodes
ARM: OMAP: zoom: Adapt to ehci-omap changes
ARM: OMAP3: overo: Adapt to ehci-omap changes
ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
ARM: OMAP3: igep0020: Adapt to ehci-omap changes
ARM: OMAP: devkit8000: Adapt to ehci-omap changes
ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
ARM: OMAP3: Beagle: Adapt to ehci-omap changes
ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Chanho Park [Wed, 12 Dec 2012 05:04:03 +0000 (14:04 +0900)]
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
This patch adds a arm-pmu node to bind device tree for exynos4210.
The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the
exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type
board. However, supporting arm-pmu for the exynos4412 will handle it later
because there is no dts support for 4412 based board.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Chanho Park [Wed, 12 Dec 2012 05:03:59 +0000 (14:03 +0900)]
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Chanho Park [Wed, 12 Dec 2012 05:03:54 +0000 (14:03 +0900)]
ARM: EXYNOS: Enable PMUs for exynos4
This patch defines irq numbers of ARM performance monitoring unit for exynos4.
Firs of all, we need to fix IRQ_PMU correctly and to split pmu initialization
of exynos from plat-samsung for easily defining it.
The number of CPU cores and PMU irq numbers are vary according to soc types.
So, we need to identify each soc type using soc_is_xxx function and to define
the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and pmus.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Chanho Park [Wed, 12 Dec 2012 05:02:49 +0000 (14:02 +0900)]
irqchip: exynos-combiner: Correct combined IRQs for exynos4
This patch corrects combined IRQs for exynos4 series platform. The exynos4412
has four extra combined irq group and the exynos4212 has two more combined
irqs
than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4
combined IRQs isn't sequential. So, we need to map the irqs manually.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: changes moved into drivers/irqchip/]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Chanho Park [Wed, 12 Dec 2012 05:02:45 +0000 (14:02 +0900)]
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the pmu of exynos has combined type
irqs.
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: changes moved into drivers/irqchip/]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Arnd Bergmann [Mon, 8 Apr 2013 16:34:19 +0000 (18:34 +0200)]
Merge branch 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx into next/drivers
From Michal Simek <michal.simek@xilinx.com>:
* 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Move timer to generic location
arm: zynq: Do not use xilinx specific function names
arm: zynq: Move timer to clocksource interface
arm: zynq: Use standard timer binding
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 16:26:15 +0000 (18:26 +0200)]
Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into next/drivers
From Tony Prisk <linux@prisktech.co.nz>:
arm: vt8500: Add pinctrl driver for arch-vt8500
This series adds support for the pinctrl/gpio module on all arch-vt8500
supported SoCs.
As part of the review process, some tidy up is also done to
drivers/of/base.c to remove some code that is being constantly duplicated.
Also, a patch for the bcm2835 pinctrl driver is included to take advantage
of the new of/base.c code.
* tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits)
pinctrl: bcm2835: make use of of_property_read_u32_index()
gpio: vt8500: Remove arch-vt8500 gpio driver
arm: vt8500: Remove gpio devicetree nodes
arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
arm: vt8500: Increase available GPIOs on arch-vt8500
of: Remove duplicated code for validating property and value
of: Add support for reading a u32 from a multi-value property.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kukjin Kim [Mon, 8 Apr 2013 16:10:13 +0000 (01:10 +0900)]
Merge commit 'v3.9-rc5' into next/clk-exynos
Conflicts:
arch/arm/boot/dts/exynos4.dtsi
arch/arm/boot/dts/exynos5440.dtsi
Arnd Bergmann [Mon, 8 Apr 2013 15:52:35 +0000 (17:52 +0200)]
Merge tag 'renesas-intc-external-irq2-for-v3.10' of git://git./linux/kernel/git/horms/renesas into next/drivers
From Simon Horman <horms+renesas@verge.net.au>:
Update for Renesas INTC External IRQ pin driver for v3.10
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
* tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
irqchip: intc-irqpin: Add support for shared interrupt lines
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Thomas Abraham [Fri, 5 Apr 2013 06:17:47 +0000 (15:17 +0900)]
ARM: EXYNOS: fix compilation error introduced due to common clock migration
The functions exynos4_clk_init and exynos4_clk_register_fixed_ext
are applicable only on Exynos4 non-dt platforms. But when building
Exynos5 platforms without including Exynos4 platforms, the following
errors show up.
arch/arm/mach-exynos/built-in.o: In function `exynos_init_time':
arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init'
arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext'
Fix this compilation errors by marking these calls as Exynos4 specific.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tushar Behera [Mon, 8 Apr 2013 06:28:12 +0000 (15:28 +0900)]
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.
With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.
dwmmc_exynos
12200000.dwmmc0: data FIFO error (status=
00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Sylwester Nawrocki [Mon, 8 Apr 2013 06:24:47 +0000 (15:24 +0900)]
clk: exynos4: export clocks required for fimc-is
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Sachin Kamat [Mon, 8 Apr 2013 12:35:25 +0000 (21:35 +0900)]
clk: samsung: Fix compilation error
Fixes the below compilation error during non-dt build.
drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext':
drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration]
drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Wei Yongjun [Fri, 5 Apr 2013 06:58:52 +0000 (14:58 +0800)]
ARM: tegra: pm: remove duplicated include from pm.c
Remove duplicated include.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Thu, 4 Apr 2013 23:13:54 +0000 (17:13 -0600)]
clk: tegra: fix enum tegra114_clk to match binding
A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:
ERROR: could not get clock /pmc:pclk(0)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:49 +0000 (17:40 +0300)]
clk: tegra: Remove forced clk_enable of uartd
The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:48 +0000 (17:40 +0300)]
ARM: dt: Add references to tegra_car clocks
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:46 +0000 (17:40 +0300)]
clk: tegra: devicetree match for nvidia,tegra114-car
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:45 +0000 (17:40 +0300)]
clk: tegra: Implement clocks for Tegra114
Implement clocks for Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Thu, 4 Apr 2013 17:48:28 +0000 (20:48 +0300)]
ARM: tegra: Define Tegra114 CAR binding
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:44 +0000 (17:40 +0300)]
clk: tegra: Workaround for Tegra114 MSENC problem
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:42 +0000 (17:40 +0300)]
clk: tegra: Add flags to tegra_clk_periph()
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:41 +0000 (17:40 +0300)]
clk: tegra: Add new fields and PLL types for Tegra114
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:40 +0000 (17:40 +0300)]
clk: tegra: move from a lock bit idx to a lock mask
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:39 +0000 (17:40 +0300)]
clk: tegra: Add PLL post divider table
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:38 +0000 (17:40 +0300)]
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:37 +0000 (17:40 +0300)]
clk: tegra: Add TEGRA_PLL_BYPASS flag
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:36 +0000 (17:40 +0300)]
clk: tegra: Refactor PLL programming code
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:35 +0000 (17:40 +0300)]
clk: tegra: provide dummy cpu car ops
tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 25 Mar 2013 19:22:24 +0000 (13:22 -0600)]
clk: tegra: defer application of init table
The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.
The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.
To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Thu, 4 Apr 2013 09:05:04 +0000 (14:35 +0530)]
clk: tegra: Fix cdev1 and cdev2 IDs
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Tue, 2 Apr 2013 14:18:44 +0000 (16:18 +0200)]
clk: tegra: Make gr2d and gr3d clocks children of pll_c
By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.
gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Thu, 28 Mar 2013 20:31:27 +0000 (21:31 +0100)]
clk: tegra: Export peripheral reset functions
The tegra_periph_reset_assert() and tegra_periph_reset_deassert()
functions can be used by drivers to reset peripherals. In order to allow
such drivers to be built as modules, export the functions.
Note that this restores the status quo as the functions were exported
before the move to the drivers/clk tree.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Yen Lin [Wed, 6 Mar 2013 11:47:24 +0000 (11:47 +0000)]
clk: tegra: Fix periph_clk_to_bit macro
The parameter name should be "gate", not "periph". This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Thu, 4 Apr 2013 22:08:13 +0000 (16:08 -0600)]
Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into for-3.10/clk
Stephen Warren [Thu, 4 Apr 2013 22:08:06 +0000 (16:08 -0600)]
Merge branch 'for-3.10/soc' into for-3.10/clk
Tony Lindgren [Thu, 4 Apr 2013 18:22:33 +0000 (11:22 -0700)]
Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux into omap-for-v3.10/gpmc
Michal Simek [Wed, 20 Mar 2013 09:46:01 +0000 (10:46 +0100)]
arm: zynq: Move timer to generic location
Move zynq timer out of mach folder to generic location
and enable it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 27 Mar 2013 11:05:28 +0000 (12:05 +0100)]
arm: zynq: Do not use xilinx specific function names
Remove all xilinx specific names from the driver
because this is generic driver for cadence ttc.
xttc->ttc
ttcps->ttc
...
No functional changes in this driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 20 Mar 2013 09:24:59 +0000 (10:24 +0100)]
arm: zynq: Move timer to clocksource interface
Use clocksource timer initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 20 Mar 2013 09:15:28 +0000 (10:15 +0100)]
arm: zynq: Use standard timer binding
Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.
Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Leela Krishna Amudala [Thu, 4 Apr 2013 06:44:40 +0000 (15:44 +0900)]
clk: exynos5250: register display block gate clocks to common clock framework
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi.
Register it to common clock framework.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:35:35 +0000 (13:35 +0900)]
clk: exynos4: Add support for SoC-specific register save list
This patch extends suspend/resume support for SoC-specific registers to
handle differences in register sets on particular SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:35:32 +0000 (13:35 +0900)]
clk: exynos4: Add missing registers to suspend save list
This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:35:27 +0000 (13:35 +0900)]
clk: exynos4: Remove E4X12 prefix from SRC_DMC register
This register is present on all Exynos4 SoCs and so the prefix is
misleading.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:35:22 +0000 (13:35 +0900)]
clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:35:18 +0000 (13:35 +0900)]
clk: exynos4: Add E4210 prefix to LCD1 clock registers
This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:37 +0000 (13:33 +0900)]
clk: exynos4: Remove SoC-specific registers from save list
Current clock save list is shared for all Exynos4 SoCs, so it must
contain only registers present in all supported SoCs, because accessing
unavailable registers might have undefined effect.
This patch removes registers specific for particular SoCs from shared
save list, as they should be supported by separate SoC-specific lists.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:34 +0000 (13:33 +0900)]
clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers,
but they are not used for clock definitions. This patch modifies related
clock definitions to use defined macros instead of numeric offsets.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:30 +0000 (13:33 +0900)]
clk: exynos4: Define {E,V}PLL registers
This patch adds preprocessor definitions of EPLL and VPLL registers and
replaces all occurences of offsets of related registers with new
definitions.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:27 +0000 (13:33 +0900)]
clk: exynos4: Add missing mout_sata on Exynos4210
This patch adds missing mout_sata that is a parent of div_sata clock.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Andrzej Hajda [Thu, 4 Apr 2013 04:33:22 +0000 (13:33 +0900)]
clk: exynos4: Add missing CMU_TOP and ISP clocks
The patch adds missing clocks to TOP and ISP clock domains.
It also adds clock gates for ISP sub-blocks.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:17 +0000 (13:33 +0900)]
clk: exynos4: Add G3D clocks
This patch adds clocks needed for G3D block present on Exynos 4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Sylwester Nawrocki [Thu, 4 Apr 2013 04:33:12 +0000 (13:33 +0900)]
clk: exynos4: Add camera related clock definitions
This patch adds several gate and mux clocks related to camera and ISP
blocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:08 +0000 (13:33 +0900)]
clk: exynos4: Export mout_core clock of Exynos4210
This patch enables clock lookup registration for mout_core clock used in
Exynos4210 cpufreq driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:33:02 +0000 (13:33 +0900)]
clk: samsung: Remove unimplemented ops for pll
Unimplemented clock operations should be simply omitted instead of returning
error values.
This patch removes unimplemented PLL operations to fix problems caused
by returning error code in round_rate callback.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Lukasz Majewski [Thu, 4 Apr 2013 04:32:59 +0000 (13:32 +0900)]
clk: exynos4: Export clocks used by exynos cpufreq drivers
This patch exports clocks used by Exynos cpufreq drivers to allow lookup
using device tree. (Support to cpufreq drivers will be added in further
patches.)
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:32:55 +0000 (13:32 +0900)]
clk: exynos4: Move dac and mixer to Exynos4210-specific clocks
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:32:51 +0000 (13:32 +0900)]
clk: exynos4: Export sclk_pcm0
This clock is used by PCM interface 0.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:32:47 +0000 (13:32 +0900)]
clk: exynos4: Add missing sclk_audio0 clock
This clock is a parent of mout_spdif and sclk_pcm0.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:32:43 +0000 (13:32 +0900)]
clk: exynos4: Add missing mout_mipihsi clock
This patch adds missing output of mux MIPIHSI which is needed for
div_mipihsi clock.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Tomasz Figa [Thu, 4 Apr 2013 04:32:37 +0000 (13:32 +0900)]
clk: exynos4: Use mout_mpll_user_* on Exynos4x12
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of
sclk_mpll as one of their parents.
This patch moves such clocks from common array into SoC-specific arrays
and adjusts their parent lists respectively.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Sylwester Nawrocki [Thu, 4 Apr 2013 04:32:33 +0000 (13:32 +0900)]
clk: exynos4: Correct sclk_mfc clock definition
This clock must be exported to allow lookup using device tree.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / log