From: Sakari Ailus Date: Mon, 10 Oct 2011 17:13:26 +0000 (-0300) Subject: [media] omap3isp: Add lane configuration to platform data X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=fe6adc1991b6ce0f6d1c4ca74ec9f02d2d8cb3b4;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [media] omap3isp: Add lane configuration to platform data Add lane configuration (order of clock and data lane) to platform data on both CCP2 and CSI-2. Signed-off-by: Sakari Ailus Acked-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- diff --git a/drivers/media/video/omap3isp/ispcsiphy.h b/drivers/media/video/omap3isp/ispcsiphy.h index 9596dc6830a6..e93a661e65d9 100644 --- a/drivers/media/video/omap3isp/ispcsiphy.h +++ b/drivers/media/video/omap3isp/ispcsiphy.h @@ -27,22 +27,11 @@ #ifndef OMAP3_ISP_CSI_PHY_H #define OMAP3_ISP_CSI_PHY_H +#include + struct isp_csi2_device; struct regulator; -struct csiphy_lane { - u8 pos; - u8 pol; -}; - -#define ISP_CSIPHY2_NUM_DATA_LANES 2 -#define ISP_CSIPHY1_NUM_DATA_LANES 1 - -struct isp_csiphy_lanes_cfg { - struct csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES]; - struct csiphy_lane clk; -}; - struct isp_csiphy_dphy_cfg { u8 ths_term; u8 ths_settle; diff --git a/include/media/omap3isp.h b/include/media/omap3isp.h index 3f4928df6ed0..4d94be5226af 100644 --- a/include/media/omap3isp.h +++ b/include/media/omap3isp.h @@ -90,6 +90,29 @@ enum { ISP_CCP2_MODE_CCP2 = 1, }; +/** + * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity + * @pos: position of the lane + * @pol: polarity of the lane + */ +struct isp_csiphy_lane { + u8 pos; + u8 pol; +}; + +#define ISP_CSIPHY1_NUM_DATA_LANES 1 +#define ISP_CSIPHY2_NUM_DATA_LANES 2 + +/** + * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration + * @data: Configuration of one or two data lanes + * @clk: Clock lane configuration + */ +struct isp_csiphy_lanes_cfg { + struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES]; + struct isp_csiphy_lane clk; +}; + /** * struct isp_ccp2_platform_data - CCP2 interface platform data * @strobe_clk_pol: Strobe/clock polarity @@ -109,6 +132,7 @@ struct isp_ccp2_platform_data { unsigned int ccp2_mode:1; unsigned int phy_layer:1; unsigned int vpclk_div:2; + struct isp_csiphy_lanes_cfg lanecfg; }; /** @@ -119,6 +143,7 @@ struct isp_ccp2_platform_data { struct isp_csi2_platform_data { unsigned crc:1; unsigned vpclk_div:2; + struct isp_csiphy_lanes_cfg lanecfg; }; struct isp_subdev_i2c_board_info {