From: Yoichi Yuasa Date: Tue, 2 Oct 2007 21:19:23 +0000 (-0700) Subject: PCI: fix IDE legacy mode resources X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=fd6e732186ab522c812ab19c2c5e5befb8ec8115;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git PCI: fix IDE legacy mode resources I got the following error on MIPS Cobalt. PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) PCI: Unable to reserve I/O region #3:8@f0000170 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) pata_via 0000:00:09.1: no available native port The legacy mode IDE resources set the following order. pci_setup_device() Legacy mode ATA controllers have fixed addresses. IDE resources: 0x1F0-0x1F7, 0x3F6, 0x170-0x177, 0x376 | V pcibios_fixup_bus() MIPS Cobalt PCI bus regions have the -0x10000000 offset from PCI resources. pcibios_fixup_bus() fix PCI bus regions. 0x1F0 - 0x10000000 = 0xF00001F0 | V ata_pci_init_one() PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 In some architectures, PCI bus regions have the offset from PCI resources. For this reason, pci_setup_device() should set PCI bus regions to dev->resource[]. [akpm@linux-foundation.org: use struct initialiser] Signed-off-by: Yoichi Yuasa Cc: Alan Cox Cc: Greg KH Cc: Bartlomiej Zolnierkiewicz Cc: Ralf Baechle Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 171ca712e523..40e571d3c392 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -744,22 +744,46 @@ static int pci_setup_device(struct pci_dev * dev) */ if (class == PCI_CLASS_STORAGE_IDE) { u8 progif; + struct pci_bus_region region; + pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); if ((progif & 1) == 0) { - dev->resource[0].start = 0x1F0; - dev->resource[0].end = 0x1F7; - dev->resource[0].flags = LEGACY_IO_RESOURCE; - dev->resource[1].start = 0x3F6; - dev->resource[1].end = 0x3F6; - dev->resource[1].flags = LEGACY_IO_RESOURCE; + struct resource resource = { + .start = 0x1F0, + .end = 0x1F7, + .flags = LEGACY_IO_RESOURCE, + }; + + pcibios_resource_to_bus(dev, ®ion, &resource); + dev->resource[0].start = region.start; + dev->resource[0].end = region.end; + dev->resource[0].flags = resource.flags; + resource.start = 0x3F6; + resource.end = 0x3F6; + resource.flags = LEGACY_IO_RESOURCE; + pcibios_resource_to_bus(dev, ®ion, &resource); + dev->resource[1].start = region.start; + dev->resource[1].end = region.end; + dev->resource[1].flags = resource.flags; } if ((progif & 4) == 0) { - dev->resource[2].start = 0x170; - dev->resource[2].end = 0x177; - dev->resource[2].flags = LEGACY_IO_RESOURCE; - dev->resource[3].start = 0x376; - dev->resource[3].end = 0x376; - dev->resource[3].flags = LEGACY_IO_RESOURCE; + struct resource resource = { + .start = 0x170, + .end = 0x177, + .flags = LEGACY_IO_RESOURCE, + }; + + pcibios_resource_to_bus(dev, ®ion, &resource); + dev->resource[2].start = region.start; + dev->resource[2].end = region.end; + dev->resource[2].flags = resource.flags; + resource.start = 0x376; + resource.end = 0x376; + resource.flags = LEGACY_IO_RESOURCE; + pcibios_resource_to_bus(dev, ®ion, &resource); + dev->resource[3].start = region.start; + dev->resource[3].end = region.end; + dev->resource[3].flags = resource.flags; } } break;