From: Dinh Nguyen Date: Tue, 5 Jan 2016 20:59:38 +0000 (-0600) Subject: ARM: dts: socfpga: add the clk-phase property for sd/mmc clock X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=faf68cdfdf6c9f0999686802ad066b1378b89413;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git ARM: dts: socfpga: add the clk-phase property for sd/mmc clock The CIU clock for the SD/MMC should be the sdmmc_clk and not the sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk. Signed-off-by: Dinh Nguyen --- diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1c5e139e4d05..f75dd232ec2e 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -362,6 +362,7 @@ compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; + clk-phase = <0 135>; }; qspi_clk: qspi_clk { @@ -589,7 +590,7 @@ reg = <0xff808000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; status = "disabled"; };