From: Palmer Dabbelt Date: Fri, 23 Jun 2017 20:31:39 +0000 (-0700) Subject: Documentation: atomic_ops.txt is core-api/atomic_ops.rst X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=f5620df7e395465f4eee6c187a4f956b7100b794;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Documentation: atomic_ops.txt is core-api/atomic_ops.rst I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt Acked-by: Will Deacon Acked-by: Paul E. McKenney Signed-off-by: Jonathan Corbet --- diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 732f10ea382e..f1c9eaa45a57 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -498,11 +498,11 @@ And a couple of implicit varieties: This means that ACQUIRE acts as a minimal "acquire" operation and RELEASE acts as a minimal "release" operation. -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE -and RELEASE variants in addition to fully-ordered and relaxed (no barrier -semantics) definitions. For compound atomics performing both a load and a -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply -only to the store portion of the operation. +A subset of the atomic operations described in core-api/atomic_ops.rst have +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no +barrier semantics) definitions. For compound atomics performing both a load +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics +apply only to the store portion of the operation. Memory barriers are only required where there's a possibility of interaction between two CPUs or between a CPU and a device. If it can be guaranteed that